JPS61181151A - Ceramic base body for package of semiconductor device - Google Patents

Ceramic base body for package of semiconductor device

Info

Publication number
JPS61181151A
JPS61181151A JP2115585A JP2115585A JPS61181151A JP S61181151 A JPS61181151 A JP S61181151A JP 2115585 A JP2115585 A JP 2115585A JP 2115585 A JP2115585 A JP 2115585A JP S61181151 A JPS61181151 A JP S61181151A
Authority
JP
Japan
Prior art keywords
lead
leads
lead frame
base body
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2115585A
Other languages
Japanese (ja)
Inventor
Masao Ueda
植田　正夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2115585A priority Critical patent/JPS61181151A/en
Publication of JPS61181151A publication Critical patent/JPS61181151A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To position a lead in a lead frame in the side surface of a base body correctly by previously recessing a section, to which the lead is fixed, while being conformed to the width of the fixing lead. CONSTITUTION:With a base body consisting of ceramics, a recess 1 for loading a semiconductor chip is formed at approximately the center of an upper surface, and an electrode pad and a conductive pattern for the semiconductor chip loaded and fastened to the recess 1 are lead out to the side surface 2 of the base body. The leading-out sections are shaped into recesses 3 into while leads in a lead frame fixed to the leading-out sections intrude. Accordingly, a lead fixing section in the side surface on which hte leads in the lead frame are fastened is recessed previously while being conformed to the width of the fixing leads, thus attaching the leads at correct positions by introducing the fastening the leads in the lead frame to the recesses, then resulting in no positional displacement on heating in post-processes, provided that the yield of products is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体チップを表面側に固着し、側面に’Ｊ
−ド付けを行って、前記半導体チップのパッケージング
を行うために用いる半導体装置パッケージ用セラミック
基体に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a method for fixing a semiconductor chip on the front surface side and forming a 'J' on the side surface.
- A ceramic substrate for a semiconductor device package used for packaging the semiconductor chip by bonding the semiconductor chip.

〔従来の技術〕[Conventional technology]

第２図および第３図は、従来の半導体装置パッケージ用
セラミック基体の側面に、リードフレームのリードを固
着した状態を示す側面図である。FIGS. 2 and 3 are side views showing a state in which leads of a lead frame are fixed to the side surface of a conventional ceramic substrate for a semiconductor device package.

第２図においては、半導体チップを上面１１１１に搭載
し、この半導体チップの電極パッドと導電接続のリード
フレーム４のリード５が、セラミックの基体１１０麹面
の正しい位置に固着されている。ところが、リードフレ
ーム４のリード５が第２図のように何時も正しい位置に
固着されると拡限ら犬第３図に示すように、その固着位
置がすれることがある。In FIG. 2, a semiconductor chip is mounted on the upper surface 1111, and the leads 5 of the lead frame 4, which are conductively connected to the electrode pads of the semiconductor chip, are fixed at correct positions on the surface of the ceramic base 110. However, if the lead 5 of the lead frame 4 is always fixed at the correct position as shown in FIG. 2, the fixed position may be shifted as shown in FIG. 3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のとおシ、従来のセラミック基体においては、リー
ドフレームのリードの位置決めがすれて、正しい位置Ｋ
ＩＪ−ドが固着されず、プリント基板に実装時に支障を
来たすということが暫々起る。As mentioned above, in conventional ceramic substrates, the leads of the lead frame are misaligned, resulting in the correct position K.
It sometimes happens that the IJ-card is not fixed, causing trouble when mounting it on a printed circuit board.

また、パッケージ工程のグイボンディング、封止などの
加熱によるシーリングガラスの溶融時にも固着リードの
位置すれを起すという問題がある。Furthermore, there is a problem in that the fixed leads may become misaligned when the sealing glass is melted by heating during bonding or sealing in the packaging process.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点に対し、本発明では、基体側面のす−ドフレ
ームのリードが固着する部分は固着リードの幅に合せて
凹ませておく。In order to solve the above problem, in the present invention, the portion of the side surface of the base to which the leads of the slide frame are fixed is recessed to match the width of the fixed leads.

〔実施例〕〔Example〕

つぎに本発明を実施例により説明する０第１図は本発明
の一実施例の斜視図である。図において、本発明のセラ
ミックの基体では、上面のはは中央に、半導体チップを
搭載するための凹み１が設けられ、また、この凹み１＆
Ｃ搭載固着した半導体チップ（図示せず）の電極パッド
と導電接続の導電パターンは、基体側面２に導出されて
おυ、かつ、この導出部は、ここに固着されるリードフ
レームのリードが入り込む凹み３に形成されている。Next, the present invention will be explained with reference to an embodiment. FIG. 1 is a perspective view of an embodiment of the present invention. In the figure, in the ceramic base of the present invention, a recess 1 for mounting a semiconductor chip is provided at the center of the upper surface.
The conductive pattern for conductive connection with the electrode pads of the semiconductor chip (not shown) mounted and fixed on C is led out to the side surface 2 of the base body υ, and the leads of the lead frame fixed here enter into this lead-out part. It is formed in the recess 3.

〔発明の効果〕〔Effect of the invention〕

上述のとおシ、本発明の半導体装置パッケージ用セ２ミ
ック基体では、リードフレームのリードが固着される側
面のリード固着部は固着リードの幅に合せて凹ませてい
るので、この凹んだところにリードフレームのリードを
入れ固着することで、正しい位置にリード付けかなされ
、また後工程の加熱の際にも位置すれを起すことがなく
、よって製品歩留シが向上される。As mentioned above, in the semiconductor device package semiconductor substrate of the present invention, the lead fixing portion on the side surface to which the leads of the lead frame are fixed is recessed to match the width of the fixed lead, so that the recessed part By inserting and fixing the leads of the lead frame, the leads can be attached at the correct position, and there will be no misalignment during heating in the post-process, thereby improving product yield.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の斜視図、第２図とを示す側
面図である。 １・・・・・・半導体チップ収納凹み、２・・・・・・
リード付は側面、３・・・・・・リード付は凹み、４・
・・・・・リードフレーム、５・・・・・・リード部、
１１・・・・・・従来のセラミック基体。FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a side view showing the same. 1... Semiconductor chip storage recess, 2...
With lead, side, 3... With lead, recess, 4.
...Lead frame, 5...Lead part,
11... Conventional ceramic substrate.

Claims (1)

【特許請求の範囲】[Claims] 　表面側に半導体チップを搭載し、側面にリードフレー
ムの複数のリードが固着される半導体装置用セラミック
基体において、前記側面には前記リードが個々に入り込
む凹みが形成されていることを特徴とするパッケージ用
セラミック基体。A ceramic substrate for a semiconductor device on which a semiconductor chip is mounted on the front side and a plurality of leads of a lead frame are fixed to the side surface, the package characterized in that the side surface is formed with recesses into which the leads individually enter. Ceramic substrate for use.
JP2115585A 1985-02-06 1985-02-06 Ceramic base body for package of semiconductor device Pending JPS61181151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2115585A JPS61181151A (en) 1985-02-06 1985-02-06 Ceramic base body for package of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2115585A JPS61181151A (en) 1985-02-06 1985-02-06 Ceramic base body for package of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61181151A true JPS61181151A (en) 1986-08-13

Family

ID=12047013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2115585A Pending JPS61181151A (en) 1985-02-06 1985-02-06 Ceramic base body for package of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61181151A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7751193B2 (en) 2006-12-27 2010-07-06 Mitsubishi Corporation Electronic control apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7751193B2 (en) 2006-12-27 2010-07-06 Mitsubishi Corporation Electronic control apparatus

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