JPS61180430A - Formation of electrode of semiconductor device - Google Patents
Formation of electrode of semiconductor deviceInfo
- Publication number
- JPS61180430A JPS61180430A JP2107285A JP2107285A JPS61180430A JP S61180430 A JPS61180430 A JP S61180430A JP 2107285 A JP2107285 A JP 2107285A JP 2107285 A JP2107285 A JP 2107285A JP S61180430 A JPS61180430 A JP S61180430A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- bonding
- metal layer
- bonding electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 7
- 239000000956 alloy Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000000470 constituent Substances 0.000 abstract description 3
- 229910052733 gallium Inorganic materials 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 38
- 239000010931 gold Substances 0.000 description 28
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 18
- 229910052737 gold Inorganic materials 0.000 description 18
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003353 gold alloy Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004452 microanalysis Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置のオーミック電極を形成する方法に
関し、特に■−ｖ族化合物半導体装置におけるオーミッ
ク電極形成方法の改良に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming an ohmic electrode in a semiconductor device, and particularly relates to an improvement in a method for forming an ohmic electrode in a ■-v group compound semiconductor device.
Ｉ−Ｖ族の化合物半導体装置においては、半導体チップ
に外部リード線をボンディングするためチップ表面に形
成される内部端子として、金または金合金の電極金属が
多く用いられている。In group IV compound semiconductor devices, gold or gold alloy electrode metals are often used as internal terminals formed on the chip surface for bonding external lead wires to the semiconductor chip.
この場合、上記金兄電極は半導体チップのリード線導出
予定領域主表面に被着したままの状態では良好なボンデ
ィング性能を有しているものの、該電極を半導体層にオ
ーミック接触させるために熱処理を施すとボンディング
能率が低下することが知られている。この原因は、熱処
理によって半導体結晶の構成成分または金合金中のオー
ミック成分が電極膜表面にまで拡散し、表層に薄い酸化
層を形成するためであると考えられる。In this case, although the metal electrode has good bonding performance when it remains attached to the main surface of the area where the lead wires are to be led out of the semiconductor chip, heat treatment is required to bring the electrode into ohmic contact with the semiconductor layer. It is known that bonding efficiency decreases if The reason for this is thought to be that the constituent components of the semiconductor crystal or the ohmic components in the gold alloy diffuse to the surface of the electrode film due to the heat treatment, forming a thin oxide layer on the surface layer.
この問題に対する一つの対策として、上記と同様にして
金合金層の被着およびオーミック接触のための熱処理を
行なった後、更にその上に金層を積層被着する「金オー
バーコート方式」と呼ばれる方法が提案されている。こ
の方法によってボンディング能率は飛躍的に向上し、例
えばＧａＰ発光ダイオードに適用した場合、従来は９５
〜９９％のボンディング成功率が９９．９９％にまで向
上した。他の半導体結晶に適用した例でも、何れの場合
も従来方式に比べればボンディング能率を向上できる結
果が得られている。One solution to this problem is the "gold overcoat method," in which a gold alloy layer is deposited and heat treated for ohmic contact in the same manner as above, and then a gold layer is deposited on top of it. A method is proposed. This method dramatically improves bonding efficiency, and for example, when applied to GaP light emitting diodes, conventionally 95
The bonding success rate of ~99% was improved to 99.99%. Even when applied to other semiconductor crystals, results have been obtained in which the bonding efficiency can be improved compared to the conventional method.
なお、以下の説明においては、「金オーバーコート方式
」で最初に被着する電極をオーミック電極、その上に積
層被着される電極をボンディング電極と称することにす
る。In the following description, the electrode deposited first in the "gold overcoat method" will be referred to as an ohmic electrode, and the electrode laminated thereon will be referred to as a bonding electrode.
ところが、上記「金オーバーコート方式」もボンディン
グ性の低い半導体、例えばＧａＡｌＡｓ赤色発光素子に
適用した場合には、従来４０〜７０％であったボンディ
ング成功率が８５〜９５％と大幅に向上するものの、他
の半導体装置に適用した場合に比較すればこの数字はか
ならずしも満足できるものではない。この場合にもボン
ディング電極層を厚くすればボンディング成功率を更に
向上することが可能であるが、コストが増大する上、電
極金属の真空蒸着中に基板温度が上昇する結果、次の説
明と同様、Ｑａ等のオーミック成分がボンディング電極
の金層を拡散して表面に堆積し、却ってボンディング性
が劣化するおそれがある。However, when the above-mentioned "gold overcoat method" is applied to semiconductors with poor bonding properties, such as GaAlAs red light emitting devices, the bonding success rate, which was conventionally 40 to 70%, is significantly improved to 85 to 95%. However, this figure is not necessarily satisfactory when compared with applications to other semiconductor devices. In this case as well, it is possible to further improve the bonding success rate by making the bonding electrode layer thicker, but this increases the cost and increases the substrate temperature during vacuum deposition of the electrode metal, which is similar to the following explanation. , Qa, and the like may diffuse through the gold layer of the bonding electrode and deposit on the surface, which may actually deteriorate the bonding performance.
ところで、ＧａＡ Ｉ Ａｓ赤色発光ダイオードの場合
に、「金オーバーコート方式」を適用しても上記のよう
に低いボンディング能率に止まる原因については、イオ
ンマイクロアナリシス等の表面物理解析の結果から次の
ように推察することができる。By the way, in the case of GaAI As red light emitting diodes, the reason why the bonding efficiency remains low even if the "gold overcoat method" is applied is as follows based on the results of surface physical analysis such as ion microanalysis. It can be inferred that
即ち、「金オーバーコート方式」ではオーミック電極の
形成後、例えば真空蒸着によりボンディング電極を形成
するに際し、オーミック電極とボンディング電極との密
着性を良好にするため、オーミック電極層が被着された
半導体基板を２００℃程度に加熱しながら金を蒸発して
被着せしめる。In other words, in the "gold overcoat method", after forming the ohmic electrode, when forming the bonding electrode by vacuum evaporation, the semiconductor on which the ohmic electrode layer is coated is used to improve the adhesion between the ohmic electrode and the bonding electrode. Gold is evaporated and deposited while heating the substrate to about 200°C.
このとき、既にオーミック電極表面に析出していた半導
体構成４分等が蒸着中のボンディング金層中を拡散し、
その表面に大量に析出する。この析出成分が水分等によ
りその後酸化される結果、ボンディング能率が低下する
ものと考えられる。At this time, the semiconductor components that had already been deposited on the surface of the ohmic electrode diffused into the bonding gold layer that was being deposited.
It precipitates in large quantities on its surface. It is thought that this precipitated component is subsequently oxidized by moisture or the like, resulting in a decrease in bonding efficiency.
本発明は上記事情に鑑みてなされたもので、上述の「金
オーバーコート方式」を改良し、特にＧａＡｌＡｓ赤色
発光ダイオ−下等のように「金オーバーコート方式」で
もなおボンディング能率の低い半導体素子に適用してボ
ンディング能率を顕著に向上することができる半導体装
置の電極形成方法を提供するものである。The present invention has been made in view of the above circumstances, and is an improvement on the above-mentioned "gold overcoat method", and is particularly suitable for semiconductor devices such as GaAlAs red light emitting diodes, which still have low bonding efficiency even with the "gold overcoat method". The present invention provides a method for forming electrodes of a semiconductor device that can be applied to significantly improve bonding efficiency.
本発明による半導体装置の電極形成方法は、半導体単結
晶表面上にオーミック電極を形成し得る金属層を被着し
た後、加熱処理を施すことにより前記半導体単結晶表面
にオーミック接触したオーミック電極層を形成する工程
と、該オーミック電極層上に積層して第一のボンディン
グ電極用金属層を被着した後、被着装置外に取出すこと
なく一旦冷却して前記第一のボンディング電極用金属層
の被着開始温度以下になってから再度第二のボンディン
グ電極用金属層を被着する工程とを具備したことを特徴
とするものである。The method for forming an electrode in a semiconductor device according to the present invention includes depositing a metal layer capable of forming an ohmic electrode on the surface of a semiconductor single crystal, and then applying heat treatment to form an ohmic electrode layer in ohmic contact with the surface of the semiconductor single crystal. After depositing the first bonding electrode metal layer by laminating it on the ohmic electrode layer, the first bonding electrode metal layer is cooled without being taken out of the deposition apparatus. The present invention is characterized by comprising the step of again depositing the second bonding electrode metal layer after the temperature drops below the deposition start temperature.
上記のようにボンディング電極用金属層を二段階以上の
被着で形成することにより、オーミック電極表面に析出
していた半導体構成４分等がボンディング電極用金層表
面に大量に析出するのを防止できる。即ち、下層のボン
ディング電極用金属層を被着した後に一旦冷却して上層
のボンディング電極用金属層を被着するから、下層電極
層表面に析出していた半導体構成４分等の上層電極金属
層中への拡散が抑制されることになる。By forming the metal layer for the bonding electrode in two or more stages as described above, it is possible to prevent the semiconductor components, etc., which were deposited on the surface of the ohmic electrode, from depositing in large quantities on the surface of the gold layer for the bonding electrode. can. That is, since the lower bonding electrode metal layer is deposited and then cooled once, the upper bonding electrode metal layer is deposited, so that the upper electrode metal layer, such as the semiconductor component quarter, which has been deposited on the surface of the lower electrode layer is removed. Diffusion into the interior will be suppressed.
以下、添附の図面を参照して本発明の一実施例を説明す
る。Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.
まず、Ｐ型ＧａＡＳ基板１上にＰ型ＧａＡｌＡｓ１１２
及びＮ型ＧａＡ Ｉ Ａｓ層３を順次エピタキシャル成
長させ、赤色発光ダイオードの発光領域となるＰＮ接合
を形成する。続いてＰ型ＧａＡＳ基板１の裏面およびＮ
型ＧａＡ Ｉ ＡＳ層３の表面に、ＡｕＢｅ合金層４、
ＡｕＧｅ合金層５を夫々真空蒸着する。次に、Ｎ２ガス
中で５２０℃、５分間の熱処理を施すことにより合金層
４，５にオーミック接触を与え、オーミック電極を形成
する。First, P-type GaAlAs 112 is placed on P-type GaAS substrate 1.
and an N-type GaAI As layer 3 are sequentially epitaxially grown to form a PN junction that will become a light emitting region of a red light emitting diode. Next, the back surface of the P-type GaAS substrate 1 and the N
On the surface of the type GaAI AS layer 3, an AuBe alloy layer 4,
AuGe alloy layers 5 are each vacuum-deposited. Next, heat treatment is performed at 520° C. for 5 minutes in N2 gas to bring the alloy layers 4 and 5 into ohmic contact, thereby forming an ohmic electrode.
なお、こうして形成されたオーミック電極４゜５の表層
には、夫々Ｇｅ、Ｇａの酸化物が存在することがオージ
ェ分析等で明らかになっている。Incidentally, Auger analysis etc. have revealed that Ge and Ga oxides are present in the surface layer of the ohmic electrode 4.5 thus formed, respectively.
次に、ＡｕＧｅ電極面上にボンディング電極用金属層と
してＡｕを真空蒸着する。その際、まず通常の「金オー
バーコート方式」と同様、略１５０℃程度に加熱してか
ら蒸着を開始して第一のＡＵ層６を形成する。こうして
第一のＡｕ層６を蒸着している間に、温度は更に上昇す
る。そこで、第一のＡｕ層６が所定の膜厚で形成された
ら一旦蒸着を中止し、略１２０℃の温度まで冷却した後
、再度Ａｕの蒸着を開始して第二のＡｕ層７を被着する
。こうしてのＡｕの積層膜からなるボンディング電極用
金属層を形成したら、ウェハーを真空蒸着装置の外に取
出し、次いで写真蝕刻法によりこのＡｕ積層膜を所定の
電極形状にパターンニングしてボンディング電極とする
。Next, Au is vacuum-deposited as a bonding electrode metal layer on the AuGe electrode surface. At this time, first, as in the usual "gold overcoat method", the first AU layer 6 is formed by heating to approximately 150° C. and then starting vapor deposition. While the first Au layer 6 is being deposited in this way, the temperature further increases. Therefore, once the first Au layer 6 is formed with a predetermined thickness, the vapor deposition is temporarily stopped, and after cooling to a temperature of approximately 120° C., Au vapor deposition is started again to deposit the second Au layer 7. do. After forming the bonding electrode metal layer made of the Au laminated film, the wafer is taken out of the vacuum evaporation apparatus, and then the Au laminated film is patterned into a predetermined electrode shape by photolithography to form the bonding electrode. .
上記実施例の方法で形成されたボンディング電極では、
その表面に析出しているＧａ、Ｇｅ等が従来の「金オー
バーコト方式」の場合に比べて約１桁少ないことが明ら
かになった。これは第一のＡｕ層６を蒸着した後に一旦
冷却することで、ＡＵ層６の表面に析出したＱａ、 Ｇ
ｅ等が第二のＡＵ層７中に拡散するのを抑制できたこと
を示している。In the bonding electrode formed by the method of the above example,
It has been revealed that the amount of Ga, Ge, etc. precipitated on the surface is about one order of magnitude less than in the conventional "gold overcoat method". This is because by cooling the first Au layer 6 after vapor deposition, Qa and G precipitated on the surface of the AU layer 6 are removed.
This shows that diffusion of e.g. into the second AU layer 7 could be suppressed.
こうしてボンディング電極表面における半導体構成々分
の析出が回避される結果、ボンディング性を大幅に向上
できる。この効果を検証するために、次の三種類のＧａ
ＡｌＡｓ赤色発光ダイオード素子を対象としたボンディ
ング試験を行なった。In this way, precipitation of semiconductor constituents on the surface of the bonding electrode is avoided, and as a result, bonding properties can be significantly improved. In order to verify this effect, the following three types of Ga
A bonding test was conducted on an AlAs red light emitting diode element.
実施例量
上記実施例の方法で電極を形成したＧａＡｌＡｓ赤色発
光ダイオードチップ。Example Quantity A GaAlAs red light emitting diode chip with electrodes formed by the method of the above example.
従来品Ａ
ＡｕＧｅオーミック電極５のみを形成したＧａＡｌＡｓ
赤色発光ダイオードチップ。Conventional product A GaAlAs with only AuGe ohmic electrode 5 formed
Red light emitting diode chip.
従来品Ｂ
従来の「金オーバーコート方式」によりボンディング電
極を形成したＧａＡｌＡｓ赤色発光ダイオードチップ。Conventional product B A GaAlAs red light emitting diode chip with bonding electrodes formed using the conventional "gold overcoat method."
上記の各ボンディング試験におけるボンディング成功率
を比較すると、下記第１表に示す通りであった。A comparison of the bonding success rates in each of the above bonding tests was as shown in Table 1 below.
第１表の結果から、上記の実施例によれば［金オーバー
コート方式」によっても未だ充分なボンディング性能が
得られたかったＧａＡ Ｉ Ａｓ素子についても、その
ボンディング性能を著しく向上し、他の素子の場合と同
様のボンディング成功率を得られることが明かである。From the results in Table 1, it can be seen that according to the above example, the bonding performance of the GaA I As element, for which sufficient bonding performance could still be obtained even with the [gold overcoat method], was significantly improved, and the bonding performance of other elements was improved. It is clear that the same bonding success rate as in the case of .
なお、上記の実施例ではボンディング電極を二段階で形
成したが、三段階以上の多段階で形成するようにしても
よい。In addition, although the bonding electrode was formed in two steps in the above embodiment, it may be formed in multiple steps of three or more steps.
また、本発明はＧａＡｌＡｓ以外の半導体チップ、Ａｕ
以外の電極材料を用いた場合にも適用できるものである
。Further, the present invention is applicable to semiconductor chips other than GaAlAs, Au
It can also be applied to cases where other electrode materials are used.
以上詳述したように、本発明による電極形成方法を用い
れば、ＧａＡ Ｉ Ａｓ赤色発光ダイオード等のように
「金オーバーコート方式」でもなおボンディング能率の
低い半導体素子についてもボンディング能率を大幅に向
上できる等、顕著な効果が得られるものである。As detailed above, by using the electrode forming method according to the present invention, it is possible to significantly improve the bonding efficiency of semiconductor elements such as GaAIAs red light emitting diodes, which still have low bonding efficiency even with the "gold overcoat method". etc., remarkable effects can be obtained.
添附の図面は、本発明をＧａＡ Ｉ Ａｓ赤色発光ダイ
オード素子の電極形成に適用した一実施例を説明するた
めの断面図である。
１ ・Ｐ型ＧａＡＳ基板、２−Ｐ型ＧａＡｌＡｓ層、３
・Ｎ型ＧａＡｌ Ａｓ層、４ ・Ａ ｕ Ｂ ｅオー
ミック電極、５・・・ＡｕＧｅオーミック電極、６・・
・第一のＡｕボンディング電極層、７・・・第二のＡＵ
ボンディング電極層。The accompanying drawings are cross-sectional views for explaining one embodiment in which the present invention is applied to electrode formation of a GaAIAs red light emitting diode element. 1 - P-type GaAS substrate, 2-P-type GaAlAs layer, 3
・N-type GaAl As layer, 4 ・AuBe ohmic electrode, 5...AuGe ohmic electrode, 6...
・First Au bonding electrode layer, 7... second AU
Bonding electrode layer.
Claims (2)
る金属層を被着した後、加熱処理を施すことにより前記
半導体単結晶表面にオーミック接触したオーミック電極
層を形成する工程と、該オーミック電極層上に積層して
第一のボンディング電極用金属層を被着した後、被着装
置外に取出すことなく一旦冷却して前記第一のボンディ
ング電極用金属層の被着開始温度以下になつてから再度
第二のボンディング電極用金属層を被着する工程とを具
備したことを特徴とする半導体装置の電極形成方法。(1) A step of depositing a metal layer capable of forming an ohmic electrode on the surface of the semiconductor single crystal, and then performing heat treatment to form an ohmic electrode layer in ohmic contact with the surface of the semiconductor single crystal, and the ohmic electrode After the first bonding electrode metal layer is laminated on the layer, the first bonding electrode metal layer is cooled once to a temperature below the deposition start temperature of the first bonding electrode metal layer without being taken out of the deposition apparatus. 1. A method for forming an electrode for a semiconductor device, comprising the step of again applying a second bonding electrode metal layer.
徴とする特許請求の範囲第（１）項記載の半導体装置の
電極形成方法。(2) The method for forming an electrode for a semiconductor device according to claim (1), wherein the semiconductor single crystal is GaAlAs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60021072A JPH0693443B2 (en) | 1985-02-06 | 1985-02-06 | Method for forming electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60021072A JPH0693443B2 (en) | 1985-02-06 | 1985-02-06 | Method for forming electrode of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61180430A true JPS61180430A (en) | 1986-08-13 |
| JPH0693443B2 JPH0693443B2 (en) | 1994-11-16 |
Family
ID=12044679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60021072A Expired - Lifetime JPH0693443B2 (en) | 1985-02-06 | 1985-02-06 | Method for forming electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693443B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162457A (en) * | 1978-06-14 | 1979-12-24 | Toshiba Corp | Electrode forming method for semiconductor element |
| JPS55111126A (en) * | 1979-02-19 | 1980-08-27 | Matsushita Electric Ind Co Ltd | Method of forming electrode for compound-semiconductor device |
| JPS5624932A (en) * | 1979-08-08 | 1981-03-10 | Mitsubishi Electric Corp | Method of forming ohmic electrode on semiconductor of n type, 3-5 group compound in periodic table |
| JPS56142666A (en) * | 1980-04-07 | 1981-11-07 | Toshiba Corp | Semiconductor device |
-
1985
- 1985-02-06 JP JP60021072A patent/JPH0693443B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162457A (en) * | 1978-06-14 | 1979-12-24 | Toshiba Corp | Electrode forming method for semiconductor element |
| JPS55111126A (en) * | 1979-02-19 | 1980-08-27 | Matsushita Electric Ind Co Ltd | Method of forming electrode for compound-semiconductor device |
| JPS5624932A (en) * | 1979-08-08 | 1981-03-10 | Mitsubishi Electric Corp | Method of forming ohmic electrode on semiconductor of n type, 3-5 group compound in periodic table |
| JPS56142666A (en) * | 1980-04-07 | 1981-11-07 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0693443B2 (en) | 1994-11-16 |
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