JPS60253246A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60253246A JPS60253246A JP10919384A JP10919384A JPS60253246A JP S60253246 A JPS60253246 A JP S60253246A JP 10919384 A JP10919384 A JP 10919384A JP 10919384 A JP10919384 A JP 10919384A JP S60253246 A JPS60253246 A JP S60253246A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor
- semiconductor element
- die
- metal thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000010409 thin film Substances 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 7
- 239000011347 resin Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 5
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 238000005275 alloying Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 abstract description 7
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 238000005453 pelletization Methods 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 229910015367 Au—Sb Inorganic materials 0.000 abstract 1
- 229910015365 Au—Si Inorganic materials 0.000 abstract 1
- 230000005496 eutectics Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に関し、特に、安価で
電気特性の優れた半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device that is inexpensive and has excellent electrical characteristics.
（従来技術）
従来より、半導体装置の製造において、半導体素子裏面
とリードフレーム・アイランドとの間に、オーεツクコ
ンタクトを得ることは、半導体素子のラッチアップ不良
を低減するため等、重要な技術となっており、種々の裏
面メタライゼーション方法、又は、ダイボンディング方
法が提供されている。(Prior art) Traditionally, in the manufacturing of semiconductor devices, obtaining open contact between the back surface of a semiconductor element and a lead frame island has been an important technology for reducing latch-up defects of semiconductor elements. Various backside metallization methods or die bonding methods have been provided.
広く用いられている方法に、Ａｕ Ｓｒ共晶法がある。A widely used method is the Au/Sr eutectic method.
Ａｕ−８ｉ共晶法は、半導体素子をＡｕ薄膜又は、微量
のｓｂを含んだＡｕ薄膜片をダイボンディング用ソルダ
ーとして、４００℃以上に加熱しリードフレームアイラ
ンド上にダイボンディングする方法である。Ａｕ−８ｉ
共晶法でダイボンディングした半導体素子はラッチアッ
プ不良の発生はなく、即ちオーミック・コンタクト性は
良好であるが、非常に高価である欠点がある。又、Ａｕ
−８ｉ共晶法で、ダイボンディングするためには、半導
体素子裏面の表面状態、即ち、表面の酸化物層の厚みに
注意しなければならず、工程管理上にも問題がある。The Au-8i eutectic method is a method in which a semiconductor element is die-bonded onto a lead frame island by heating it to 400° C. or higher using an Au thin film or an Au thin film piece containing a small amount of SB as a die-bonding solder. Au-8i
Semiconductor elements die-bonded by the eutectic method do not cause latch-up failures, that is, have good ohmic contact, but have the drawback of being very expensive. Also, Au
In order to perform die bonding using the -8i eutectic method, attention must be paid to the surface condition of the back surface of the semiconductor element, that is, the thickness of the oxide layer on the surface, which also poses problems in terms of process control.
他の方法として、半導体素子裏面にあらかじめ金属薄膜
を形成し、しかる後、導電性樹脂にてダイボンディング
する裏面一層メタライゼーシ田ン法がある。この場合、
金属薄膜は、Ａｕ又はｓｂを含むＡｕ薄膜（以下Ａｕ又
はＡｕ−８ｂ薄膜と略記）を真空蒸着法によって形成す
る方法が広く用いられている。この従来方法は、安価で
、かつ、オーミックコンタクト性もほぼ良好である。し
かしながら、この従来方法では、オーミック・コンタク
ト性のバラツキが大きく、半導体装置の歩留シを低下さ
せる原因となる。このバラツキ改善のため、■半導体基
板を加熱した後、Ａｕ又はＡｕ−８ｂ薄膜を真空蒸着す
る方法、又は■Ａｕ又はＡ、ｕ−８ｂ薄脱の蒸着に先だ
ち Ｉｐｉ薄膜を蒸着する方法が提案されているが、い
ずれも、メーミックコンタクト性のバラツキを改善する
に致っていない。Another method is a backside single-layer metallization method in which a metal thin film is previously formed on the backside of the semiconductor element and then die-bonded with a conductive resin. in this case,
As the metal thin film, a method of forming an Au thin film containing Au or sb (hereinafter abbreviated as Au or Au-8b thin film) by vacuum evaporation is widely used. This conventional method is inexpensive and has almost good ohmic contact properties. However, in this conventional method, there is large variation in ohmic contact properties, which causes a decrease in the yield of semiconductor devices. In order to improve this variation, a method has been proposed: (1) vacuum-depositing an Au or Au-8b thin film after heating the semiconductor substrate, or (2) depositing an Ipi thin film prior to the thin-film deposition of Au, A, or U-8b. However, none of these methods has been able to improve the variation in memic contact properties.
（発明が解決しようとする問題点）
本発明の目的れ安価でオーミックコンタクト性の優れた
ダイボンディング方法を含む半導体装置の製造方法を得
ることにある。(Problems to be Solved by the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor device including a die bonding method that is inexpensive and has excellent ohmic contact properties.
（問題点を解決するための手段）
本発明によれば、半導体素子の裏面に半導体素子構成材
料とＡｕ又は８ｂを含んだＡｕである第１の金属との合
金を形成する工程と、その後この合金の上にＡｕ又はｓ
ｂを含んだＡｕである第２の金属を被覆する工程と、第
２の金属をリードフレームもしくは素子容器に導電性樹
脂で接着する工程とを含む半導体装置の製造方法を得る
。(Means for Solving the Problems) According to the present invention, there is a step of forming an alloy of a semiconductor element constituent material and a first metal which is Au or Au containing 8b on the back surface of a semiconductor element, and then this step. Au or S on the alloy
A method for manufacturing a semiconductor device is obtained, which includes a step of coating a second metal, which is Au containing b, and a step of bonding the second metal to a lead frame or an element container with a conductive resin.
（発明の効果）
本発明によれば、安価でオーミック・コンタクト性が良
好で、かつ、バラツキの少ない半導体装置の製造方法を
提供できる。即ち本発明によれば高価なＡｕ−８ｉ共晶
法を用いることなしに、Ａｕ−８ｉ共晶法と、同程度の
バラツキのないオーミック・コンタクト性を提供するこ
とが出来、従来、Ａｕ−８ｉ共晶法によるダイボンディ
ングでしか生産出来なかった半導体装置を、安価な導電
性樹脂によるダイボンディング法で生産できる裏面メタ
ライゼーシ璽ン方法を提供するものである。(Effects of the Invention) According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that is inexpensive, has good ohmic contact properties, and has little variation. That is, according to the present invention, it is possible to provide ohmic contact properties with the same level of variation as the Au-8i eutectic method without using the expensive Au-8i eutectic method. To provide a backside metallization method that can produce semiconductor devices that could only be produced by die bonding using the eutectic method, by die bonding using an inexpensive conductive resin.
（実施例）
まず、本発明の構成を更に詳しく説明する。本発明によ
ると、あらかじめ、第一の金属薄膜を形成する工程と、
熱処理を施して、合理化する工程と、さらに第二の金属
薄膜を形成する工程とを経た、即ち裏面二層メタライゼ
ーシ冒ン層を形成した半導体素子を用いて、導電性樹脂
によるダイボンディングをすることによＪ） Ａｕ−８
ｉ共晶法と同程度の、バラツキの少ないオーミックコン
タクト性５−
が得られ、Ａｕ−８４共晶法と比較して数分の１の価格
で、生産することが可能と力る。本発明で、使用する、
第１、第２の金属薄膜としてＡｕ又はＡｕ・ｓｂ薄膜が
有効であるが、使用方法は衣−１の如く使用半導体基板
の導電型により異なる。表−１でＡｕ、 Ａｕ −８ｂ
と書かれているのは同金属を蒸着した後、加熱する方法
で、形成する金属薄膜であシ、Ｔｔ−Ａｕ、 Ｔｉ Ａ
ｕ−８ｂと書かれているのは、あらかじめＴｉを蒸着し
た後、直ちにＡｕ又はＡｕ−８ｂを蒸着する方法で形成
する金属薄膜を示している。(Example) First, the configuration of the present invention will be explained in more detail. According to the present invention, the step of forming a first metal thin film in advance;
Die bonding with a conductive resin is performed using a semiconductor element that has undergone a process of heat treatment and rationalization and a process of forming a second metal thin film, that is, a two-layer metallization layer is formed on the back side. Yo J) Au-8
It is believed that it is possible to obtain ohmic contact properties 5- with little variation comparable to that of the i-eutectic method, and to be able to produce it at a fraction of the price compared to the Au-84 eutectic method. In the present invention, used
Au or Au.sb thin films are effective as the first and second metal thin films, but the method of use differs depending on the conductivity type of the semiconductor substrate used, as in Example 1. In Table-1, Au, Au-8b
This is a method in which the same metal is vapor-deposited and then heated, and the formed metal thin film is
The letter u-8b indicates a metal thin film formed by depositing Ti in advance and then immediately depositing Au or Au-8b.
表−１半導体基板の導電型による金属薄膜の種類６−
以下、本発明を実施例にもとづき説明する。Ｎ型半導体
基板ウェーハに通常の酸化、拡散、フォト・エツチング
法等を用いて半導体素子を形成した。この半導体ウェー
ハの裏面に０．２％のｓｂ を含んだ、Ａｕ薄膜を約２
００ＯＡ、Ｅ・ガン蒸着法によって形成した。この時Ａ
ｕ−８ｂ薄膜のハガレを防止する手段として■Ａｕ薄膜
を蒸着した後２００’Ｃに半導体ウェーハを加熱する。Table 1 Types of metal thin films according to conductivity type of semiconductor substrate 6 The present invention will be described below based on examples. Semiconductor elements were formed on an N-type semiconductor substrate wafer using conventional oxidation, diffusion, photo-etching, etc. methods. Approximately 20% of the Au thin film containing 0.2% sb was deposited on the back side of this semiconductor wafer.
It was formed by the 00OA, E gun evaporation method. At this time A
As a means to prevent peeling of the U-8B thin film, (1) After depositing the Au thin film, the semiconductor wafer is heated to 200'C.
■あらかじめ、Ｔｉを約３００Ａ程度蒸着した後、Ａｕ
−８ｂ薄膜を連続蒸着するの三方法がある。さらに、半
導体ウェーハを４８０℃の電気炉にて１ｏ分間加熱処理
を施こし、該ウェーハ裏面にＡｕ−８４層を形成した。■After evaporating Ti to about 300A in advance, Au
There are three methods for successively depositing -8b thin films. Furthermore, the semiconductor wafer was heat-treated for 10 minutes in an electric furnace at 480° C. to form an Au-84 layer on the back surface of the wafer.
しかる後、前記と同様の方法で、第２のＡｕ−８ｂ薄膜
を形成した。これらの処理は通常ウェーハ状態で行なわ
れる。以上で、裏面二層メタライゼーション工程は完了
し、以下通常のベレッタイジング工程を経て、ダイボン
ディング工程と々る。ダイボンディング工程においては
、９０重量％のＡｇを含んだエポキシ樹脂を用いて接着
した。その後、通常の工程を経て、半導体装置を製造す
る。Thereafter, a second Au-8b thin film was formed in the same manner as above. These processes are usually performed in the wafer state. With the above steps, the back side two-layer metallization process is completed, followed by the usual pelletizing process and then the die bonding process. In the die bonding process, bonding was performed using an epoxy resin containing 90% by weight of Ag. Thereafter, a semiconductor device is manufactured through normal steps.
本実施例を用いて製造した、Ｃ−ＭＯ８型半導体集積回
路のラッチアップによる製品不良率を、他の方法と比較
した結果を表−２に示す。Table 2 shows the results of comparing the product defect rate due to latch-up of the C-MO8 type semiconductor integrated circuit manufactured using this example with other methods.
表−２本発明の一実施例におけるラッチアップ不良率々
お、従来方法−Ｃｔ）Ｆｉ、単にＡｕ片でダイボンディ
ングした製品でオシ、従来方法−（２）は半導体素子表
面に０．２％のｓｂを含んだＡｕ（Ａｕ 、８ｂ ）薄
膜を形成した後２００℃で加熱処理した素子（ａ）、Ｔ
ｉを形成した稜直ちにＡｕ−８ｂを蒸着した素子（ｂ）
を用゛いて、導電性樹脂にてダイボンディングした製品
である。Table 2: Latch-up failure rate in one embodiment of the present invention, Conventional method - Ct) Fi, Product simply die-bonded with Au pieces, Conventional method - (2) 0.2% on the surface of the semiconductor element Element (a), T
Element in which Au-8b was deposited immediately on the edge where i was formed (b)
This is a product that is die-bonded with conductive resin.
又、同様に本実施例を用いて製造した、高速スイッチン
グ・ダイオードの順方向電圧分布を、他の方法で製造し
た結果と比較して表−３に示す。Table 3 also shows the forward voltage distribution of a high-speed switching diode similarly manufactured using this example, in comparison with the results of manufacturing using other methods.
比較対象は前記、Ｃ−ＭＯ８型半導体集積回路装置と同
じである。The comparison target is the same as the C-MO8 type semiconductor integrated circuit device described above.
このように、本発明を用いることにより、安価でかつＡ
ｕ−８ｉ共晶法で、ダイボンディングしたのと、同様の
効果が得られた。In this way, by using the present invention, it is possible to achieve low cost and A
The same effect as die bonding using the u-8i eutectic method was obtained.
表−３本発明の一実施例におゆる順方向電圧特性のバラ
ツキ
９−
以上の実施例では、Ｎ型半導体基板についてのみ記した
がＰ創生導体基板においては、第一の金属薄膜としてＡ
ｕ−８ｂ薄膜の代シに９９．９９％以上の純度のＡｕ薄
膜を使用することによシ実施できる。Table 3 Variation in forward voltage characteristics in one embodiment of the present invention 9 In the above embodiment, only the N-type semiconductor substrate was described, but in the P-generated conductor substrate, A
This can be achieved by using an Au thin film with a purity of 99.99% or more instead of the U-8B thin film.
又、半導体基板の導電型にかかわらず、第二の金属薄膜
としてＡｕ又はＡｕ−８ｂ薄膜のいずれも使用可能であ
る。Furthermore, regardless of the conductivity type of the semiconductor substrate, either Au or Au-8b thin film can be used as the second metal thin film.
さらに、合金化のための、熱処理条件は、半導体素子、
及び熱処理装置の性能によシ種々選択出来、Ａｕ−８ｉ
層を形成する３８０℃から半導体素子の特性を変動させ
ない５００℃の範囲内で、５〜３０分加熱するだけで十
分である。その時の熱処理雰囲気は特に限定されること
はない。Furthermore, the heat treatment conditions for alloying include semiconductor elements,
Various choices can be made depending on the performance of the heat treatment equipment and Au-8i.
It is sufficient to heat for 5 to 30 minutes within the range of 380° C., which forms the layer, to 500° C., which does not change the characteristics of the semiconductor element. The heat treatment atmosphere at that time is not particularly limited.
第一の金属薄膜として使用するＡｕ−８ｂ薄腹中のｓｂ
濃度は０．２ ％に限定されないことは言うまでもない
。sb in Au-8b thin film used as first metal thin film
It goes without saying that the concentration is not limited to 0.2%.
１０−10-
Claims (4)
程と、前記半導体素子を形成する材料と該第−の金属薄
膜とを合金化するための熱処理工程と、さらに第２の金
属薄膜を形成する工程とを経た前記半導体素子を用いて
、導電性樹脂にて半導体素子容器に接着することを特徴
とする半導体装置の製造方法。(1) A step of forming a first metal thin film on the back surface of a semiconductor element, a heat treatment step of alloying the material forming the semiconductor element and the second metal thin film, and further forming a second metal thin film. A method of manufacturing a semiconductor device, characterized in that the semiconductor element that has undergone the step of forming a semiconductor element is bonded to a semiconductor element container using a conductive resin.
成する材料がＮ型半導体基板の時、Ｓｂを含ん′／ｅＡ
ｕ薄膜、前記半導体素子を形成する材料がＰ型半導体基
板の時、Ａｕ薄膜を使用することを特徴とする特許請求
の範囲第１項記載の半導体装置の製造方法。(2) When the material forming the semiconductor element is an N-type semiconductor substrate, the first metal thin film does not contain Sb'/eA
2. The method of manufacturing a semiconductor device according to claim 1, wherein an Au thin film is used when the material forming the semiconductor element is a P-type semiconductor substrate.
〜５００℃で、５〜３０分の熱処理を施すことを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。(3) As the heat treatment step for alloying, 380
2. The method of manufacturing a semiconductor device according to claim 1, wherein heat treatment is performed at 500° C. for 5 to 30 minutes.
だＡｕ薄膜を用いることを特徴とする特許請求の範囲第
１項又は第２項記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein an Au thin film containing Au or Sb is used as the second metal thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10919384A JPS60253246A (en) | 1984-05-29 | 1984-05-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10919384A JPS60253246A (en) | 1984-05-29 | 1984-05-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60253246A true JPS60253246A (en) | 1985-12-13 |
Family
ID=14503985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10919384A Pending JPS60253246A (en) | 1984-05-29 | 1984-05-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60253246A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57154844A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Semiconductor element |
-
1984
- 1984-05-29 JP JP10919384A patent/JPS60253246A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57154844A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Semiconductor element |
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