JPS61178779A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make a feedback mechanism unnecessary and to reduce the titled circuit in scale by detecting a supplied write data signal even it is kept in either high or low level state. CONSTITUTION:When the write data signal is kept in a high or low level state due to a short-circuited head troubled circuit, the potentials Va, Vb of terminals A, B are made unchanged after lapse of a predetermined time. With the potential Va at a high level, a capacitor C1 continues to be charged in a capacitor C1 through a transistor Q6 so that the potential Vn1 at a node n1 exceeds a reference voltage Vref2, as shown by the dotted line (a). With the voltage remaining at the low level, the capacitor C1 continues to be discharged through a transistor Q4 so that the potential Vn1 of the node n1 falls below the reference voltage Vref1 as shown by the dotted line (b). As a result, the output of comparators CMP1 or CMP2 is inverted to produce an abnormality signal phid.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor integrated circuit technology, and relates to a technology effective for use in, for example, a semiconductor integrated circuit device for recording and reproducing in a magnetic disk device.

[Background Art] FIG. 3 shows the configuration of a head drive section of a recording/reproducing IC (semiconductor integrated circuit) in a magnetic disk device such as a hard disk driver or a Fronbi disk driver. That is, the bipolar transistor Q11*Q,2 is connected between the power supply voltage Vcc and the terminals A and B, and the transistor Q1 is connected between the terminals A and B and the constant current source 000.
3. Q14 are connected to each other in pairs. and.

A coil L constituting a magnetic head is externally connected between the terminals A and B, and transistors Q□.

For the base terminals of Q12 and Q131Q14.

, D, and complementary write data signals are applied, respectively. As a result, when the write data signal D changes, the direction of the current flowing through the coil changes, and the reversal of the magnetic field at that time causes data to be written on the magnetic disk.

However, if the write data signal D supplied to the head drive section is not inverted due to a short circuit in the coil L in the magnetic head or a defect in the recording/reproducing IC, normal writing may not be performed. It will no longer be possible. Therefore, for example, in a recording/reproducing IC such as Layer HD102128 manufactured by Hitachi, Ltd., an abnormality detection circuit as shown in FIG. 4 is provided to detect the above-mentioned writing abnormality.

In other words, the capacitor C7 is continuously charged up by the constant current source CC2, and the rise or fall of the potential Va at the terminal A (or B) is detected.
Transistor Q connected in parallel with the above capacitor C1
A circuit is configured to draw out the charge accumulated in the capacitor C1 by turning on zo. Then,
In a normal device, the write data signal is always inverted periodically, so if there is a short circuit in the head or a defect in the IC, the potentials at terminals A and B will not change. Therefore, transistor QIO is no longer turned on, and capacitor C1 is no longer discharged. the result,
The potential of node n1 increases steadily. Therefore, the abnormal signal φd was generated by detecting the potential of this node n1 with the comparator CMP.

However, in the abnormality detection circuit as described above, if an abnormality occurs while the potential of the monitored terminal A or B is at a high level, the transistor QIO remains on and the abnormality cannot be detected. There is a risk that it will disappear. Therefore, once the potential of the node n1 is lowered, it becomes necessary to provide a feedback function that lowers the base potential of the transistor Q1o to cut it off. Therefore, if the circuit format shown in FIG. 4 is adopted, the circuit scale of the entire abnormality detection circuit becomes very large.Furthermore, in the circuit shown in FIG. 4, the transistor QIO operates in saturation.

There is a problem in that the peripheral substrate potential must be stabilized, which creates layout constraints.

[Object of the Invention] An object of the present invention is to provide a semiconductor integrated circuit technology that can reduce the scale of an abnormality detection circuit in a recording/reproducing IC of a magnetic disk device, for example.

Another object of the present invention is to provide a semiconductor integrated circuit technology that facilitates the layout design of a recording/reproducing IC for a magnetic disk device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, 1. For example, when applied to an abnormality detection circuit in a recording/reproducing IC of a magnetic disk device, the capacitor is instantaneously discharged to a predetermined level by the potential of the output terminal of the head drive unit, which fluctuates according to the write data signal. In addition to the transistor, a transistor is provided that instantly charges up the capacitor to a predetermined level, and after the capacitor is discharged or charged up by these transistors,
By configuring a circuit that gradually continues discharging or charging up, it is possible to detect whether the supplied write data signal remains at a high level or a low level and does not change. The present invention achieves the above-mentioned objectives of reducing the circuit scale of the abnormality detection circuit and eliminating layout constraints by eliminating transistors that operate in saturation.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to, for example, an abnormality detection circuit in a recording/reproducing IC of a magnetic disk device.

In this embodiment, a PNP bipolar transistor Q2 is connected via a resistor R2 between the other terminal (node n,) of a capacitor C1 whose one terminal is connected to the power supply voltage Vcc and the power supply voltage vE8. ing. Further, between the power supply voltage Vcc and the node n, an NPN bipolar transistor Q1 is connected in parallel with the capacitor C1.
and resistor R1 are connected in series.

The base terminals of the transistors Q1 and Q2 are supplied with a voltage Van that is level-shifted from the potential Va at the terminal A (or B) of the magnetic head drive circuit as shown in FIG.
and Va2 (where Va□×V a 2 ) are applied.

Furthermore, an NPN bipolar transistor Q4 is connected to the node n1 to which one terminal of the capacitor C1 is connected.
A constant current source CC1 is connected to the emitter terminal of this transistor Q4.

The emitter terminal of the transistor Q4 has the same <NP
The emitter of the N-type transistor Q3 is connected and drawn by a common constant current source CC1, thereby forming a current switch circuit. The potential vb of the terminal B of the circuit shown in FIG. 3 is applied to the base terminal of the transistor Q3. Furthermore, the collector terminals of the transistors Q3 and Q4 are
Current mirror-connected transistors Q5 and Q6 are connected, respectively.

In this embodiment, the potential of the node n1 is applied to the inverting and non-inverting input terminals of the comparators CMP and CMP2. Comparator C
The reference voltage V r e f is applied to the non-inverting input terminal of MP.
1, and a reference voltage Vref2 (Vraf2>Vrefl) is applied to the inverting input terminal of the comparator CMP2. As a result, when the potential of the node n1 becomes higher than the reference voltage V r e f2 or lower than Vreil, the abnormal signal φd is output.

Next, the operation of the abnormality detection circuit configured as described above will be explained.

When the write data signal D input to the head driving section shown in FIG. 3 changes periodically, the potentials Va and vb of the terminals A and B change accordingly. These voltages Va and vb are applied to the base terminals of differential transistors Q3 and Q4 as input signals of the abnormality detection circuit shown in FIG. 1, and the voltage Va is level-shifted by a level shift circuit (not shown). Val and Va2 (see FIG. 2) are applied to the base terminals of transistors Q1 and Q2.

Therefore, when the voltage Va changes to a high level and the voltage vb changes to a low level in response to a write data signal, for example, the transistor Q3 is turned on and the transistor Q4 is turned off.
Current begins to flow to the side of Qr.

Further, as the voltage Va changes to a high level, the voltage V
Since an and Va2 rise, PNP transistor Q2
is cut off and replaced by NPN transistor Q1.
is turned on. As a result, transistor Q1
Charge flows into node n1 via (current ix). At this time, since transistor Q4 is turned off, capacitor C1 is charged up. In addition, the transistor Q5 connected to the turned-on transistor Q3 and the transistor Q6 connected in a current mirror have the following characteristics:
Since a current of the same magnitude as that of transistor Q5 flows,
Charge flows into node n1 through transistor Q6 (current ir'). As a result, the potential V n 1 of the node n1 quickly rises as shown in FIG.

As the potential of node n1 rises, the emitter voltage of transistor Q1 rises, so transistor Q1 is turned off. Therefore, from now on, the current 11' is caused to flow toward the node n1 only from the side of the transistor Q6 through which the current is caused to flow by the current mirror. the result.

As shown in FIG. 2, the voltage V n 1 rises rapidly to a certain level and then shifts to a slow rise. Then, the write data signal changes, and the potential of terminal A becomes V
When a is changed from high level to low level, voltage vb is changed to high level at this time. Therefore, the transistor Q3 in the abnormality detection circuit is cut off and the transistor Q4 is turned on instead. Furthermore, since the signal Van, v62, which is the level-shifted voltage Va, also changes to a low level, the transistor Q2 is turned on (Ql remains off).

As a result, the charge accumulated in the capacitor C1 is quickly extracted through the transistors Q2 and Q4, and the potential Vnl of the node nl drops. Then, when the potential Vn of the node n1 falls to a predetermined level, the transistor Q2 is cut off, and the current 1 flowing through Q2
2 is blocked.

At this time, however, since transistor Q3 is cut off by voltage Va, no current flows through transistors Q5 and Q6 either. Therefore, capacitor C1
The charges accumulated in the transistor Q4 are then gradually extracted through the transistor Q4. As a result, when the potential Va at the terminal A is changed to a low level due to a change in the write data signal, the potential at the node n1 rapidly decreases to a predetermined level, and then slowly begins to decrease.

The write data signal changes periodically, and the potential V of terminal A
As long as a is changed within a certain period of time, the potential Vnl of the node n1 in the abnormality detection circuit repeats rising and falling due to the above operation, and the reference voltages V r e f 1 and V r
e f never exceeds 2. Therefore, the outputs of the comparators CMP1 and CMP2 are not changed, and the abnormal signal φd is not output.

However, if the write data signal entering the head drive unit is fixed at high or low level due to a short circuit in the head or a circuit failure, terminals A and B
The potentials Va and Vb do not change even after a certain period of time. Then, when the potential Va is at a high level, charges continue to be charged to the capacitor C1 through the transistor Q6, and as shown by the broken line A in FIG. 2, the potential Vn1 of the node n finally reaches the reference voltage V r a f 2. I'll go beyond it. Furthermore, if the voltage Va remains at a low level, the charge in the capacitor C1 continues to be discharged through the transistor Q4, and as shown by the broken line in FIG.
Finally, the potential Vnl of node n1 reaches the reference voltage V r e
f will drop below 1. As a result, the output of comparator CMPI or CMP2 is inverted and the abnormal signal φ
d is formed.

As explained above, according to this embodiment, if the write data signal or the potential of terminal A (or B) remains unchanged at either high level or low level, this can be reliably detected. The abnormal signal φd can be formed by

Moreover, like the abnormality detection circuit shown in FIG.

There is no need to feed back changes in the potential of the node n1 in the abnormality detection circuit to the preceding circuit that holds the potential of the output terminal A (or B) of the head drive unit, so the circuit scale of the entire abnormality detection circuit is small. Therefore, the chip size can be reduced.

Furthermore, since the abnormality detection circuit of this embodiment does not have a transistor that operates in saturation, there is no need to take care to stabilize the substrate potential around the transistor. Therefore, there is an advantage that circuit layout design etc. are facilitated.

[Effects] (1) In a recording/reproducing IC for a magnetic disk device, in addition to a transistor for instantaneously discharging a capacitor to a predetermined level by the potential of the output terminal of the head drive unit that fluctuates in accordance with a write data signal, In addition to providing transistors that instantly charge up the capacitor to a predetermined level, an abnormality detection circuit is configured to gradually continue discharging or charging up the capacitor after the capacitor is discharged or charged up by these transistors. , the ability to detect whether the supplied write data signal remains unchanged at high or low level eliminates the need for a feedback mechanism, thereby reducing the circuit size of the abnormality detection circuit. It has the effect of being

(2) In addition to the transistor that instantly discharges the capacitor to a predetermined level using the potential of the output terminal of the head drive unit that changes according to the write data signal, the transistor that instantly charges up the capacitor to a predetermined level. In addition, after the capacitor is discharged or charged up by these transistors, an abnormality detection circuit is configured to prevent the gradual discharge or charge-up from continuing.As a result, there are no transistors operating in saturation. This has the effect of facilitating circuit layout design and the like.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, two comparators and their reference voltages are provided for detection, but it is also possible to use only one comparator.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to an abnormality detection circuit in a recording/reproducing IC of a magnetic disk device, which is the field of application in which the invention was made, but the present invention is not limited to this. It can be widely used in cases where it is desired to monitor whether a certain signal has maintained a predetermined level for a certain period of time or more.

[Brief explanation of drawings]

Figure 1 shows the present invention as a recording/reproducing IC for a magnetic disk device.
FIG. 2 is a time chart showing changes in signals of each part in the circuit. FIG. 3 is a circuit diagram showing an example of the configuration of a head drive section in a recording/reproducing IC of a magnetic disk device, and FIG. 4 is a circuit diagram showing an example of an abnormality detection circuit in a conventional recording/reproducing IC of a magnetic disk device. It is a diagram. Qloo... Charge transistor, C2... Discharge transistor, Qs = C4...
Differential transistor, CC, -CC2... Constant current source, C1... Capacitor, CMP, , CMP2...
·comparator. Figure 1vA Figure 2

Claims (1)

[Claims] 1. A current switch circuit including a pair of differential transistors operated by a signal to be monitored and its inverted signal or a signal complementary thereto; one differential transistor and a power supply voltage; a capacitor connected between the capacitor and a charging transistor and a discharging transistor connected to one terminal of the capacitor and controlled to turn on and off by a signal corresponding to the monitoring signal;
a comparator that detects the charging voltage of the capacitor, and is configured such that the output of the comparator changes when the level of the monitoring signal maintains the same level for a certain period of time. . 2. The current switch circuit includes a transistor connected to a current mirror, and when the discharge path of the capacitor is cut off, the capacitor is charged up by the current flowing through the transistor by the current mirror. A semiconductor integrated circuit according to claim 1, characterized in that: 3. The charging transistor is an NPN bipolar transistor connected between one terminal of the capacitor and the first power supply voltage of the circuit, and the discharging transistor is connected between one terminal of the capacitor and the circuit. The semiconductor integrated circuit according to claim 1 or 2, characterized in that the semiconductor integrated circuit comprises a PNP type bipolar transistor connected between the second power supply voltage and the second power supply voltage.