KR19980066614A - Hysteresis type voltage comparator - Google Patents

Abstract

The present invention relates to a voltage comparator having hysteresis characteristics designed to design an accurate hysteresis voltage, comprising: a bias circuit unit generating a DC bias voltage; A comparator which is DC biased by the bias circuit section and compares a predetermined reference voltage with an input voltage; A current mirror provided to the load of the comparator and changing the output current value of the comparator to a first current value and a second current value in response to the output current of the comparator; And an output buffer for hysterically driving the output voltage in response to the first and second current values.

Description

Hysteresis type voltage comparator

The present invention relates to a voltage comparator having hysteresis characteristics, and more particularly, to a voltage comparator having hysteresis characteristics designed to design an accurate hysteresis voltage.

1 is a diagram showing a circuit diagram of a comparator according to the prior art. Conventional hysteresis characteristics of the comparator is a voltage divider (DIVIDER) consisting of resistors R4 and R5, a voltage comparator capable of comparing an input voltage and a reference voltage, and a resistor R6 and a transistor capable of generating a hysteresis voltage. It consists of Q4.

The operation principle of this circuit is as follows. Compare the reference voltage of the voltage divider consisting of resistors R3, R4, and R5 with the input voltage of the voltage comparator, and when the input voltage increases and exceeds the reference voltage, transistor Q5 is turned on and transistors Q4 and Q6 are turned on and resistor R5 The parallel resistance of and R6 is formed, so that the reference voltage of the voltage comparator is set lower than the initial setting value, thereby forming the hysteresis voltage. Thus, even if the input voltage is lowered again, the output voltage of transistor Q6 can be kept low by the hysteresis voltage. In such a structure, it is difficult to design an accurate hysteresis voltage because a design considering the saturation voltage relationship of transistor Q4 is required.

An object of the present invention is to provide a voltage comparator having hysteresis characteristics designed to design an accurate hysteresis voltage.

In order to achieve the above object, a voltage comparator having a hysteresis characteristic according to the present invention includes: a bias circuit unit generating a DC bias voltage; A comparator which is DC biased by the bias circuit section and compares a predetermined reference voltage with an input voltage; A current mirror provided to the load of the comparator and changing the output current value of the comparator to a first current value and a second current value in response to the output current of the comparator; And an output buffer for hysterically driving the output voltage in response to the first and second current values.

1 is a circuit diagram of a comparator according to the prior art.

2 is a circuit diagram of a comparator according to the present invention.

3 is a diagram illustrating an output waveform and an input waveform according to the circuit shown in FIG. 2.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a comparator according to the present invention, and FIG. 3 is a diagram showing an output waveform according to the circuit shown in FIG.

The circuit shown in FIG. 2 is a DC biasing circuit section 10 composed of transistors Q1, resistors R8, and R4, and transistors Q2, Q5, Q6, and resistor R7 so that the magnitudes of the reference voltage Vref and the input voltage Vin can be compared. Comparator 20 is configured to provide a load of the comparator 20, the output current value of the comparator 20 in response to the output current of the constant current source 10 to the first current value and the second current value A current mirror 30 composed of transistors Q7, Q8, resistors R1, R2, transistors Q3, Q4, Q9, Q10 to hysterically drive the output voltage in response to the first and second current values And an output buffer 40 composed of resistors R5 and R6. The transistor Q1 is connected to the transistors Q2, Q3, and Q4 in the form of a current mirror to provide the DC biasing voltages of the comparator 20 and the output buffer 40.

The comparator 20 is connected between the emitter constant current sources Q2 and R7 connected between the power supply voltage Vcc and the first node N1, and between the first node N1 and the second node N2. The first transistor Q5 of the first conductivity type and pnp type, to which the reference voltage Vref is applied to the base, is connected between the first node N1 and the third node N3 and the input voltage Vin ) Includes a second transistor Q6 of the first conductivity type applied to the base.

The current mirror 30 is connected to the second node N2 and the fourth node N4, and the first transistor Q8 of npn, whose second base is connected to the third node N3, A second transistor Q7 of the second conductivity type connected between the third node N3 and the fifth node N5 and a base connected to the third node N3, and the fourth node N4. The first resistor R2 is connected between ground, and the second resistor R1 is connected between the fifth node N5 and ground.

The output buffer 40 is a third transistor of a second conductivity type having a base connected to the second node N2, a constant current (provided by Q3 and R6) supplied to the collector, and an emitter connected to the fourth node. (Q9) and the fourth transistor (Q10) of the second conduction type having a base connected to the collector of the third transistor (Q9), a constant current (provided by Q4, R5) supplied to the collector, and the emitter grounded. Include.

Referring to the operation of this circuit, when the input voltage increases and becomes higher than the reference voltage by comparing the input voltage Vin and the reference voltage Vref of the comparator 20, the collector current of Q6 decreases and thus the collector of Q7 and Q8. The current is also reduced, so that the collector current of Q5 increases more than the current sinked to Q8 so that the base current of Q9 flows to the first current value, but the emitter current of Q9 also increases and flows to R2. Since the voltage across R2 increases, the input voltage must be sufficiently high compared to the reference voltage. However, when the base potential of Q9 is sufficiently increased and Q9 is sufficiently turned on, the collector potential drops to a low state and Q10 is turned off. The output voltage of the buffer 40 is inverted from a low state to a high state.

On the contrary, when the input voltage is lower than the reference voltage, the collector current of Q6 increases, so that the current capability of sinking in Q8 increases, but the emitter current of Q9 is still provided to the fourth node, thereby charging the second node. Because the charged charges cannot escape through Q8 at high speed, the output voltage does not fall low and remains high. As the input voltage continues to drop, the collector current of Q6 further increases, so that the current sinking capability of Q8 also increases, so even if the emitter current of Q9 is supplied to the fourth node N4, the charge of the second node N2 is reduced. Since the base emitter voltage of Q9 is reduced and the Q9 is turned off because Q9 is turned to some extent, the output voltage of the output buffer 40 falls to a low state because Q10 is turned on. Since the charge of the second node is quickly discharged through Q8, the output voltage of the output buffer 40 is kept low.

3A and 3B illustrate output waveforms and input waveforms in a circuit according to the present invention, respectively. In FIG. 3A, the interval between the solid line and the dotted line graph represents the hysteresis voltage Vhys, and in FIG. 3B, the solid line graph represents the input voltage Vin and the dotted line graph represents Vref.

As described above, in the present invention, since the output voltage is inverted from the low state to the high state at an input voltage higher than the reference voltage, and the output voltage is inverted from the high state to the low state at an input voltage lower than the reference voltage, there is a hysteresis characteristic. The setting of the two pointer values of the hysteresis of the present invention is a constant current value of Q3, so that the designer can arbitrarily adjust the hysteresis voltage pointer.

As described above, according to the voltage comparator having hysteresis characteristics according to the present invention, the hysteresis voltage can be accurately designed because the constant current value can be adjusted without considering the saturation relationship by the transistor in the circuit. have.

Claims (4)

A bias circuit unit generating a DC bias voltage; A comparator which is DC biased by the bias circuit section and compares a predetermined reference voltage with an input voltage; A current mirror provided to the load of the comparator and changing the output current value of the comparator to a first current value and a second current value in response to the output current of the comparator; And an output buffer for hysterically driving the output voltage in response to the first and second current values. 2. The apparatus of claim 1, wherein the comparator comprises: an emitter constant current source coupled between the power supply voltage and the first node; A first transistor of a first conductivity type connected between the first node and a second node and having the reference voltage applied to a base; And And a second transistor of a first conductivity type connected between said first node and a third node, said input voltage being applied to a base. The semiconductor device of claim 2, wherein the current mirror comprises: a first transistor of a second conductivity type connected to the second node and a fourth node, and a base of which is connected to the third node; A second transistor of a second conductivity type connected between the third node and a fifth node and having a base connected to the third node; A first resistor coupled between the fourth node and ground; A second resistor connected between the fifth node and ground; And the output current of the comparator is supplied to the fourth node. 4. The transistor of claim 3, wherein the output buffer comprises: a third transistor of a second conductivity type having a base connected to the second node, a constant current supplied to the collector, and an emitter connected to the fourth node; And A hysteresis voltage comprising a fourth transistor of a second conductivity type having a base connected to the collector of the third transistor, a constant current supplied to the collector, and an emitter grounded, and an output terminal connected to the collector of the fourth transistor. Comparator.