JPS61177762A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61177762A
JPS61177762A JP60017823A JP1782385A JPS61177762A JP S61177762 A JPS61177762 A JP S61177762A JP 60017823 A JP60017823 A JP 60017823A JP 1782385 A JP1782385 A JP 1782385A JP S61177762 A JPS61177762 A JP S61177762A
Authority
JP
Japan
Prior art keywords
corners
pad
pads
rounded
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60017823A
Other languages
Japanese (ja)
Other versions
JPH0418694B2 (en
Inventor
Shinjiro Kojima
小島 伸次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60017823A priority Critical patent/JPS61177762A/en
Publication of JPS61177762A publication Critical patent/JPS61177762A/en
Publication of JPH0418694B2 publication Critical patent/JPH0418694B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive to improve the product yield by eliminating the generation of cracks in the insulation plate even when the insulation plate is thinned or pads and adhesion copper plates are thickened in order to improve thermal conduction to a heat dissipating plate, by method wherein the corners of pads and the like directly joined to an insulation plate are rounded. CONSTITUTION:Wire bonding pads 23 and chip mounting pads 24 are joined to the top of an insulation plate (DBC substrate) 33 by direct junction, the corners of which pads are rounded at R=1.0mm. This rounding can be easily carried out by etching or press punching. The value of R can be selected suitably without restriction to 1mm. Otherwise, only the corners of each chip constituting squares of a pad group including the wire bonding apds 23 and the chip mounting pads 24 can be rounded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はパワー半導体装置ブロックからなる半導体装置
に関し、更に詳しくはパワー半導体装置ブロックが絶縁
板ユニット構造と呼ばれる構造をもち、モジュール化に
好適なものに使用される。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device comprising a power semiconductor device block, and more specifically, a power semiconductor device block having a structure called an insulating plate unit structure and suitable for modularization. used for.

〔発明の技術的背景〕[Technical background of the invention]

パワートランジスタやそれを直列、並列に接続したパワ
ートランジスタモジュールを製作するにあたっては、そ
れらを高度に共通互換性のあるパワートランジスタブロ
ックで構成することが便利である。そのようなモジュー
ルの単位となるブロックは、ブロック自体の部品点数が
少なく組立工程が簡単であると共に、モジュール化のた
めの端子接続が容易であることが必要である。
When manufacturing power transistors and power transistor modules in which power transistors are connected in series or parallel, it is convenient to configure them with highly commonly compatible power transistor blocks. A block serving as a unit of such a module needs to have a small number of parts and a simple assembly process, and also need to be easy to connect terminals for modularization.

本発明者は上記の如きパワートランジスタブロックから
なる半導体装置に関し、先に特許出願(特開昭57−1
11054号、特開昭57−166037号等)をした
が、これらのものの概要を添付図面の第8図乃至第12
図を参照して説明する。なお、図面の説明において同一
要素は同一符号で示しである。
The present inventor previously filed a patent application (Japanese Unexamined Patent Application Publication No. 57-1999) regarding a semiconductor device consisting of a power transistor block as described above.
No. 11054, Japanese Unexamined Patent Publication No. 57-166037, etc.).
This will be explained with reference to the figures. In addition, in the description of the drawings, the same elements are indicated by the same reference numerals.

第8図は絶縁板ユニット構造のパワートランジスタブロ
ックを、モールド型のモジュールに組立てた場合の要部
断面図である。即ちパワートランジスタブロック20は
、絶縁板33と、その表面に配設されたワイヤボンディ
ング用パッド22゜23とチップマウント用パッド24
を有している。
FIG. 8 is a sectional view of a main part when a power transistor block having an insulating plate unit structure is assembled into a molded module. That is, the power transistor block 20 includes an insulating plate 33, wire bonding pads 22 and 23 and chip mounting pads 24 provided on the surface of the insulating plate 33.
have.

そして、半導体チップ5をマウント用パッド24にマウ
ントすると共にパッド22.23にワイヤボンディング
する。そしてこのブロックを2個20.20’用意し、
放熱板7上に接着銅板25などを介して接着し、外部端
子の接続および樹脂封止してモジュール化したものであ
る。
Then, the semiconductor chip 5 is mounted on the mounting pad 24 and wire-bonded to the pads 22 and 23. Then prepare two of these blocks 20.20',
It is made into a module by adhering it onto the heat sink 7 via an adhesive copper plate 25 or the like, connecting external terminals, and sealing it with resin.

このようなものは、部品点数が絶縁板33、ワイヤボン
ディング用パッド22.23、チップマウント用パッド
24及び接着銅板25の合計5部品であるだけである。
This type of device has only five parts in total: the insulating plate 33, the wire bonding pads 22, 23, the chip mounting pads 24, and the bonded copper plate 25.

更にワイヤボンディング用パッド22.23とチップマ
ウント用パッド24とに接着用銅板25と同様の銅板を
用い、それらをセラミック絶縁板33上に直接接合法に
より配設した場合には、特に大幅な工程数の短縮が可能
になる。
Furthermore, when the wire bonding pads 22, 23 and the chip mounting pads 24 are made of copper plates similar to the adhesive copper plate 25, and they are directly bonded onto the ceramic insulating plate 33, a particularly large process is required. The number can be reduced.

上記の如き銅板のセラミック板に対する直接接合法とは
、表面が酸化した銅板をセラミック板に′   重ねた
状態で1065℃以上1085℃以下の実質温度に保持
し、cu20−Cu共共融融液接合面を濡らし、そのま
ま冷却して直接接合するという、米国ゼネラルエレクト
リック社の開発に基づく方法を意味する。この直接接合
法に特に適する銅板は、タフピッチ鋼、0FHC銅、銀
銅などであり、また特に適するセラミック板はアルミナ
などである。 第9図は直接接合法によるブロックの斜
視図である。同図において絶縁板33は板厚0.635
as+の96%アルミナ板を、またワイヤボンディング
用パッド22,23、チップマウント用パッド24及び
接着銅板25は板厚0.3amのタフピッチ銅板を用い
、1063℃の窒素雰囲気中に通して一工程でそれらを
強く固着せしめる。
The method of directly bonding a copper plate to a ceramic plate as described above is to hold a copper plate with an oxidized surface on top of a ceramic plate at a substantial temperature of 1065°C or more and 1085°C or less, and then bond the Cu20-Cu eutectic melt bonding surface. This refers to a method developed by General Electric Company in the United States, in which the materials are wetted, cooled, and directly bonded. Copper plates particularly suitable for this direct bonding method include tough pitch steel, 0FHC copper, silver copper, and the like, and ceramic plates particularly suitable include alumina and the like. FIG. 9 is a perspective view of a block formed by the direct bonding method. In the same figure, the insulating plate 33 has a thickness of 0.635
An AS+ 96% alumina plate was used, and the wire bonding pads 22 and 23, the chip mounting pad 24, and the adhesive copper plate 25 were tough pitch copper plates with a thickness of 0.3 am, and were passed through a nitrogen atmosphere at 1063°C in one step. Make them stick firmly.

次に端子をブロック周辺部の端子エリア4.41゜42
に配設し、それぞれベース、エミッタ、コレクタ端子と
し、チップマウント用パッド24上にチップ5、また必
要に応じてダイオード51などをマウントし、ボンディ
ングワイヤ6で接続してパワートランジスタブロック2
0を得る。
Next, attach the terminal to the terminal area around the block 4.41°42
The chip 5 is mounted on the chip mounting pad 24, and if necessary, the diode 51, etc. are mounted on the chip mounting pad 24, and connected with the bonding wire 6 to form the power transistor block 2.
Get 0.

第10図は並列及び直列接続モールド型パワートランジ
スタモジュールの平面図、第11図(a)は並列接続モ
ジュールに用いた外部端子配置図、同図(b)は同等価
回路図、第12図(a)直列接続モジュールに用いた外
部端子配置図、同図(b)は同等価回路図である。なお
、第10図〜第12図において7は放熱板、8は外部端
子、91はケース、TR1,TR2はトランジスタ素子
、DI 、D2はダイオード素子である。
Fig. 10 is a plan view of parallel and series connected molded power transistor modules, Fig. 11 (a) is an external terminal arrangement diagram used in the parallel connection module, Fig. 11 (b) is an equivalent circuit diagram, and Fig. 12 ( a) A diagram showing the arrangement of external terminals used in the series-connected module, and (b) the equivalent circuit diagram. 10 to 12, 7 is a heat sink, 8 is an external terminal, 91 is a case, TR1 and TR2 are transistor elements, and DI and D2 are diode elements.

〔背景技術の問題点〕[Problems with background technology]

上記の如き従来装置において、絶縁板に直接接合される
各パッドの角部は尖っている(鋭部を有する)。第13
図は各パッドを接合した絶縁板の平面図で、第14図は
その一部拡大図である。図示の如く、ワイヤボンディン
グ用パッド23、チップマウント用パッド24等の角部
は尖っており、このため角部に応力が集中しやすくなる
In the conventional device as described above, each pad that is directly bonded to the insulating plate has a sharp corner. 13th
The figure is a plan view of an insulating plate to which pads are bonded, and FIG. 14 is a partially enlarged view thereof. As shown in the figure, the corners of the wire bonding pad 23, the chip mounting pad 24, etc. are sharp, and therefore stress tends to concentrate on the corners.

ところで、放熱板への熱伝導を良好にするためには、絶
縁板の厚さは小さく、かつパッドおよび接着銅板の厚さ
は比較的大きくすることが望ましく、例えば第9図の従
来例では絶縁板33−0.635ag+に対してパッド
22〜24および接着銅板25−0.3amの厚さにな
っている。そして近年、回路の高集積化と大容量化のた
めこの傾向はさらに進み、絶縁板−0,4m+以下、パ
ッドおよび接着銅板−0,4履以上厚さのものが要求さ
れてきている。しかしながら、従来の形式のものでこれ
を実現すると、パッドの角部における応力の集中は増々
大きくなり、それに反してね縁板の強度は増々低下し、
従って角部に「割れ」が発生し易くなる。この絶縁板3
3の割れは第′、4図において符号101で示すように
現われ、このため製品の歩留りが著しく低下してしまう
By the way, in order to improve heat conduction to the heat sink, it is desirable that the thickness of the insulating plate be small and the thickness of the pad and bonded copper plate be relatively large. For example, in the conventional example shown in FIG. Pads 22 to 24 and bonded copper plate 25 have a thickness of 0.3 am to plate 33 of 0.635 ag+. In recent years, this trend has progressed further due to higher integration and larger capacity of circuits, and insulating plates with a thickness of 0.4 m or less and pads and bonded copper plates with a thickness of 0.4 m or more are now required. However, if this is achieved with the conventional type, the concentration of stress at the corners of the pad will increase, and on the other hand, the strength of the edge plate will decrease.
Therefore, "cracks" are likely to occur at the corners. This insulation board 3
The cracks No. 3 appear as indicated by the reference numeral 101 in FIGS.

〔発明の目的) 本発明は上記の如き従来技術の欠点を克服するためにな
されたもので、放熱板への熱伝導を良くするために絶縁
板を薄く、あるいはパッドおよび接着銅板を厚くした場
合にも、絶縁板に「割れ」が生じたりすることのない半
導体装置を提供することを目的とする。
[Object of the Invention] The present invention has been made to overcome the drawbacks of the prior art as described above. Another object of the present invention is to provide a semiconductor device in which "cracking" does not occur in an insulating plate.

〔発明の概要〕[Summary of the invention]

上記の目的を達成するため本発明は、絶縁板ユニット構
造をもつ半導体装置の絶縁板に直接接合法で接合された
ワイヤボンディング用バッド、およびチップマウント用
バッド等の角部に、丸みを付けた半導体装置を提供する
ものである。さらに本発明は、絶縁板および接着金属(
例えば銅)板についても、角部に丸みを付けた半導体装
置を提供するものである。
In order to achieve the above object, the present invention provides rounded corners of wire bonding pads, chip mounting pads, etc. that are bonded by direct bonding to an insulating plate of a semiconductor device having an insulating plate unit structure. The present invention provides a semiconductor device. Furthermore, the present invention provides an insulating plate and an adhesive metal (
For example, the present invention provides a semiconductor device with rounded corners for a copper plate as well.

〔発明の実施例〕[Embodiments of the invention]

以下、添付図面の第1図乃至第7図を参照して本発明の
いくつかの実施例を説明する。
Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 1 to 7 of the accompanying drawings.

第1図は同実施例の要部の斜視図である。絶縁板(DB
G基板)33の上面にはワイヤボンディング用バッド2
3およびチップマウント用パッド24が直接接合法で接
合されており、その角部にはR−1,0履の丸みが付け
られている。この丸みはエツチング法、プレス打抜き法
等により容易に付けることができる。また、Rの値は1
jIIIに限らず適宜選択することができる。
FIG. 1 is a perspective view of the main parts of the same embodiment. Insulating board (DB
G board) 33 has a wire bonding pad 2 on the top surface.
3 and a chip mounting pad 24 are joined by a direct joining method, and their corners are rounded to R-1,0. This roundness can be easily imparted by etching, press punching, or the like. Also, the value of R is 1
It can be selected as appropriate without being limited to jIII.

第2図は第1図に示す実施例の変形例の要部の平面図で
ある。第2図(a)はワイヤボンディング用バッド23
およびチップマウント用バッド24を含むパッド群の4
角を構成する各チップの角部のみに丸みを付けたもので
ある。応力の集中はパッド群の4角において特に著しく
、従ってこの部分で絶縁板33に「割れ」が生じ易いの
で、この部分にのみ丸みを付けることによって製品の歩
留りをかなり向上できる。
FIG. 2 is a plan view of a main part of a modification of the embodiment shown in FIG. 1. Figure 2(a) shows the wire bonding pad 23.
and 4 of the pad group including the chip mounting pad 24.
Only the corners of each chip that make up the corners are rounded. The concentration of stress is particularly significant at the four corners of the pad group, and therefore "cracks" are likely to occur in the insulating plate 33 in these parts, so by rounding only these parts, the yield of the product can be considerably improved.

第2図(b)はパッド群の4辺にある各チップの角部に
のみ丸みを付けたものである。パッド群の4角にある各
パッドの角部に次いで応力の集中が著しいのは、パッド
群の4辺にある各パッドの角部である。従うてこれらの
部分に丸みをつけることで、製品の歩留りを大幅に向上
できる。
In FIG. 2(b), only the corners of each chip on the four sides of the pad group are rounded. Next to the corner portions of each pad at the four corners of the pad group, stress is most concentrated at the corner portions of each pad at the four sides of the pad group. Therefore, by rounding these parts, the yield of the product can be greatly improved.

第2図(C)は各パッドの角部のうち、鈍角部分以外の
角部に丸みを付けたものである。パッド群の4辺にある
各パッドの角部に次いで応力の集中し易いのは、この鈍
角部分以外の内側の角部である。従ってこれらの部分に
丸みを付けることで、絶縁板の「割れ」はほとんど解消
される。
In FIG. 2(C), the corners of each pad other than the obtuse angle portions are rounded. Next to the corners of each pad on the four sides of the pad group, stress is likely to be concentrated at the inner corners other than the obtuse angle portions. Therefore, by rounding these parts, most of the "cracks" in the insulation board can be eliminated.

第2図(d)は第1図のものと同等のもので、このよう
にすれば最大の効果が得られる。なお、上記の第2図(
b)〜(d)の変形例において、応力集中の大きさに応
じてRの値を変えるようにするとより効果的である。
FIG. 2(d) is equivalent to that in FIG. 1, and the maximum effect can be obtained by doing so. In addition, the above figure 2 (
In the modified examples b) to (d), it is more effective to change the value of R depending on the magnitude of stress concentration.

第3図は本発明の他の実施例の要部の平面図である。こ
れが第2図(a)のものと異なる点は、パッド群の角部
のみならず絶縁板の角部においても丸みが付けられてい
ることである。このようにすれば、絶縁板32の下側か
らの応力に対しても十分に対応できる。
FIG. 3 is a plan view of essential parts of another embodiment of the present invention. This differs from the one shown in FIG. 2(a) in that not only the corners of the pad group but also the corners of the insulating plate are rounded. In this way, it is possible to sufficiently cope with stress from below the insulating plate 32.

第4図はこの事情を説明するための半導体装置の断面図
である。放熱板7には半導体モジュールを囲むようにエ
ポキシ樹脂製のカバー26が接着剤27により固着され
ており、チップ5はゴム状のチップエンキャップ28で
覆われている。そして、カバー26内はゲル状のエンキ
ャップ剤29で満されている。
FIG. 4 is a sectional view of a semiconductor device for explaining this situation. An epoxy resin cover 26 is fixed to the heat sink 7 with an adhesive 27 so as to surround the semiconductor module, and the chip 5 is covered with a rubber-like chip cap 28. The inside of the cover 26 is filled with a gel-like encapsulant 29.

このような半導体装置において、接着剤27は絶縁板3
3と放熱板7の間に入り込み易く、これらが原因で絶縁
板33の角部に応力が集中し易くなる。そこで第3図に
示すように絶縁板の角部に丸みを持たせれば、パッド2
3.24等による応力の集中のみならず、接着剤27等
による下側からの応力集中をも緩和できる。なお、第3
図ではパッド群の4角を構成する各パッドの角部のみに
丸みを付けたが、第2図(b)〜(d)の如く各パッド
の他の角部についても丸みを付けてもよいことは言うま
でもない。
In such a semiconductor device, the adhesive 27 is attached to the insulating plate 3.
3 and the heat dissipating plate 7, and stress tends to concentrate on the corners of the insulating plate 33 due to these factors. Therefore, if the corners of the insulating plate are rounded as shown in Figure 3, the pad 2
Not only stress concentration due to 3.24 etc. but also stress concentration from below due to adhesive 27 etc. can be alleviated. In addition, the third
In the figure, only the corners of each pad constituting the four corners of the pad group are rounded, but other corners of each pad may also be rounded as shown in Figure 2 (b) to (d). Needless to say.

第5図は本発明のさらに他の実施例の要部の底面図であ
る。この実施例では、絶縁板33の底面に直接接合法で
接合された接着銅板25の4角に丸みを付けている。こ
の方式と前記の方式を併用すれば、さらに大きな効果を
あげることができる。
FIG. 5 is a bottom view of the main parts of still another embodiment of the present invention. In this embodiment, the four corners of the bonded copper plate 25 bonded to the bottom surface of the insulating plate 33 by a direct bonding method are rounded. If this method and the above method are used together, even greater effects can be achieved.

なお、前記の第1図乃至第5図に示す実施例において、
絶縁板、パッドおよび接着銅板の厚さは特に限定されな
いが、絶縁板の厚さを0.4aa+程度にしたときに特
に有効である。
Note that in the embodiments shown in FIGS. 1 to 5 above,
Although the thickness of the insulating plate, pad, and bonded copper plate is not particularly limited, it is particularly effective when the thickness of the insulating plate is about 0.4 aa+.

次に、第6図および第7図を参照して上記実施例の効果
を説明する。
Next, the effects of the above embodiment will be explained with reference to FIGS. 6 and 7.

第6図はパッドの角部における丸みの有無と「割れ」発
生率の間係を示す特性図である。図から明らかなように
、絶縁板(A1203)の厚さt−0,635am+に
おいては、パッドの角部に丸みがないときはパッドの厚
さを0.4履以下としなければならないが、パッドの角
部に丸みがあるときはパッドの厚さを0.6m以上とす
ることができる。また、絶縁板の厚さt=0.4amに
おいては、パッドの角部に丸みがないときはパッドの厚
さを0.15am以下としなければならず、実用に供す
ることが難しくなるが、パッドの角部に丸みを付ければ
パッドの厚さを0.4am以上とすることができ、大き
な放熱効果を発揮できる。
FIG. 6 is a characteristic diagram showing the relationship between the presence or absence of roundness at the corners of the pad and the occurrence rate of "cracking". As is clear from the figure, when the thickness of the insulating plate (A1203) is t-0,635am+, if the corners of the pad are not rounded, the thickness of the pad must be 0.4 or less. When the corners of the pad are rounded, the thickness of the pad can be 0.6 m or more. In addition, when the thickness of the insulating plate is t = 0.4 am, if the corners of the pad are not rounded, the thickness of the pad must be 0.15 am or less, which makes it difficult to put it into practical use. By rounding the corners of the pad, the thickness of the pad can be made 0.4 am or more, and a large heat dissipation effect can be achieved.

パッドの角部に丸みを付けることは、外部端子の半田付
けによる応力集中にも有効である。第7図はその事情を
説明するためのもので、第7図(a)は斜視図、第7図
(b)はそのA−All断面図である。第7図において
、外部端子8の厚さtlは0.7〜0.8履程度あり、
半田43の厚みt2も0.5s程度に達する。このため
、ワイヤボンディング用パッド23の外部端子近傍の角
部には応力集中が特に著しく、「割れ」が発生し易くな
る。しかしながら、本発明の如く角部に丸みを付ければ
、応力集中をやわらげて製品の歩留りの向上にもなる。
Rounding the corners of the pad is also effective in reducing stress concentration due to soldering of external terminals. FIG. 7 is for explaining the situation; FIG. 7(a) is a perspective view, and FIG. 7(b) is an A-All sectional view thereof. In FIG. 7, the thickness tl of the external terminal 8 is approximately 0.7 to 0.8 mm.
The thickness t2 of the solder 43 also reaches about 0.5 seconds. Therefore, stress concentration is particularly significant at the corners of the wire bonding pads 23 near the external terminals, and "cracking" is likely to occur. However, if the corners are rounded as in the present invention, stress concentration can be reduced and the yield of products can be improved.

さらに本発明によれば、角部の丸みの有無によって絶縁
板、パッドの厚さ、あるいは放熱効果の表示ができると
いう格別の効果がある。すなわち、前述のように絶縁板
およびパッド等の厚さと放熱効果には相開関係があり゛
、かつ絶縁板が薄くなれば「割れ」が生じやすく、パッ
ド等が厚(なれば「割れ」が生じやすくなるという関係
がある。そこで、放熱効果を最大にするために最も「割
れ」易くな、つたものを例えば第2図(d)の如き構成
とし、次に「割れ」易くなったものを第2図(C)の如
き構成とし、順次、放熱効果の大きい順すなわち「割れ
」易くなったものの順に第2図(b)。
Further, according to the present invention, there is a special effect that the thickness of the insulating plate or pad or the heat dissipation effect can be displayed depending on the presence or absence of roundness of the corners. In other words, as mentioned above, there is a phase relationship between the thickness of insulating plates, pads, etc. and the heat dissipation effect, and the thinner the insulating plate is, the more likely it is that cracks will occur; Therefore, in order to maximize the heat dissipation effect, the material that is most likely to "break" is configured as shown in Figure 2 (d), and then the material that is most likely to "break" is The configuration is as shown in FIG. 2(C), and the heat dissipation effect is increased, that is, the one that is more likely to break, as shown in FIG. 2(b).

(a)の如き構成とする。このようにすれば、−児して
放熱効果の大小、許容発熱量の大小等を判別できる。
The configuration is as shown in (a). In this way, it is possible to determine the magnitude of the heat dissipation effect, the magnitude of the allowable calorific value, etc.

なお、以上説明した効果は、絶縁板としてAl2O3の
セラミックを用いた場合に限らず1、A I N等を用
いたときにも奏することができ、パッド等として銅板以
外の金属板を用いた場合にも奏することができる。
The effects explained above are not limited to the case where Al2O3 ceramic is used as the insulating plate, but can also be achieved when using AIN, etc., and when a metal plate other than a copper plate is used as the pad etc. It can also be played.

〔発明の効果〕〔Effect of the invention〕

上記の如く本発明では、絶縁板ユニット構造をもつ半導
体装置の絶縁板に直接接合されたパッド等の角部に丸み
を付けるようにしたので、放熱板・への熱伝導を良くす
るために絶縁板を薄く、あるいはパッドおよび接着銅板
を厚くした場合にも、絶縁板に「割れ」が生じたりする
ことなく、従って製品の歩留りを著しく向上させること
のできる半導体装置が得られる。また、角部に丸みを付
けることは容易に実現できるので、特に製造コストを上
昇させることもない。
As described above, in the present invention, the corners of the pads, etc. directly bonded to the insulating plate of a semiconductor device having an insulating plate unit structure are rounded, so that the insulating plate is insulated to improve heat conduction to the heat dissipation plate. Even when the plate is made thinner or the pads and bonded copper plate are made thicker, the insulating plate does not "crack" and therefore a semiconductor device can be obtained which can significantly improve the product yield. Further, since rounding of the corners can be easily achieved, the manufacturing cost does not particularly increase.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の要部の斜視図、第2図は同
実施例の変形例の要部の平面図、第3図は本発明の他の
実施例の要部の平面図、第4図は同実施例に特有の効果
を説明するための断面図、第5図は本発明のさらに他の
実施例の要部の底面図、第6図は本発明の詳細な説明す
る特性図、第7図は本発明の格別の効果を説明するため
の斜視図および断面図、第8図は絶縁基板を用いた従来
モジュールの要部断面図、第9図はこの絶縁基板にチッ
プを搭載したときの斜視図、第10図はこのモジュール
の完成前の平面図、第11図はこのモジュールの平面図
および等価回路図、第12図はこのモジュールの他の例
の平面図および等価回路図、第13図は従来装置の要部
の平面図、第14図はその一部拡大図である。 5・・・チップ、7・・・放熱板、8・・・外部端子、
23・・・ワイヤボンディング用パッド、24・・・チ
ップマウント用パッド、25・・・接着銅板、26・・
・カバー、27・・・接着剤、28・・・チップエンキ
ャップ、33・・・絶縁板。 出願人代理人  猪  股     情事1図 j 第2図(a) 第2図(c) LI 第2図(d) J 第3図 第4図 第5図 第7図(a) ”l 第7図(b) 第8図 第9図 第10図 1U   ’/    lLJ   ’dl第11図 (a)(b) 第12図
FIG. 1 is a perspective view of the main part of an embodiment of the present invention, FIG. 2 is a plan view of the main part of a modification of the same embodiment, and FIG. 3 is a plan view of the main part of another embodiment of the invention. FIG. 4 is a sectional view for explaining effects specific to the same embodiment, FIG. 5 is a bottom view of a main part of still another embodiment of the present invention, and FIG. 6 is a detailed explanation of the present invention. 7 is a perspective view and a sectional view for explaining the special effects of the present invention, FIG. 8 is a sectional view of the main part of a conventional module using an insulating substrate, and FIG. 9 is a characteristic diagram of this insulating substrate. FIG. 10 is a plan view of this module before completion; FIG. 11 is a plan view and an equivalent circuit diagram of this module; FIG. 12 is a plan view and an equivalent circuit diagram of another example of this module. An equivalent circuit diagram, FIG. 13 is a plan view of the main part of the conventional device, and FIG. 14 is a partially enlarged view. 5... Chip, 7... Heat sink, 8... External terminal,
23... Pad for wire bonding, 24... Pad for chip mounting, 25... Adhesive copper plate, 26...
- Cover, 27... Adhesive, 28... Chip encap, 33... Insulating plate. Applicant's agent Inomata Affair Figure 1j Figure 2 (a) Figure 2 (c) LI Figure 2 (d) J Figure 3 Figure 4 Figure 5 Figure 7 (a) ''l Figure 7 (b) Figure 8 Figure 9 Figure 10 Figure 1U'/lLJ'dlFigure 11 (a) (b) Figure 12

Claims (1)

【特許請求の範囲】 1、ほぼ方形の絶縁板の上面に直接接合法で少なくとも
ワイヤボンディング用パッドおよびチップマウント用パ
ッドを含むパッド群を接合し、この絶縁板の下面に接着
金属板を介して直接接合法で放熱板を接合した半導体装
置において、前記パッド群を構成する各パッドの角部に
丸みを付けたことを特徴とする半導体装置。 2、前記パッド群の4角を構成する前記各パッドの角部
に丸みを付けた特許請求の範囲第1項記載の半導体装置
。 3、前記パッド群の4辺内にある前記各パッドの角部に
丸みを付けた特許請求の範囲第1項記載の半導体装置。 4、前記各パッドの各角部のうち鈍角部分を除く他の角
部に丸みを付けた特許請求の範囲第1項記載の半導体装
置。 5、ほぼ方形の絶縁板の上面に直接接合法で少なくとも
ワイヤボンディング用パッドおよびチップマウント用パ
ッドを含むパッド群を接合し、この絶縁板の下面に接着
金属板を介して直接接合法で放熱板を接合した半導体装
置において、前記パッド群を構成する各パッドの角部に
丸みを付け、かつ前記絶縁板の4角に丸みを付けたこと
を特徴とする半導体装置。 6、前記パッド群の4角を構成する前記各パッドの角部
に丸みを付けた特許請求の範囲第5項記載の半導体装置
。 7、ほぼ方形の絶縁板の上面に直接接合法で少なくとも
ワイヤボンディング用パッドおよびチップマウント用パ
ッドを含むパッド群を接合し、この絶縁板の下面に接着
金属板を介して直接接合法で放熱板を接合した半導体装
置において、前記パッド群を構成する各パッドの角部に
丸みを付け、かつ前記絶縁板および接着金属板の4角に
丸みを付けたことを特徴とする半導体装置。 8、前記パッド群の4角を構成する前記各パッドの角部
に丸みを付けた特許請求の範囲第7項記載の半導体装置
[Claims] 1. A pad group including at least a wire bonding pad and a chip mounting pad is bonded to the upper surface of a substantially rectangular insulating plate by a direct bonding method, and a pad group including at least a wire bonding pad and a chip mounting pad is bonded to the lower surface of this insulating plate via an adhesive metal plate. What is claimed is: 1. A semiconductor device in which a heat sink is bonded by a direct bonding method, characterized in that corners of each pad constituting the pad group are rounded. 2. The semiconductor device according to claim 1, wherein the corners of each of the pads constituting the four corners of the pad group are rounded. 3. The semiconductor device according to claim 1, wherein corners of each of the pads within four sides of the pad group are rounded. 4. The semiconductor device according to claim 1, wherein the corners of each pad other than the obtuse angle portions are rounded. 5. A group of pads including at least wire bonding pads and chip mounting pads are bonded to the top surface of a substantially rectangular insulating plate by a direct bonding method, and a heat sink is bonded to the bottom surface of this insulating plate by a direct bonding method via an adhesive metal plate. A semiconductor device in which the corners of each pad constituting the pad group are rounded, and the four corners of the insulating plate are rounded. 6. The semiconductor device according to claim 5, wherein corners of each of the pads constituting the four corners of the pad group are rounded. 7. A group of pads, including at least wire bonding pads and chip mounting pads, is bonded to the upper surface of a substantially rectangular insulating plate by a direct bonding method, and a heat sink is bonded to the bottom surface of this insulating plate by a direct bonding method via an adhesive metal plate. A semiconductor device in which the corners of each pad constituting the pad group are rounded, and the four corners of the insulating plate and the adhesive metal plate are rounded. 8. The semiconductor device according to claim 7, wherein corners of each of the pads constituting four corners of the pad group are rounded.
JP60017823A 1985-02-01 1985-02-01 Semiconductor device Granted JPS61177762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60017823A JPS61177762A (en) 1985-02-01 1985-02-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60017823A JPS61177762A (en) 1985-02-01 1985-02-01 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61177762A true JPS61177762A (en) 1986-08-09
JPH0418694B2 JPH0418694B2 (en) 1992-03-27

Family

ID=11954445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60017823A Granted JPS61177762A (en) 1985-02-01 1985-02-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61177762A (en)

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EP1814153A2 (en) * 1996-09-12 2007-08-01 Ibiden Co., Ltd. Circuit board for mounting electronic parts
EP1814153A3 (en) * 1996-09-12 2008-09-24 Ibiden Co., Ltd. Circuit board for mounting electronic parts
USRE44251E1 (en) 1996-09-12 2013-06-04 Ibiden Co., Ltd. Circuit board for mounting electronic parts
JP2017130633A (en) * 2016-01-22 2017-07-27 豊田合成株式会社 Light-emitting device
JP2018032742A (en) * 2016-08-24 2018-03-01 トヨタ自動車株式会社 Semiconductor device
DE102019217679B4 (en) 2018-11-19 2023-11-02 Skyworks Solutions, Inc. ELECTRONIC DEVICE HOUSING AND HIGH FREQUENCY FILTER WITH HEAVY DUTY SOLDER TERMINALS

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