JPS61176817U - - Google Patents

Info

Publication number
JPS61176817U
JPS61176817U JP5996485U JP5996485U JPS61176817U JP S61176817 U JPS61176817 U JP S61176817U JP 5996485 U JP5996485 U JP 5996485U JP 5996485 U JP5996485 U JP 5996485U JP S61176817 U JPS61176817 U JP S61176817U
Authority
JP
Japan
Prior art keywords
field effect
effect transistor
bipolar transistor
capacitor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5996485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5996485U priority Critical patent/JPS61176817U/ja
Publication of JPS61176817U publication Critical patent/JPS61176817U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の構成を示す回路図
、第2図は同実施例の作用を説明するためのタイ
ムチヤート、第3図は本考案の他の実施例の構成
を示す回路図、第4図は従来のゲート増幅回路の
構成を示す回路図、第5図はその作用を説明する
ためのタイムチヤートである。 1,6……MOS形電界効果トランジスタ、2
……バイポーラトランジスタ、3,5……抵抗、
4……コンデンサ。
FIG. 1 is a circuit diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the same embodiment, and FIG. 3 is a circuit diagram showing the configuration of another embodiment of the present invention. 4 is a circuit diagram showing the configuration of a conventional gate amplifier circuit, and FIG. 5 is a time chart for explaining its operation. 1, 6...MOS type field effect transistor, 2
...Bipolar transistor, 3,5...Resistor,
4... Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] MOS形電界効果トランジスタと、この電界効
果トランジスタのソースにベースが接続されたバ
イポーラトランジスタと、抵抗およびコンデンサ
が直列接続され、その一端が前記バイポーラトラ
ンジスタのコレクタに、その他端が前記バイポー
ラトランジスタのエミツタにそれぞれ接続され、
且つ、前記抵抗およびコンデンサの相互接合点が
前記電界効果トランジスタのドレインに接続され
たスナバ回路とを具備し、前記コンデンサの放電
々流を、前記電界効果トランジスタを介して、前
記バイポーラトランジスタのベースに供給するこ
とを特徴とするゲート増幅回路。
A MOS type field effect transistor, a bipolar transistor whose base is connected to the source of the field effect transistor, a resistor and a capacitor are connected in series, one end of which is connected to the collector of the bipolar transistor, and the other end is connected to the emitter of the bipolar transistor. each connected,
and a snubber circuit in which a mutual junction of the resistor and the capacitor is connected to the drain of the field effect transistor, and the snubber circuit directs the discharge current of the capacitor to the base of the bipolar transistor through the field effect transistor. A gate amplifier circuit characterized by supplying.
JP5996485U 1985-04-22 1985-04-22 Pending JPS61176817U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5996485U JPS61176817U (en) 1985-04-22 1985-04-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5996485U JPS61176817U (en) 1985-04-22 1985-04-22

Publications (1)

Publication Number Publication Date
JPS61176817U true JPS61176817U (en) 1986-11-05

Family

ID=30586875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5996485U Pending JPS61176817U (en) 1985-04-22 1985-04-22

Country Status (1)

Country Link
JP (1) JPS61176817U (en)

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