JPS61176222A - Error detection method for serial data transfer - Google Patents

Abstract

PURPOSE:To maintain the reliability of the transfer data by sampling the data on each bit transferred at >=2 points in the bit length and comparing these sample values with each other. CONSTITUTION:A bit counting circuit 16 transmits a start bit signal BT or a stop bit signal BP to a start/stop bit check circuit 11 when the data on the start bit bt or the stop bit bp is received. Then the circuit 11 checks whether the sample value SM is coincident with the prescribed value or not in case the coincidence is obtained through a data sample comparator 10 between the sample values SM1 and SM2 of 2 times of the bit bt or bp. When no coincidence is obtained, a transfer error is decided. Then a discordance MM2 is transmitted to an RR interruption control circuit 13 and the reception enable signal RR is inverted into H.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for detecting transfer errors when performing norial data transfer in a relatively small-scale system.

[Prior art and its problems] In norial data transfer, in which binary data is sequentially transferred bit by bit, noise is added to the transferred data. Even during long periods of time (transmission time of 1 bit of data), it does not maintain a constant value (voltage) corresponding to "pi" or "φ°", but constantly fluctuates.

Therefore, on the receiving side, the value of each received bit of data is measured at a certain point in the bit length, and the measured value is compared with a predetermined threshold to determine whether it is "pi" or "φ°". I have to. Note that in this specification, "sampling" refers to measuring the value of data at a certain point and determining whether it is 1" or "φ" by comparing the measured value with a threshold value.

By the way, if large noise occurs during Norial data transfer, it may be due to an error in the data sample on the receiving side.
In other words, since there is a possibility that a transfer error may occur, it is necessary to check the transfer error.

R9232C is well-known as a serial data transfer protocol that takes this point into consideration, but controlling transfer using this protocol requires complex hardware and software processing, so it is relatively difficult to use with a word processor, etc. Not suitable for data transfer within a small system.

On the other hand, in serial data transfer using asynchronous communication method,
It is common practice to add a parity bit for transfer error detection to the data of each block (having a fixed number of bits) to be transferred, but in this case, the parity bit is unrelated to the original data. There is a problem in that the transfer time is long because of the large amount of data being transferred. Moreover,
Since it is necessary to provide a parity generation circuit on the transmitting side and a parity check circuit on the receiving side, the logic circuits thereof become complicated.

[Rounding Means to Solve the Problems] The present invention proposes a new transfer error detection method that can solve the above problems.

In the present invention, the data of each block is serially transferred, the data of each transferred bit is sampled at two or more points in the bit length, and the sample value (
φ′′ or °ko”).
(Previously, it was counted as one point.)

[Effects of the Invention] In the method of the present invention, the data of each transferred bit is sampled multiple times during the bit length, so if there is a mismatch in sample values, it is possible to detect a transfer error, and the transfer Data reliability can be maintained.

Furthermore, in the method of the present invention, there is no need to add extra bits such as parity bits for error detection.
Data transfer time is no longer prolonged due to error detection.

Furthermore, in order to implement the method of the present invention, it is sufficient to provide a relatively simple error detection logic circuit only on the receiving side, so the configuration of the logic circuit can be simplified.

can do.

[Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In the word processor shown in FIG. 2, binary data (key code signal) generated by the keyboard device l in response to key operations is sent to the host interface 2 in blocks.
After being checked for transfer errors at the post interface 2, it is subjected to serial/parallel conversion (S/I) conversion and input to the host combicoater 3.

” Between the two-legged keyboard device l and the host interface 2, the keyboard devices 1 to 71;
When the data line 4 that transfers serial data to the keyboard device 1 and the host interface 2 are capable of receiving data, the keyboard device 1
A reception ready status line 5 is provided for transmitting a reception ready signal RR.

On the other hand, post interface 2 and post computer 3
In between, there is a signal line 6 for transmitting an interrupt signal INT from the post interface 2 to the post computer 3;
A signal line 7 transmits a read signal i0R indicating that parallel data can be read from the host combicoter 3 to the post interface 2 in response to an interrupt signal INT; A data line (not shown) for transmitting and inputting parallel data is interposed from the host computer 2 to the host computer 3. Note that the host interface 3 is usually built into the host computer 2.

As shown in FIG. 3, data transferred from the keyboard device 1 to the post interface 2 is
−Bit start bit bt (−“φ” fixed)
, 8 data bits hφ to b7, and 1 stop bit bp (fixed at -“bit), making up a total of 10 bits, and the serial data is serially transferred block by block. At that time, if each bit is "φ", the binary coded BS sent from the keyboard device 1 to the host interface 2 maintains the L level during the bit length of the bit, and each bit becomes "Io". If so, the binary code BS is within the bit length of that bit.
maintain the level. For example, the bit length of each bit is 10
4. It is set to Iμs (according to 9600 BPS).

Note that when data is not transferred, the binary number B
S is always at I] level.

The above-mentioned receivable signal 1 1 1 is 1 level when it is in the receiving state, and the signal is 1 level when it is in the receiving state.
Start of the data being transferred from this tilt
is output, the start hit BS is inverted and RRl. +Inversion 1 becomes I7 level, and post-interface 2) Full data reception starts 3. From Gypo-1/Device 1,
Subsequently, the data bits l)φ~b are output in sequence.
These data bits bφ to b7(') are sequentially S/P converted after being received by the post interface 2.Furthermore, when the reception of the stop hit l-bp is completed, the interrupt signal IN'r' changes from 11 to l, Then, post-interface 2 informs host 1-bin 3 that the S/P-converted data will be sent manually.

Once the host Combi Coater 3 is able to accept data,
The read signal i 0rj is inverted from 11 to 1, and data is input from the post interface 2 to the host=1 amplifier 3. When the data input to the host combination coater 3 is completed, the signal qiorj is inverted to LI again,
Along with this, the interrupt signal INT and the reception enable signal RR are also inverted to H, and the host interface 2 ("Gibo-
1. Ready to receive the next block of data from device 1.

Here, if we organize each signal, the receivable signal RR
is at the I7 level from the start of the output of the data of block (1) from the Gyport device 1 until the input to the post-combi coater 3 is completed.

Also, the interrupt signal TNT is input only during an interrupt from the post interface 2 to the host combination coater 3.

The read signal i0R becomes level 17 only while the post-combi coater 3 is reading data from the host interface 2.

Next, the circuit configuration of the post interface 2 will be explained.

As shown in FIG. 4, the post interface 2 detects the start of serial data transfer by detecting the star/bit detection circuit 8, which detects each transferred bit b[, A data sample comparison circuit IO samples the data of hφ~b7, bp at two points in the bit length and compares the two sample values, and determines whether the start bit bt is °゛φ'' or not. and S) Start/stop bit check circuit II that checks whether or not l-1+p is bit, and data of each data hit bφ to b7 received by the data sample comparison circuit IO are sequentially S/P S/P conversion circuit +2 (shift resistor) to convert, reception enable signal RR and interrupt signal IN
The post interface 2 includes a timing generation circuit 14 that supplies timing pulses to each circuit at a predetermined timing. An oscillation circuit 15 that supplies clock pulses to the timing generation circuit 14 and the start bit detection circuit 8, and a bit count circuit 16 that counts how many hits are being received are provided (J
It is being

When the star I/hit detection circuit 8 detects the start bit bt by inverting the binary code BS from H to [7, it sends a reception start signal RT to the RR interrupt control circuit 3 and sets the reception ready signal RR to H. to I7.

In addition, the start bit detection circuit 8 detects star), filler +-
Simultaneously with the detection of bt, a count start signal CT is sent to the timing generation circuit 14, and accordingly, the timing generation circuit +4i:J: starts timing counting based on the clock pulse from the oscillation circuit 15.

''-The timing generation circuit 14 generates the first sample pulse SMI''l to the data sample comparison circuit 10 after 3271 seconds have elapsed from the start of data transmission of each bit.
(see Figure 1), the data sample comparison circuit 10
At the same time as receiving this sample pulse SMP1, samples the first data in each bit (J) and stores the sample value SMI ('"φ" or "l"). When 64 μs has elapsed from the start, the second sample pulse SMP2 is transmitted, and the data sample comparison circuit 10 samples the second data for each bit based on the sample pulse SMP2, and stores the sample value SM2. .

Furthermore, the timing generation circuit 14 transmits the first comparison pulse CMI to the data sample comparison circuit 10 at the time when 64.5/lS has elapsed from the start of each pip, and the data sample comparison circuit 10 receives this comparison pulse. At the same time as the pulse CMI is received, the first and second sample values SMI and SM2 of that bit are compared. Sample value SMI, SM2
If they match, it is assumed that a correct transfer has been performed for that bit, and a match signal M is sent to the start/stop bit check circuit 11, and the matched sample value SM is transmitted as a start/stop bit. The signal is transferred to the DEC circuit 11 and the S/P conversion circuit 12.

- On the other hand, if the sample values SMI and SM2 do not match,
The transfer of that bit is deemed to be an error, and a mismatch signal MM1 is sent to the RR interrupt control circuit 13.
Based on the mismatch signal MMI, the R interrupt control circuit 13 inverts the receivable signals R and R to 1 (as shown by the two-dot chain line in FIG. 1), and notifies the keyboard device 1 of a transfer error. , control after an error is detected during transfer will be described later.

” The two-leg timing generation circuit 14 transmits the second comparison pulse CM2 to the start/stop bit check circuit 11 when 64.75 μs has elapsed from the start of each bit, and furthermore, when 64.75 μs has elapsed from the start of each bit, When 257zs has elapsed, a shift pulse SF is transmitted to the S/P conversion circuit 12. By this shift pulse SF, sample values SM of data of each data bit bφ to b7 supplied to the S/P conversion circuit 12 are sequentially S/P converted.

Further, the timing generation circuit 14 transmits a bit end pulse BR to the bit count circuit 16 at the end of each bit, and the bit count circuit 16 increments the number of bits based on this pulse BR.

The bit count circuit 16 transmits a start bit signal BT or a stop bit signal BP to the start/stop bit check circuit 11 when receiving data of a start bit (bt) or a stop bit (bp). As a result, if the two sample values SMI and SM2 of the start bit bt or stop bit 1l-)bp in the data sample comparison circuit IO match, the start/stop bit check circuit 11 further determines that the sample value SM is period value (M is ′φ”
, bp is "l"). If the sample value SM at the start bit bt or stop bit bp does not match the expected value, it is regarded as a transfer error, a mismatch signal MM2 is sent to the RR interrupt control circuit 13, and the receivable signal Rr (is inverted to H). be done.

The bit count circuit 16 sends a count end signal CP to the timing generation circuit 14 to stop timing counting when the reception of the data of the I block is completed, and transmits a transfer end signal TE to the RR interrupt control circuit 13. Send. r(R) The interrupt control circuit 13 inverts the interrupt signal INT to {circle around (2)} at the same time as receiving the transfer end signal TE.Subsequently, the read signal i
When the OR is inverted to L, the 8-bit parallel data converted by the S/P conversion circuit 12 is input to the host computer 3. When the input of the 8-bit parallel data to the host computer 3 is completed, the read signal i0R is inverted to I again as described above, and accordingly, the receivable signal RR and the interrupt signal INT are also inverted to 1. The post interface 2 is returned to its initial state and can receive the next block of data.

At this point, an error is detected during the transfer, and the
The subsequent control when the receivable signal RR is inverted from L to H before the next transfer is completed will be explained.

That is, in the above case, even if the receivable signal RR is inverted to H, data transfer continues until the data transfer of that block is completed. However, even if the transfer of the data of the block is completed, the interrupt signal jNT remains at H, and the data of the block is not input to the host computer 3. In that case, at the same time as the transfer ends, host interface 2 is returned to its initial state,
Immediately, retransmission processing of the data of the block is started.

Next, based on the flowchart of FIG. 5, the processing procedure on the keyboard device I side when transferring Norial data from the keyport device I to the host interface station 2 will be explained once again. That is, (1) When 1 block of data without transfer is set in step SO, it is determined in Sl whether the receivable signal RR is IT or not, and if RR is 17, Rrt should be IT. and wait.

(II) If RR is H, or if RR becomes II, the data of the start bit bt is output in S2, and the data of the start bit bt is held for one hit in S3 without continuing to output the data of the start bit bt.

(iii) When the start hit bt output is finished,
Proceeding to S4, data bits 11φ to lI7 are sequentially output, and in S5, data bits bφ to b7 are held for 1 bit while continuing to be output. Continuing, in S6, it is determined whether n=7, that is, whether the output of the last data bit 1-b7 has been completed, and if the output of the last data bit b7 has not been completed, the process returns to S4. Output the next data bit.

(iv) When the output of the last data bit b7 is finished in S6, the process proceeds to S7 to output the stop bit bp, and then in S8 the output of the stop bit bp is not continued and is held for one hit.

(■) When the output of the stop bit bp is completed, the process advances to S9, and it is determined whether the RR is ■. If RR is H, as described above, it is assumed that an error has occurred during the transfer of the block, and the process returns to Sl to start retransmission processing of the data of the block.

(vi) If RR is L, the data is considered to have been transferred correctly, and it is determined whether there is any remaining data to be transferred by proceeding to SIO, and if there is no data remaining to be transferred, , transmission is stopped. On the other hand, if there remains data to be transferred, the process returns to SO, sets the data for the next block, and starts transfer.

As explained above, in this embodiment, data to be serially transferred is sampled at two points in each bit length on the receiving side,
If there is a discrepancy in the sample values, it is treated as a transfer error, so it is possible to maintain the reliability of the transferred data with a relatively simple protocol, and an extra bit is added for error detection. Since there is no need to do this, there is no delay in transfer time.

Further, since it is sufficient to provide a relatively simple logic circuit only in the host interface 2 on the receiving side for error detection, the circuit configuration can be simplified and the efficiency of the interface by the host interface 2 can be improved.

Furthermore, when an error is detected during transfer, the occurrence of the error is immediately notified to the keyboard device 1 by inverting RR to 1], and retransmission processing is immediately started when the occurrence of the error is notified. Instead, the retransmission process is started after the transfer of that block is completed, so that it is possible to reliably prevent a transfer failure due to the occurrence of an error.

Furthermore, a keyboard device 1 and a host interface 2
Since it is only necessary to provide two signal lines, the data line 4 and the reception ready status line 5, for serial data transfer between ``You can go back twice.''

In addition, in the embodiment 1, the case where serial data is transferred between the keyboard device I and the host computer 3 via the host interface 2 has been described, but -1-
The error detection method described above can be applied to serial data transfer between various devices such as displays and printers in word processors and the host computer 3, as well as serial data transfer within various other relatively small-scale systems. Needless to say.

Furthermore, the number of bits and bit length of data constituting one block are not limited to the above values, and it is also possible to sample and compare data at 3 or more points of each bit length. It is.

[Brief explanation of drawings]

FIG. 1 is a time chart showing the generation timing of various pulses within a bit length in a serial data transfer system according to an embodiment of the present invention, and FIG. 2 is a serial data transfer system according to an embodiment of the invention. Figure 3 is a block diagram showing the main parts of the data transfer system. The circuit configuration diagram of the host interface shown in the figure, and Fig. 5 is a flowchart showing the processing procedure in the keyboard device shown in Fig. 2. 2...Host interface (receiving side). Patent applicant: Sharp Corporation. person
Patent attorney: ``Two idiots, master craftsmen''``Ae'' Su^O

Claims (1)

[Claims] (1) In serial data transfer that sequentially transfers blocked binary data bit by bit, the receiving side samples each bit of data at two or more points within the bit length, compares the sample values, and selects one of the An error detection method in serial data transfer, characterized in that if there is a mismatch of sample values in bits of the block, the transferred data of that block is regarded as an error.