KR100555644B1 - transmitting/receiving method of bit stream - Google Patents

Abstract

A bit stream transmission / reception method is disclosed. In the bit stream receiving method according to the present invention, when one bit stream is input to a general-purpose input terminal, determining whether the first bit input is a start bit, and if the start bit is a result, a bit between the host device and the slave device. Enabling and adjusting the interrupt generating means to generate an interrupt signal at each transmission time, and detecting a data bit that is a transmission target bit of the bit stream based on each interrupt signal of the adjusted interrupt generating means; . According to the present invention, since the UART does not need to be provided, the production cost of the slave device can be reduced.

Bit stream, host device, slave device

Description

Bitstream transmission / receiving method of bit stream

1 is a block diagram of a host device and a slave device to which a bit stream transmission / reception method according to the present invention is applied;

2 is an internal block diagram of the microcomputer of FIG. 1;

3 is a flowchart illustrating a method of receiving a bit stream according to the present invention;

4 is a timing diagram for explaining a detection point of a bit stream according to the reception method of FIG. 3.

5 is a flowchart illustrating a bit stream transmission method according to the present invention;

FIG. 6 is a timing diagram illustrating a timing of transmitting a bit stream according to the transmitting method of FIG. 5.

* Description of the symbols for the main parts of the drawings *

110: microcomputer 111: input terminal

112: Register 113: Timer / Counter

114: interrupt signal generator 115: output terminal

116: control circuit

The present invention relates to a bit stream transmission / reception method, and more particularly, a host device and a universal input / output terminal equipped with a universal asynchronous receiver and transmitter (UART, hereinafter referred to as “UART”). The present invention relates to a method for transmitting / receiving a bit stream between a general purpose input / output terminal) and a slave device having interrupt generating means.

In general, host devices such as computers and slave devices such as peripherals each have a UART. In general, UART generates and removes start bit, stop bit, and parity bit according to UART protocol. Also, when transmitting a bit stream, the UART converts byte parallel data into a serial bit stream through parallel / serial conversion. On the other hand, when receiving a serial bit stream, the UART converts the serial bit stream received through the channel into serial parallel data and converts it into byte parallel data, and transmits it to the CPU.

Conventionally, the UART is provided in both the host device and the slave device. Therefore, considering the current trend of mass production of products, there is a problem that the UART in both devices increases the production cost. In particular, when a lot of functions are required in a product such as nowadays, when one or more slave devices are provided, the provision of a UART for each device will further increase the production cost. In addition, there is a problem in that a printed circuit board (PCB) is complicated when a UART is provided for each slave device. Also, since a UART protocol for an interface is predetermined in hardware, there is a complexity that a hardware change is required for the protocol change.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a bit received from a UART of a host device using an interrupt signal generated at predetermined time intervals without a separate UART in a slave device. The present invention provides a bit stream transmitting / receiving method capable of detecting each bit in a stream and transmitting a predetermined bit stream using an interrupt signal generated at predetermined time intervals.

In order to achieve the above technical problem, the present invention provides a slave device having a general purpose input terminal and an interrupt generating means from a host device equipped with a universal asynchronous receiver and a transmitter. In the method for transmitting a bit stream, if one bit stream is input to the general-purpose input terminal, determining whether the input first bit is a start bit, if the determination result is the start bit, the host device and the slave Enabling and adjusting the interrupt generating means to generate an interrupt signal at each transmission time per bit between devices and based on each interrupt signal of the adjusted interrupt generating means, a data bit which is a transmission target bit of the bit stream. Detecting.

In the adjusting step, when the start bit is the start bit, calculating the transmission time per bit based on the data transmission rate from the host device to the slave device, and generating an interrupt signal for each calculated transmission time per bit. Enabling and adjusting said interrupt generating means to generate.

In the detecting step, the first interrupt signal is generated after the bit detection adjustment time based on the transmission time per bit has elapsed from the detection time of the start bit, and the bit detection adjustment time corresponds to 1.5 times the transmission time per bit. It is preferable that it is time to make.

Hereinafter, as a preferred embodiment of the present invention, a bit stream transmission / reception method will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a host device 200 and a slave device 100 to which a bit stream transmission / reception method according to the present invention is applied. According to the present invention, when the bit stream is transmitted / received through each channel between the host device 200 and the slave device 100, only the host device 200 is provided with a UART 220 to transmit / receive the bit stream. do. When transmitting predetermined data from the host device 200, the parallel data from the CPU 210 in the host device 200 is transferred to the UART 220, and the transferred parallel data is parallel / serial converted by the UART 220. Is transmitted to the slave device (100). The microcomputer 110 of the slave device 100 receives the transmitted bit stream and detects each bit of the bit stream according to the data receiving method according to the present invention. In addition, when transmitting predetermined data to the host device 200, parallel data from the microcomputer 110 in the slave device 100 is transmitted to the host device 200 according to the bit stream transmission method according to the present invention. That is, according to the present invention, in the case of the slave device 100, the UART 220 is not provided, and the microcomputer 110 in the slave device 100 is programmed to perform the transmission method according to the present invention and replaces the UART 220. .

2 is a block diagram of a microcomputer 110 for performing a data bit transmission / reception method according to the present invention. The microcomputer 110 according to the present invention includes an input terminal 111, a register 112, a timer / counter 113, an interrupt signal generator 114, an output terminal 115, and a control circuit 116.

The input terminal 111 receives a bit stream transmitted from the host device 200. It is preferable to apply a general purpose pin as the input terminal 111. The general purpose pin refers to a pin that is not manufactured for a specific use in the manufacturing process of the microcomputer 110. Therefore, it can be used for a predetermined purpose through programming by a user.

The register 112 is a storage means and stores data transmission rate information, which is a transmission rate of a bit stream between the host apparatus 200 and the slave apparatus 100. Typically, the unit of data rate is bps (bit per second). The register 112 stores the initially set data bit value information. Here, the data bits are bits to be transmitted by the CPU 210 or the microcomputer 110, and the data bit information means the number of bits of the data bits transmitted through each bit stream.

The timer / counter 113 generates a clock of a predetermined period through control by the control circuit 116. In addition, the counting operation is performed by increasing the counting value by 1 whenever each bit of the bit stream is received and detected through the control by the control circuit 116 or when each bit in the bit stream is transmitted. In addition, the timer / counter 113 transmits a control signal to the interrupt signal generator 114 at predetermined time intervals under the control of the control circuit 116. In the timer / counter 113, the time when 1.5 times the transmission time per bit has elapsed from the time when the start bit is detected becomes the transmission time of the first control signal, and when the transmission time for each bit elapses thereafter. It may be preferable to generate each control signal for each transmission and transmit the control signal to the interrupt signal generator 114. The interrupt signal generator 114 generates an interrupt signal based on the control signal and transmits the interrupt signal to the control circuit 116.

The interrupt signal generator 114 generates an interrupt signal according to the control signal of the timer / counter 113. The generated interrupt signal is transmitted to the control circuit 116, and the control circuit 116 detects each bit in the bit stream received by the microcomputer 110 in accordance with the interrupt signal. In the case of data transmission, each bit is transmitted for each generated interrupt signal.

The output terminal 115 is used to transmit a bit stream from the slave device 100 to the host device 200, and it is preferable to apply a general purpose pin.

When a predetermined bit stream is input to the input terminal 111, the control circuit 116 determines whether the first bit of the input bit stream is a start bit. The control circuit 116 controls the timer / counter 113 to be enabled when the determination result is the start bit. In addition, when the determination result is the start bit, the transmission time per bit is calculated based on the data transmission rate information stored in the register 112.

The control circuit 116 also controls the timer / counter 113 to transmit the control signal at every transmission time per bit to the interrupt signal generator 114. As mentioned above, in the case of data reception, it is preferable to control the transmission time of the first control signal so that the time corresponding to 1.5 times the transmission time per bit has elapsed from the time when the start bit is input.

In the case of data reception, the control circuit 116 determines whether the count value of the timer / counter 113 increased according to the detection of each bit in the bit stream and the data bit value previously stored in the register 112 are the same. To judge. As a result of the determination, if not the same, the control circuit 116 controls the timer / counter 113 to increase the counting value by one and to detect the next bit. If the determination result is the same, the control circuit 116 determines whether the next bit of the data bit is the stop bit. As a result of the determination, in the case of the stop bit, the control circuit 116 controls the timer / counter 113 to be disabled. As a result of the determination, if it is not the stop bit, the control circuit 116 transmits an error message to the host device 200 and requests to retransmit the same bit stream.

Also, in the case of data transmission, the control circuit 116 checks whether the counting value of the timer / counter 113 increased in accordance with the transmission of each bit and the data bit value previously stored in the register 112 plus 2 are the same. If it is not the same, and if it is not the same control to transmit the next bit, and if the same, the timer / counter 113 controls to be disabled.

3 is a flowchart illustrating a data receiving method according to the present invention. When the bit stream is received from the host device 200 (S300), the control circuit 116 determines whether the first bit of the bit stream is the start bit (S310). As a result of the determination, in the case of the start bit, the control circuit 116 enables the timer / counter 113 (S320). The control circuit 116 then calculates the transfer time per bit based on the data transfer rate stored in the register 112. Then, the timer / counter 113 delays the time corresponding to 1.5 times the transmission time per bit from the time of detecting the start bit (S330), and then transmits the first control signal to the interrupt signal generator 114. Thereafter, the control signal is transmitted at every transmission time therefrom. An interrupt signal is generated from the interrupt signal generator 114 based on the transmitted control signal and transmitted to the control circuit 116, and the control circuit 116 detects each bit of the bit stream for each transmitted interrupt signal (S340). . If one bit is detected, it is determined whether the pre-stored counting value and the data bit value are the same (S350). If the result is not equal, the counting value is increased by 1 and the next bit is detected. This process is repeated until the counting value and the data bit value are the same. As a result of determination, the control circuit 116 determines whether the next bit of the last bit of the data bit is the stop bit (S370). If it is determined that the bit is not a stop bit, the control circuit 116 transmits an error message and a data retransmission request signal to the host device 200 (S390). As a result of the determination, in the case of the stop bit, the control circuit 116 disables the timer / counter 113 and waits for reception of the next bit stream (S380).

  4 is a timing diagram illustrating a detection time of a bit stream according to the receiving method of FIG. 3. In this figure, it is assumed that a bit stream is composed of a start bit (ST_B) of 1 bit, a data bit (DA_B) of 8 bits, and a stop bit (SP_B) of 1 bit. Typically, the start bit has a value of '0' and the stop bit has a value of '1'. In addition, R1 to R8 indicate when each bit of the bit stream is detected through the interrupt signal generated from the interrupt signal generator 114.

As an example, assuming a data transmission rate of 9600bps (bit per second) between the host device 200 and the slave device 110, a transmission rate of 1 bit corresponds to approximately 104 μsec. Therefore, when applying the reception method according to the present invention, the control circuit 116 detects the first bit approximately 156μsec after detecting the start bit. In this case, 156 μsec means a time corresponding to 1.5 times 104 μsec, the transmission rate per bit, from the detection of the start bit. This is because it is preferable to perform the detection operation at the center of each bit.

The second bit is detected 104μsec after the first bit is detected. This operation is repeated until the data bit value is equal to the counting value.

5 is a flowchart illustrating a data transmission method according to the present invention.

First, the control circuit 116 is processed by the microcomputer 110 to prepare the data bit to be transmitted to the host device (200) (S400), and enables the timer / counter 113 (S410). The control circuit 116 then calculates the transfer time per bit based on the data transfer rate stored in the register 112. Under the control of the control circuit 116, the timer / counter 113 transmits a control signal to the interrupt signal generator 114 at every transmission time per bit, and the interrupt signal generator 114 controls the control circuit 116 based on this. Send an interrupt signal. The control circuit 116 transmits each bit of the data bit prepared for each interrupt signal to the host device 200 through the transmission channel. However, the start bit is transmitted first, the data bit is transmitted next, and the stop bit is transmitted last. On the other hand, each time the bit is transmitted, the timer / counter 113 increments the counting value by 1, and generates a control signal for generating the interrupt signal until the counting value becomes equal to (data bit + 2). In step S430, S450 is transmitted. If the counting value is equal to (data bit + 2), the control circuit 116 stops further bit transmission and disables the timer / counter 113 (S440).

FIG. 6 is a timing diagram illustrating a timing of transmitting a bit stream according to the transmitting method of FIG. 5. However, the same description as in FIG. 4 will be omitted to avoid duplication.

In this figure, data bits are assumed to be 8 bits, and T1 to T10 indicate the time points at which each bit of the bit stream is transmitted through the interrupt signal generated from the interrupt signal generator 114.

As an example, it is assumed that the transmission rate of the bit stream is 9600 bps (bit per second) between the host device 200 and the slave device 110, and 104 μsec, which is a transmission rate per bit, is calculated. According to the transmission method according to the present invention, the control circuit 116 transmits a start bit, a data bit and a stop bit for each interrupt signal at predetermined intervals. Here, the predetermined interval should be 104 μsec, which is the transmission rate per bit.

In this detailed description, the microcomputer 110 includes the register 112, the timer / counter 113, and the interrupt signal generator 114 separately, but according to the exemplary embodiment, the register 112 and the timer / counter ( 113 and the interrupt signal generator 114 may be implemented as one device.

As described above, according to the bit stream transmission / reception method according to the present invention, since the slave device does not need to have a UART, the production cost of the slave device can be reduced. In addition, since the UART is implemented in software, the number of data bits to be transmitted can be easily changed by user setting, and the UART protocol can be easily changed.

In the above, certain preferred embodiments of the present invention have been illustrated and described. However, the present invention is not limited to the above-described embodiments, and any person having ordinary skill in the art to which the present invention pertains without departing from the spirit and spirit of the present invention claimed in the claims may make various modifications and variations. Implementation will be possible.

Claims (5)

A method of transmitting a bit stream from a host device equipped with a universal asynchronous receiver and a transmitter to a slave device provided with a general purpose input terminal and interrupt generating means, When a bit stream is input to the general-purpose input terminal, determining whether the first bit input is a start bit; Enabling and adjusting the interrupt generating means to generate an interrupt signal at every transmission time between the host device and the slave device when it is the start bit; And And detecting a data bit that is a transmission target bit of the bit stream based on each adjusted interrupt signal of the interrupt generating means. The method of claim 1, The adjusting step, Calculating a transmission time per bit based on a data transmission rate from the host device to the slave device when the determination result is the start bit; And Enabling and adjusting the interrupt generating means to generate an interrupt signal at each calculated transmission time per bit. The method of claim 1, In the detecting step, the first interrupt signal is generated after the bit detection adjustment time based on the transmission time per bit has elapsed from the detection time of the start bit. The method of claim 3, And the bit detection adjustment time is 1.5 times the transmission time per bit. Claims [1] A method for transmitting a bit stream from a slave device having a general purpose output terminal and an interrupt generating means to a host device having a universal asynchronous receiver and transmitter. Calculating a transmission time per bit based on a data transmission rate from the slave device to a host device; Enabling and adjusting the interrupt generating means to generate an interrupt signal at each calculated transmission time per bit; And And transmitting each bit of a bit stream to be transmitted through the general-purpose output terminal for each interrupt signal of the adjusted interrupt generating means.

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