JPS61174783A - Manufacture of superconducting circuit device - Google Patents

Abstract

PURPOSE:To simplify processes, by burying the surrounding part of the first superconducting wiring layer pattern by an insulating layer, making the first superconducting layer to be an insulating film, and blocking a tunnel current between the first superconducting layer and the second superconducting layer. CONSTITUTION:A lower superconducting niobium film, which is patterned and surrounded by SiO2 3, is formed in contact with an Si substrate 1. RF plasma oxidation is performed, and an interlayer insulating film 4 comprising a niobium oxide film having a specified thickness is formed. Thereafter, an upper super conducting niobium film 5 is provided. As a result, the upper superconducting layer is formed through the interlayer insulating film, which is formed in the embedded lower superconducting layer by self-alignment. Thus a multilayer structure is implemented. In this method, the processes can be simplified, estimat ing allowance is not required and the device can be made compact.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a superconducting circuit device comprising at least a superconductor, an insulator, and a tunnel barrier. More specifically, the present invention relates to a method for manufacturing a superconducting circuit device that includes a step of forming an interlayer insulating film after the periphery of the lower superconducting layer is embedded in an insulating layer.

(Prior art and its problems) A structure in which a plurality of mutually electrically insulated superconducting layers are stacked on a substrate is used in superconducting circuit devices, such as a Josephson junction device or a Josephson junction integrated circuit. It will be done. For example, a flattened structure is shown in Lanyoshi Kosaka's 45th Japan Society of Applied Physics Academic Conference 12P-Y-7. FIG. 3 shows a conventional example of a two-layer structure of superconducting layers electrically insulated from each other. Lower superconducting layer 18 or buried insulating layer 1
After depositing the glabella insulating layer 20 in contact with 9, the vaginal interlayer insulating layer 2
An upper superconducting layer 21 was formed in contact with the upper layer 0. By the way, it is necessary to reduce the thickness of the interlayer insulating layer 20 in order to reduce the inductance of the upper superconducting layer 21 when a substrate IK ground plane is provided and to facilitate the formation of contact holes.

In order to satisfy this requirement with the structure shown in FIG. 3, as shown in FIG. It is conceivable to remove the glabellar insulating layer in the area where the lower superconducting layer 23 does not intersect. However, this conventional manufacturing method requires a step of patterning the glabella insulating layer 25 in correspondence with the pattern of the lower superconducting layer 23.

This complicates the molding process and requires a margin for alignment, which hinders miniaturization of the device.

(Object of the Invention) An object of the present invention is to provide a method for manufacturing a superconducting circuit device that eliminates the above-mentioned conventional drawbacks and can realize patterning of an interlayer insulating layer by self-line.

(Structure of the Invention) According to the present invention, a superconducting circuit device having a first superconducting wiring layer and a second superconducting wiring layer located on the first superconducting wiring layer with an insulating layer interposed therebetween is manufactured. After filling the periphery of the patterned first superconducting wiring layer with an insulating layer,
The problems of the insulating layer technique have been solved by making the surface of the first superconducting wiring layer thick enough to prevent tunneling current flowing between the first and second superconducting wiring layers.

FIG. 1 is a sectional view showing the manufacturing process of a superconducting circuit device according to the present invention. A patterned lower superconducting layer 2 surrounded by a buried insulating layer 3 is provided in contact with a substrate 1 (al). Next, the surface of the lower superconducting layer 2 is made into an insulating layer to provide interlayer insulation. Layer 4 As a result, a multilayer structure can be realized in which the upper superconducting layer is formed on the lower superconducting layer via the glabella insulating layer formed by self-aligning the buried lower superconducting layer.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a manufacturing process diagram of a Josephson junction device showing an embodiment of the present invention. The manufacturing process of the Josephson junction element is already well known, and for example, the process up to the flattening of the counter electrode shown in FIG. 2(a) can be easily realized. For example, a silicon wafer with an oxidized surface is used as the substrate 6, and a ground plane 7 made of, for example, niobium with a thickness of 300 nm is provided on the substrate 6. Next, a base electrode 9 using, for example, a niobium sputtered film and a base electrode 9 made of, for example, a niobium sputtered film are formed. A tunnel barrier 10 obtained by oxidizing the electrode surface and a counter electrode 1 made of a niobium sputtered film
1 is formed all at once in the same apparatus, and then patterning is performed using, for example, a dry etching method so as to leave the base electrode 9, tunnel barrier 10, and counter electrode 11 in required areas. Generally, the Josephson electrode density is 10'~10''A/
d, the thickness of the tunnel barrier 10 is approximately I
It ranges from OA to 20A.

After that, for example, SIO is deposited up to the same distance from the substrate 6 as the upper surface of the counter electrode 11, and the region on the insulating layer 8 where the base electrode q is not provided is buried with the insulating layer (1) 12.
The surface of the device up to this step is flattened.

(FIG. 2(a)) Next, a counter electrode wiring layer 13 is formed of, for example, a niobium sputtered film in contact with the surface of the device, and is patterned by, for example, a dry etching method so as to leave a necessary area. The insulating layer (2) 1 is filled with, for example, a 810 vapor deposited film in the area where the etching has been removed by etching.
4, and a counter electrode wiring layer 13 and a buried insulating layer r2.
) 14 so that their top surfaces are in the same plane.

(FIG. 2(b)) The insulating layer 15 is formed on the surface of the electrode wiring layer 13. (Figure 2 (C)) In this case, the Josephson current density flowing through the insulating layer 15 is 10-'
If the density of the Josephson electrode flowing through the tunnel barrier 10 is designed to be approximately 10' A/d to 10'' A/d, the leakage current due to the insulating layer 15 can be ignored.

Note that these oxidation conditions are only an example, and an even higher quality insulating layer 15 can be obtained by optimizing the RF voltage, gas type, and gas pressure oxidation time.

Next, for example, a niobium sputtered film is deposited and patterned to form the control line 16. (FIG. 2(d)) Furthermore, if necessary, a protective film made of SiO, for example, may be provided, although not shown in the figure, after the control line 16 is formed.

As a result of the above, in a structure in which a control line is formed via an insulating layer on a counter electrode wiring layer whose periphery is buried, the insulating layer is formed by a self-line. Although there may be many variations in the structure of the manufacturing process itself, the superconducting material, the insulating layer material, the manufacturing method thereof, the buttering method, etc. in the above embodiments, the present invention applies to any of the above. It can be used effectively.

(Effects of the Invention) According to the present invention, when an upper superconducting layer is provided via an insulating layer formed on a lower superconducting layer in which the periphery is embedded,
Since the insulating layer is formed on the lower superconducting layer by self-alignment, there is no need for a patterning process for the insulating layer, which simplifies the process, and also eliminates the need for alignment margins, making the device more compact. Make it possible K.

3 is a cross-sectional view of the structure of one of the conventional superconducting circuit devices, and FIG. 4 is the structure of another conventional superconducting circuit device. FIG.

In the figure, 1.6, 17.22 are the substrates, 2, 18°2
3 is the lower superconducting layer, 3.19.24 is the buried insulating layer,
4, 20, 25 are insulating layers between eyebrows, 5, 21, 26 are upper superconducting layers, 7 is a ground plane, 8.15 is an insulating layer, 9 is a base electrode, 10 is a tunnel barrier, 11 is a counter electrode, 12 is A buried insulating layer (1), 13 is an opposing one-frame wiring layer, 14 is a buried insulating layer (2), and 16 is a control line.

Industrial technology? 'i': l'f' full length Figure 1 (b) (C) Figure 2 Y to u Figure 3 E 4 Figure

Claims (1)

[Claims] In manufacturing a superconducting circuit device having a first superconducting wiring layer and a second superconducting wiring layer located on the first superconducting wiring layer with an insulating layer interposed therebetween, a patterned first superconducting wiring layer is formed. After filling the periphery of the conductive wiring layer with an insulating layer, the surface of the first superconducting wiring layer is made into an insulating layer to a thickness sufficient to block tunnel current flowing between the first and second superconducting wiring layers. A method for manufacturing a superconducting circuit device characterized by: