JPS61173521A - Multi-input exclusive or circuit - Google Patents

Multi-input exclusive or circuit

Info

Publication number
JPS61173521A
JPS61173521A JP1384685A JP1384685A JPS61173521A JP S61173521 A JPS61173521 A JP S61173521A JP 1384685 A JP1384685 A JP 1384685A JP 1384685 A JP1384685 A JP 1384685A JP S61173521 A JPS61173521 A JP S61173521A
Authority
JP
Japan
Prior art keywords
circuit
elements
exclusive
input exclusive
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1384685A
Other languages
Japanese (ja)
Inventor
Masayuki Yoshizawa
吉澤　正幸
Masuo Tsuji
辻　満寿夫
Kunio Katsuno
勝野　邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1384685A priority Critical patent/JPS61173521A/en
Publication of JPS61173521A publication Critical patent/JPS61173521A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Abstract

PURPOSE:To decrease the number of elements of a circuit itself and to reduce the stray capacity of a signal delay element by using one or plural two-input exclusive OR circuit composed of inverter circuits, a clocked gate circuit, and an analog switch circuit. CONSTITUTION:A two-input exclusive OR (NOR) circuit consists of inverter circuits 4 and 5 (204 and 205), a clocked gate circuit 6 (206), and an analog switch circuit 7 (207) and is equipped with input terminals 1 and 2 (101 and 102) and an output terminal 3 (203). In this case, 10 elements are used. This circuit is used to constitute a four-input exclusive OR circuit or eight-input exclusive OR circuit. The number of elements constituting the four-input exclusive OR circuit is 30 and the number of elements constituting the eight-input exclusive OR circuit is 70, so the number of elements of circuit configuration in this invention is less than before.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 不発明は、多入力イクスクルーシブオア（ロ）路の構成
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The invention relates to a method of constructing a multi-input exclusive OR (b) path.

〔従来技術〕[Prior art]

従来の多入力イクスクルーシブオア回路は、第７図、第
８図のような４入力イクスクルーシブオア回路４ン用い
て、多入力イクスクルーシブオア回路Ｙ？ＩＩＩ成して
いる。更には、２人カイクスクルーシブオア回路ン用い
て１１１或する場合においても、ｇｓｖ、ｇ６図のよう
な２入力イクスクルーシブオア（ロ）路ケ用いている。A conventional multi-input exclusive OR circuit uses a four-input exclusive OR circuit as shown in FIGS. 7 and 8 to form a multi-input exclusive OR circuit Y? III has been completed. Furthermore, even in the case where a two-person exclusive OR circuit is used, a two-input exclusive OR circuit as shown in the gsv and g6 diagrams is used.

〔開明が解決するための手段〕[Means for Kaimei to solve the problem]

しかし、前述の従来技術では、素子数が多いため、半導
体装置７太き（してしまうという欠点が、あられれてい
る。特に入力ゲート数の多い場合、特に顕著にあられれ
る。However, in the above-mentioned conventional technology, since the number of elements is large, the semiconductor device 7 becomes thick. This problem is particularly noticeable when the number of input gates is large.

また素子数が多いため、半導体装置の信号遅延が大ぎ（
なっている。この場合においても、入力ゲート数が多（
なるにつれて、信号遅延が顕著にあられれて（る。更に
は、従来技術の場合、半導体装置の信号ラインに多大の
）！！延要素としての浮遊容量がつくため、信号遅延量
ン大き（している。Also, because the number of elements is large, the signal delay of semiconductor devices is large (
It has become. Even in this case, the number of input gates is large (
As the technology progresses, signal delays become more noticeable (and, in the case of conventional technology, there is a significant amount of signal delay in the signal lines of semiconductor devices)! ! Since stray capacitance is added as a spreading element, the amount of signal delay is large.

本発明の目的は、かかる欠点ンな（すことにあり、回路
自体の素子数ン減らし、信号遅延賛素の浮遊容Ｉｌン減
らすことにある。An object of the present invention is to eliminate such drawbacks, and to reduce the number of elements in the circuit itself and the stray capacitance of signal delay elements.

〔問題点ン解決するための手段〕[Means for solving problems]

不発明の多入力イクスクルーシブオア回路の構成におい
て、インバータ回路とクロックドゲート回路とアナログ
スイッチ回路で構成された２大力イクスクル一シブオア
回路あるいは、２大力イクスクル一シブオア回路ＹｒＪ
数個用いてｍ成することン峙倣とする。In the configuration of an uninvented multi-input exclusive OR circuit, a two-power exclusive-OR circuit or a two-power exclusive-OR circuit YrJ is constructed of an inverter circuit, a clocked gate circuit, and an analog switch circuit.
It is assumed that several pieces are used to make a single copy.

〔作用〕[Effect]

本発明の上記の構成によれば、多入力イクスクルーンプ
オア回路は、入力ゲート数がふえるにつれて、多入力イ
クスクルーシブオア回路Ｙ＃４成する素子数の叔か従来
技術より本発明の回路構成のほうが、少なくて構成でき
る。構成する素子数が少ないと、半導体装置の信号遅延
Ｊｌｙ小さくすることができ、高速応答の半導体装置が
作成できる。According to the above configuration of the present invention, as the number of input gates increases, the multi-input exclusive OR circuit Y#4 has a smaller number of elements than the conventional circuit. It can be configured with fewer configurations. When the number of constituent elements is small, the signal delay Jly of the semiconductor device can be reduced, and a semiconductor device with high speed response can be created.

また素子数が少ないと、半導体装置のコストダウンにも
つながる。史には、本発明の回路構成め万が、従来技術
の回路構成よりも信号遅延の要因となる浮遊容量が少な
（てすむ。Furthermore, a small number of elements leads to a reduction in the cost of the semiconductor device. Historically, the circuit configuration of the present invention has less stray capacitance, which causes signal delay, than the circuit configuration of the prior art.

〔実施例〕〔Example〕

第１因は、本発明の回路構成で使用する２大力イクスク
ル一シブオア回路である。番号１．２が入力端子である
。この回路構成の場合、素子数は、１０素子である。第
２図に第１図の回路ン用いた４大力イクスクル一シブオ
ア回路ン示す。ｉ＠３図には、第１図の回路を用いた８
大力イクスクル一シブオア回路を示す。これら回路は、
本発明の４大力イクスクル一シブオア回路、８大力イク
スクル一シブオア回路の一実施例である。The first factor is the two-power single-or circuit used in the circuit configuration of the present invention. Numbers 1.2 are input terminals. In this circuit configuration, the number of elements is 10. FIG. 2 shows a four-power circuit using the circuit shown in FIG. 1. Figure i@3 shows 8 using the circuit in Figure 1.
Shows a powerful single-or circuit. These circuits are
This is an embodiment of the 4-power single-Sive-OR circuit and the 8-power single-Sive-OR circuit of the present invention.

本発明による４大力イクスクル一シブオア回路ンＩＩｌ
成している素子数は、３０素子である。８大力イクスク
ル一シブオア回路は、７０素子である。Four major power circuits according to the present invention
The number of elements is 30. The 8-power single-or circuit has 70 elements.

１４図、第５図に用いられている２大力イクスクル一シ
ブオア回路は、従来例に用いられているものである。＠
４図？用いた４大力イクスクル一シブオア回路ン構成し
たものが、第５図である。The two-power exclusive-OR circuit used in FIGS. 14 and 5 is the one used in the conventional example. @
Figure 4? FIG. 5 shows the configuration of the four-power exclusive OR circuit used.

この場合、回路？構成している素子数は、１ｏ６素子で
あり、本発明の回路構成よりも、約３倍強の素子数が必
要である。第５図を用いた４大力イクスクル一シブオア
回路の必要素子数は、４２素子である。８大力イクスク
ル一シブオア回路の場合は、９８素子である。第５因ン
用いた回路構成においても、本発明の回路構成の万が素
子数が少ないことがわかる。In this case, the circuit? The number of elements included is 106 elements, which is about three times as many elements as the circuit configuration of the present invention. The required number of elements for the four-power exclusive OR circuit using FIG. 5 is 42 elements. In the case of an 8-power single-OR circuit, there are 98 elements. It can be seen that even in the circuit configuration using the fifth factor, the circuit configuration of the present invention has a smaller number of elements.

第７図には、従来例として用いられている４大力イクス
クル一シブオア回路の別口路？示した。FIG. 7 shows a separate route for the four-power exclusive-OR circuit used as a conventional example. Indicated.

第７図の回路の素子数は、７２素子必要となり、本発明
の回路構成の素子数より２倍強必要なことがわかる。ま
たＷＪＺ図の回路の場合は、各ドレインが共通なため、
出刃信号ラインに大きな浮遊容量がつき、信号遅延量χ
大きくしている。It can be seen that the circuit shown in FIG. 7 requires 72 elements, which is more than twice as many as the number of elements in the circuit configuration of the present invention. In addition, in the case of the circuit shown in the WJZ diagram, each drain is common, so
There is a large stray capacitance in the Deba signal line, and the signal delay amount χ
It's getting bigger.

更には、第６１ｇ、＠７１ｉＱで用いた回路では、半導
体装置を太き（するため、装置自体のコストがあがり、
本発明の回路と比−較すると、全（有効性を失なってい
る。Furthermore, in the circuits used in No. 61g and @71iQ, the semiconductor device is made thicker (because of this, the cost of the device itself increases,
Compared to the circuit of the present invention, it has lost all (effectiveness).

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、回路素子数が減るた
め、信号遅延量が小さいという効果ン有する。As described above, according to the present invention, since the number of circuit elements is reduced, there is an effect that the amount of signal delay is small.

従って、本発明の回路は、高速動作する半導体装置に最
適の回路となっている。また回路素子数が少ないため、
半導体装置自体の大きさｔ小さくすることができる。従
って半導体装置自体のコストダウンの点でも、本回路は
効果ン有する。Therefore, the circuit of the present invention is an optimal circuit for semiconductor devices operating at high speed. Also, since the number of circuit elements is small,
The size t of the semiconductor device itself can be reduced. Therefore, this circuit is also effective in reducing the cost of the semiconductor device itself.

本発明の回路は、多大カイスフルーシブオア回路のみな
らず多入方イクスクルーシプノア回路にも応用でき、ま
た、入力端子数に関係なく、最小の素子数で回路？構成
できる。The circuit of the present invention can be applied not only to multi-input exclusive OR circuits but also to multi-input exclusive NOR circuits. Can be configured.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の回路構成に用いる２人カイクスクル
ーシブオア回路の一実施例？示した図。 第２１は、本発明の回路構成に用いる２人力イクスクル
ーシプノア回路の一実施例ケ示した１゜第３図は、本発
明の４大力イクスクル一シブオア回路で、第１図の２人
カイクスクルーシブオア回路３つ？用いて構成した回路
図。 第４図は、本発明の８大力イクスクル一シブオア回路で
、第１図の２人カイクスクルーシブオア回路７つ用いて
構成した回路図。 第５図は、従来例の多入力イクスクルーシブオア回路に
用いられていた２人力イクスクルーシブオア回路図。 第６図は、従来例の多入力イクスクルーシブオア回路に
用いられていた２入力イクスクルーシブオア回路図。 ｗＩＪＺ図は、第５図の回路方式で構成されていた４入
力イクスクルーシブオア回路図。 第８図は、従来用いられていた４入力イクスクルーシブ
オア回路の一例を示した図。 １．２・・・・・・入力端子 ３・・・・・・出力端子 ４．５・・・・・・インバータ回路 ６・・・・・・クロックドゲート回路 ７・・・・・・アナログスイッチ ２０１．２０２・・・・・・入力端子 ２０３・・・・・・出力端子 ２０４．２０５・・・・・・インバータ回路２０６・・
・・・・クロックドゲート回路２０７・・・・・・アナ
ログスイッチ回路１０．１１，１２．１３・・・・・・
入力端子１４・・・・・・出力端子 １５．１６．１７・・・・・・第１図で示した２入力イ
クスクルーシブオア回路 ２０．２１，２２，２５，２４，２５，２６．２７・・
・・・・入力端子 ２８・・・・・・出力端子 ２９．３０，５１，５２，５５，５４．３５・・・・・
・４１図で示した２入力イクスクルーシブオア回路 ４０．４１・・・・・・入力端子 ４２・・・・・・出力端子 ４５．４６・・・・・・２人力ＮＯＲ回路４４・・・・
・・２人力ＮＡＮＤ回路 ４５・・・・・・インバータ回路 ５０．５１・・・・・・入力端子 ５２・・・・・・出力端子 ５３．５４．５５・・・・・・インバータ回路５７．５
８・・・・・・クロックドゲート回路（５１，６２，６
３，６４・・・・・・入力端子６５・・・・・・出力端
子 ６６、　６８．　６９．　７０．　７１．　７２．　７
５・・・・・・４人力ＮＯＲ回路 ７４・・・・・・８人力ＮＯＲ回路 ６７・・・・・・４人力ＮＡＮＤ回路 ７５、７６、７７、７８．７９．８０．８１．８２．８
５゜８４．８５，８６．８７・・・・・・インバータ回
路１０１．１０２，１０５，１０４・・・・・・入力端
子１０５・・・・・・出力端子　１０６・・・・・・電
源ＶＤＤ１０７・・・・・・電源ＶＳＳ １０８．１０９，１１０，１１１・・・・・・インバー
タ回路１１２・・・・・・Ｐｃｈ　）ランジスタ１１３
・・・・・・Ｎｃｈ　）ランジスタ。 以上FIG. 1 is an example of a two-person exclusive OR circuit used in the circuit configuration of the present invention. The diagram shown. 21 shows an example of the two-person exclusive OR circuit used in the circuit configuration of the present invention. FIG. Three exclusive OR circuits? A circuit diagram constructed using the following. FIG. 4 is a circuit diagram of an eight-power exclusive OR circuit of the present invention, which is constructed using seven two-person exclusive OR circuits shown in FIG. FIG. 5 is a two-person exclusive OR circuit diagram used in a conventional multi-input exclusive OR circuit. FIG. 6 is a two-input exclusive-OR circuit diagram used in a conventional multi-input exclusive-OR circuit. Figure wIJZ is a 4-input exclusive-OR circuit diagram constructed using the circuit system shown in Figure 5. FIG. 8 is a diagram showing an example of a conventionally used four-input exclusive OR circuit. 1.2... Input terminal 3... Output terminal 4.5... Inverter circuit 6... Clocked gate circuit 7... Analog Switches 201, 202... Input terminal 203... Output terminal 204, 205... Inverter circuit 206...
...Clocked gate circuit 207...Analog switch circuit 10.11, 12.13...
Input terminal 14...Output terminal 15.16.17...Two-input exclusive OR circuit 20.21, 22, 25, 24, 25, 26.27 shown in FIG.・・・
... Input terminal 28 ... Output terminal 29.30, 51, 52, 55, 54.35 ...
・Two-input exclusive OR circuit shown in Figure 41 40.41...Input terminal 42...Output terminal 45.46...Two-man power NOR circuit 44...・
...Two-man power NAND circuit 45...Inverter circuit 50.51...Input terminal 52...Output terminal 53.54.55...Inverter circuit 57. 5
8...Clocked gate circuit (51, 62, 6
3, 64... Input terminal 65... Output terminal 66, 68. 69. 70. 71. 72. 7
5... 4-man powered NOR circuit 74... 8-man powered NOR circuit 67... 4-man powered NAND circuit 75, 76, 77, 78.79.80.81.82.8
5゜84.85, 86.87... Inverter circuit 101.102, 105, 104... Input terminal 105... Output terminal 106... Power supply VDD107 ......Power supply VSS 108.109,110,111...Inverter circuit 112...Pch) transistor 113
・・・・・・Nch) Langister. that's all

Claims (1)

【特許請求の範囲】[Claims] 多入力イクスクルーシブオア回路の構成において、イン
バータ回路とクロックドゲート回路とアナログスイッチ
回路で構成された２入力イクスクルーシブオア回路ある
いは、２入力イクスクルーシブノア回路を複数個用いて
構成することを特徴とする多入力イクスクルーシブオア
回路。In the configuration of a multi-input exclusive OR circuit, a 2-input exclusive OR circuit consisting of an inverter circuit, a clocked gate circuit, and an analog switch circuit, or a configuration using multiple 2-input exclusive OR circuits. A multi-input exclusive-OR circuit featuring:
JP1384685A 1985-01-28 1985-01-28 Multi-input exclusive or circuit Pending JPS61173521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1384685A JPS61173521A (en) 1985-01-28 1985-01-28 Multi-input exclusive or circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1384685A JPS61173521A (en) 1985-01-28 1985-01-28 Multi-input exclusive or circuit

Publications (1)

Publication Number Publication Date
JPS61173521A true JPS61173521A (en) 1986-08-05

Family

ID=11844638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1384685A Pending JPS61173521A (en) 1985-01-28 1985-01-28 Multi-input exclusive or circuit

Country Status (1)

Country Link
JP (1) JPS61173521A (en)

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