JPH06232733A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To provide a basic cell able to realize an OR function and an AND function through function changeover with the less number of transistors(TRs). CONSTITUTION:Six TRs 1-6 are employed, two of the TRs are connected as one set to form a circuit of 3-input and 1-output, the TRs 1-4 of the 6 TRs are used for switches and the remaining 2-TRs 5,6 are used for a basic cell. A control input terminal 7 is connected to each gate of the TRs 1-4 used as the switches and a switch 9 is connected to sources of the TRs 2, 3 and a switch 8 is connected to gates of the TRs 5, 6 acting like the basic cell. Thus, the equal function to a 2-input AND function and a 2-input OR function is provided by selecting a logic level to the control input terminal 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit.

[0002]

As is well known, semiconductor logic circuits are used in various devices such as computers. The semiconductor logic circuit has an ON-OFF signal and "H"-
The calculation is performed using the “L” signal or the like, and various logical operation processes are performed.

There are three basic functions of the semiconductor logic circuit, an AND function, an OR function and a NOT function. Then, various circuits such as an FF circuit, an arithmetic circuit, and a memory circuit are configured by appropriately combining these basic functions.

[0004]

Conventionally, the AND function is an AND circuit, the OR function is an OR circuit, and the NOT function is a NOT circuit.
As with circuits, the functions that each circuit had were decided. That is, in the conventional logic circuit, one cell corresponds to one function. Therefore, for example, if you want to switch between AND and OR functions, use
Since ND circuit, OR circuit, multiplexer, etc. are required,
A total of 14 transistors were needed. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to realize a basic cell capable of realizing a logical sum function and a logical product function by switching functions with a small number of transistors.

[0005]

A semiconductor logic circuit according to the present invention comprises a first switch circuit formed by connecting two different types of transistors, N-type and P-type, in parallel, and an N-type and P-type two. A second switch circuit formed by connecting transistors of two different types in parallel, and a third switch circuit formed by connecting transistors of two different types of N type and P type in series, The switch circuit is connected in the order of the first switch circuit, the third switch circuit, and the second switch circuit, and the AND function / O
A control input terminal to which an R function switching signal is input is commonly connected to gate terminals of all the transistors that form the first switch circuit and the second switch circuit, and a first input signal is input. Of the transistors of different types selected one by one from the first switch circuit and the second switch circuit, respectively. The input terminal is commonly connected to the gates of the two transistors of the third switch circuit, and the output terminal is connected to a line connecting the two transistors of the third switch circuit in series. It is a semiconductor logic circuit.

[0006]

Since the present invention comprises the above technical means, the third switch circuit is a 2-input AND circuit or a 2-input depending on the signal input to the control input terminal to which the AND function / OR function switching signal is input. It functions as an OR circuit, and one cell realizes two functions.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor logic circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a semiconductor logic circuit of the present invention. In FIG. 1, the first switch circuit A is composed of transistors 1 and 2. In this case, the transistor 1 is a P-type transistor and the transistor 2 is an N-type transistor.

The second switch circuit B is composed of transistors 3 and 4. Of these transistors, transistor 3 is a P-type transistor and 4 is an N-type transistor.
Type transistor. Further, the third switch circuit C
Is composed of transistors 5 and 6. In this case, the transistor 6 is a P-type transistor and 5 is an N-type transistor.

In connecting these transistors 1 to 6, the transistors 1 and 2 and the transistors 3 and 4 are connected in parallel. Also, the transistor 5,
6 is connected in series, these transistor 5,
The first input terminal 8 is commonly connected to the gates of the gates 6.

On the other hand, a second input terminal 9 is connected to each source of the transistors 2 and 3. An output terminal 10 for outputting a logic signal is connected to a line connecting the transistors 5 and 6 in series.

In the semiconductor logic circuit thus constructed, when the logic level of the control input terminal 7 is "0", the logic level of the output terminal 10 is either the first input terminal 8 or the second input terminal 9. If the value is "1", it becomes "1". Further, when both the input terminals 8 and 9 are "0", it becomes "0". That is, a two-input OR having the first input terminal 8 and the second input terminal 9 as inputs
The circuit is constructed.

When the logic level of the control input terminal 7 is "1", the logic level of the output terminal 10 is "0" when either the first input terminal 8 or the second input terminal 9 is "0". It becomes "0". Further, when both the input terminals 8 and 9 are both "1", it becomes "1". That is, a 2-input AND circuit having the first input terminal 8 and the second input terminal 9 as inputs is configured.

As described above, in the semiconductor logic circuit of this embodiment, by switching the logic level of the control input terminal 7 to "0" or "1", a cell which can realize two different kinds of functions is composed of 6 transistors. Can be realized.

[0014]

As described above, according to the present invention, by switching the input logic level of the control input terminal, a basic cell having the same function as the two-input AND circuit and the two-input OR circuit is composed of 6 transistors. Therefore, the circuit configuration for realizing these functions can be simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor logic circuit showing an embodiment of the present invention.

[Explanation of symbols]

 1, 3, 6 P-type transistor 2, 4, 5 N-type transistor 7 Control input terminal 8, 9 Input terminal 10 Output terminal A First switch circuit B Second switch circuit C Third switch circuit

Claims (1)

[Claims] 1. A first switch circuit in which two different types of N-type and P-type transistors are connected in parallel, and two different types of N-type and P-type transistors are connected in parallel. A second switch circuit, and a third switch circuit in which two different types of N-type and P-type transistors are connected in series, and each of the switch circuits is a first switch circuit and a third switch circuit. The switch circuit and the second switch circuit are connected in this order, and the control input terminal to which the AND function / OR function switching signal is input is connected to the gates of all the transistors forming the first switch circuit and the second switch circuit. The first input terminal that is commonly connected to the terminals and receives the first input signal is the first input terminal.
Connected in common to the sources or drains of transistors of different types selected one from each of the switch circuit and the second switch circuit, and the second input terminal to which the second input signal is input is the third input terminal.
The semiconductor logic circuit is configured such that the output terminal is connected to a line that connects the two transistors of the switch circuit in common and the two transistors of the third switch circuit are connected in series.