JPS61172396A - Manufacture of hybrid ic device - Google Patents

Manufacture of hybrid ic device

Info

Publication number
JPS61172396A
JPS61172396A JP1243085A JP1243085A JPS61172396A JP S61172396 A JPS61172396 A JP S61172396A JP 1243085 A JP1243085 A JP 1243085A JP 1243085 A JP1243085 A JP 1243085A JP S61172396 A JPS61172396 A JP S61172396A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
patterns
hybrid
external connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1243085A
Other languages
Japanese (ja)
Other versions
JPH0230198B2 (en
Inventor
利昭 平間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP1243085A priority Critical patent/JPH0230198B2/en
Publication of JPS61172396A publication Critical patent/JPS61172396A/en
Publication of JPH0230198B2 publication Critical patent/JPH0230198B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 【技術分野〕 本発明は、複数の混成集積回路パターンを有する混成集
積回路装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method of manufacturing a hybrid integrated circuit device having a plurality of hybrid integrated circuit patterns.

〔背景技術〕[Background technology]

2個の異なる混成集積回路実装基板の外部接続端子の一
部を共通化して複数構造の混成集積回路装置とする場合
、従来は、2種の基板で別々に回路形成実装を行い、共
通の外部接続端子を取り付ける段階で初めて、別々の2
個の実装基板が組合わされ、しかる後に1個の回路ブロ
ックとしての機能チェックが可能となるために1片方の
回路基板だけが悪いために、両方の基板をだめにすると
いう問題があった。この問題を防ぐために、あらかじめ
片方の回路基板だけを、他方の標準の回路基板を組み込
んだ測定回路でチェックする方法がとられるが、微妙な
定数の調整を必要とする場合   ・には、前記チェッ
クが合格した基板同志を組合わせても電気特性の不良が
起るという欠点があった。
When making a hybrid integrated circuit device with multiple structures by sharing some of the external connection terminals of two different hybrid integrated circuit mounting boards, conventionally, circuit formation and mounting were performed separately on the two types of boards, and the common external connection terminals were For the first time, at the stage of installing the connection terminals, separate two
Since two mounting boards are combined and it is then possible to check the function as one circuit block, there is a problem that if only one circuit board is defective, both boards are ruined. In order to prevent this problem, a method is used in which only one circuit board is checked in advance using a measurement circuit that incorporates the other standard circuit board, but if delicate constant adjustments are required, the above-mentioned check can be performed. There was a drawback in that even if boards that passed the test were combined, the electrical characteristics would be defective.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、これらの欠点を除去するために、あら
かじめ組合わせる別々の混成集積回路パターンの電気特
性の調整を容易にすることができる技術を提供すること
にある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique that can facilitate adjustment of the electrical characteristics of separate hybrid integrated circuit patterns that are combined in advance, in order to eliminate these drawbacks.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される考案のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。
A brief overview of typical devices among the devices disclosed in this application is as follows.

すなわち、複数個の混成集積回路パターンを1個の絶縁
基板上に設け、それらの混成集積回路パターンの共通す
る外部接続端子取付用電極を電気的に接続し、あらかじ
め組合わせる別々の混成集積回路パターンの電気特性の
調整を行った後、各混成集積回路パターンに分割し、所
定の混成集積回路の2個を組合わせて装置を形成するよ
うにしたものである。
That is, a plurality of hybrid integrated circuit patterns are provided on one insulating substrate, and common external connection terminal attachment electrodes of these hybrid integrated circuit patterns are electrically connected, and separate hybrid integrated circuit patterns are combined in advance. After adjusting the electrical characteristics of the hybrid integrated circuit, the hybrid integrated circuit is divided into individual hybrid integrated circuit patterns, and two predetermined hybrid integrated circuits are combined to form a device.

〔発明の構成〕[Structure of the invention]

以下、本発明の構成について、実施例とともに説明する
Hereinafter, the configuration of the present invention will be explained along with examples.

なお、実施例を説明するための全図において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。
In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

第1図及び第2図は、本発明の一実施例の混成集積回路
装置の製造方法を説明するための図であり、第1図は、
複数個の混成集積回路パターンが1個の絶縁基板上に設
けられた分割以前の混成集積回路基板の概略構成を示す
平面図、第2図は。
1 and 2 are diagrams for explaining a method of manufacturing a hybrid integrated circuit device according to an embodiment of the present invention, and FIG.
FIG. 2 is a plan view showing a schematic configuration of a hybrid integrated circuit board before division, in which a plurality of hybrid integrated circuit patterns are provided on one insulating substrate.

2個の複数個の混成集積回路パターンを有する絶縁基板
を組合わせた混成集積回路装置の断面図である。
FIG. 2 is a cross-sectional view of a hybrid integrated circuit device in which two insulating substrates having a plurality of hybrid integrated circuit patterns are combined.

第1図及び第2図において、1は混成集積回路実装用基
板であり1例えば、96%のアルミナ(AQ203)等
からなる基板を用いる。この混成集積回路実装用基板1
の上に、外部接続端子取付用電極2が対向する2個の混
成集積回路パターン領域3Aと4A、3Bと4B、3C
と40.3Dと4Dに渡ってそれぞれ形成されている、
第1図では、外部接続端子取付用電極2以外の他の部分
は省略しであるが、混成集積回路パターンは同一のもの
でも異なったものでもよい、また、混成集積回路パター
ンが同じでも実装する部品の有無や。
In FIGS. 1 and 2, reference numeral 1 denotes a board for mounting a hybrid integrated circuit, and a board made of, for example, 96% alumina (AQ203) is used. This hybrid integrated circuit mounting board 1
Above are two hybrid integrated circuit pattern areas 3A and 4A, 3B and 4B, and 3C, with electrodes 2 for attaching external connection terminals facing each other.
and 40. formed over 3D and 4D, respectively.
In Figure 1, other parts other than the external connection terminal mounting electrode 2 are omitted, but the hybrid integrated circuit patterns may be the same or different, and even if the hybrid integrated circuit patterns are the same, they can be mounted. Whether there are parts or not.

種類、数量が異なっていてもよい。The types and quantities may be different.

また、混成集積回路パターンは、第1図に示すように、
同一の組合わせのパターンが多数個並んでいてもよい。
In addition, the hybrid integrated circuit pattern, as shown in FIG.
A large number of patterns having the same combination may be lined up.

次に、外部接続端子6を取り付ける前の第1図に示す状
態のままで、各混成集積回路パターン領域3Aと4A、
3Bと4B、3Gと40.3Dと4Dのそれぞれの電気
特性を調整する。
Next, in the state shown in FIG. 1 before the external connection terminal 6 is attached, each hybrid integrated circuit pattern area 3A and 4A,
Adjust the electrical characteristics of 3B and 4B, 3G and 40.3D and 4D.

この電気特性の調整の後、前記第1図に示す混成集積回
路基板1は、混成集積回路パターン分割線5の部分で分
割され、第21i!iIに示すように、例えば、2個の
混成集積回路パターン領域3Aと4A(3Bと4B、3
Cと40.8Dと4D)からなる混成集積回路基板3と
4を組合わせ、前記外部接続端子取付用電極2に外部接
続端子6を取り付けてコーティング剤7でコーティング
することにより、混成集積回路装置が完成する。
After adjusting the electrical characteristics, the hybrid integrated circuit board 1 shown in FIG. 1 is divided along the hybrid integrated circuit pattern dividing line 5, and the 21i! As shown in iI, for example, two hybrid integrated circuit pattern areas 3A and 4A (3B and 4B, 3
By combining the hybrid integrated circuit boards 3 and 4 consisting of C, 40.8D, and 4D), attaching the external connection terminal 6 to the external connection terminal attachment electrode 2, and coating it with the coating agent 7, a hybrid integrated circuit device is obtained. is completed.

なお、第2図において、8は電子部品である。In addition, in FIG. 2, 8 is an electronic component.

〔効果〕〔effect〕

以上説明したように、本発明によれば、以下に述べるよ
うな効果を得ることができる。
As explained above, according to the present invention, the following effects can be obtained.

(1)複数個の混成集積回路パターンを1個の絶縁基板
上に設け、それらの混成集積回路パターンの共通する外
部接続端子取付用電極2以外的に接続し、各混成集積回
路の電気特性を調整した後、各混成集積回路パターンに
分割し、所定の混成集積回路の複数個を組合わせて装置
を形成することにより、各混成集積回路の電気特性の調
整を同一平面内で容易に行うことができるので、機能調
整が簡単となる。
(1) A plurality of hybrid integrated circuit patterns are provided on one insulating substrate, and the electrical characteristics of each hybrid integrated circuit are determined by connecting the hybrid integrated circuit patterns using a common external connection terminal mounting electrode 2. After adjustment, the electrical characteristics of each hybrid integrated circuit can be easily adjusted within the same plane by dividing the hybrid integrated circuit into patterns and combining a plurality of predetermined hybrid integrated circuits to form a device. This makes it easy to adjust functions.

(2)前記(1)により、実装後の電気特性チェックを
早期に行うことができる。
(2) According to (1) above, the electrical characteristics can be checked at an early stage after mounting.

(3)前記(1)により、付加価値の小さいうちに不良
を排除することができるので、生産コストを低減するこ
とができる。
(3) According to (1) above, it is possible to eliminate defects while the added value is small, so production costs can be reduced.

(4)前記(1)により、従来、セラミック板のカナガ
タやマスクパターンが2組必要だったのに対し1本発明
では1組でよいので、開発費用の低減が可能である。
(4) According to the above (1), whereas conventionally two sets of ceramic plate cantilevers and mask patterns were required, the present invention requires only one set, so development costs can be reduced.

以上、本発明を実施例にもとすき具体的に説明したが1
本発明は、前記実施例に限定されるものでなく、その要
旨を逸脱しない範囲において種々変更可能であることは
言うまでもない。
The present invention has been specifically explained above using examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は、本発明の一実施例の混成集積回路
装置の製造方法を説明するための図であり、 第1図は、複数個の混成集積回路パターンを1個の絶縁
基板上に設けた分割以前の混成集積回路基板の概略構成
を示す平面図、 第2図は、2個の複数個の混成集積回路パターンを有す
る絶縁基板を組合わせた混成集積回路装置の断面図であ
る。 図中、1・・・混成集積回路実装用基板、2・・・外部
接続端子取付用電極、3,4・・・混成集積回路パター
ン、5・・・混成集積回路パターン分割線、6・・・外
部接続端子、7・・・コーティング剤、8・・・電子部
品第1図 第2図
1 and 2 are diagrams for explaining a method of manufacturing a hybrid integrated circuit device according to an embodiment of the present invention. FIG. FIG. 2 is a plan view showing a schematic configuration of the hybrid integrated circuit board provided above before division; FIG. be. In the figure, 1... Substrate for mounting hybrid integrated circuit, 2... Electrode for attaching external connection terminal, 3, 4... Hybrid integrated circuit pattern, 5... Hybrid integrated circuit pattern dividing line, 6...・External connection terminal, 7...Coating agent, 8...Electronic components Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] アルミナ等の絶縁基板上に混成集積回路パターンを形成
して成る混成集積回路実装基板を2個組合わせて1個の
回路ブロックとした混成集積回路装置の製造方法におい
て、複数個の混成集積回路パターンを1個の絶縁基板上
に設け、それらの混成声積回路パターンの共通する外部
接続端子取付用電極を電気的に接続し、各混成集積回路
パターンの電気特性を調整した後、各混成集積回路パタ
ーンに分割し、所定の混成集積回路パターンの複数個を
組合わせて装置を形成することを特徴とする混成集積回
路装置の製造方法。
In a method for manufacturing a hybrid integrated circuit device in which two hybrid integrated circuit mounting boards each having a hybrid integrated circuit pattern formed on an insulating substrate such as alumina are combined into one circuit block, a plurality of hybrid integrated circuit patterns are formed on an insulating substrate such as alumina. are installed on one insulating substrate, the common external connection terminal mounting electrodes of those hybrid integrated circuit patterns are electrically connected, and the electrical characteristics of each hybrid integrated circuit pattern are adjusted. 1. A method of manufacturing a hybrid integrated circuit device, comprising dividing the device into patterns and combining a plurality of predetermined hybrid integrated circuit patterns to form the device.
JP1243085A 1985-01-28 1985-01-28 KONSEISHUSEKIKAIROSOCHINOSEIZOHOHO Expired - Lifetime JPH0230198B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1243085A JPH0230198B2 (en) 1985-01-28 1985-01-28 KONSEISHUSEKIKAIROSOCHINOSEIZOHOHO

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1243085A JPH0230198B2 (en) 1985-01-28 1985-01-28 KONSEISHUSEKIKAIROSOCHINOSEIZOHOHO

Publications (2)

Publication Number Publication Date
JPS61172396A true JPS61172396A (en) 1986-08-04
JPH0230198B2 JPH0230198B2 (en) 1990-07-04

Family

ID=11805070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1243085A Expired - Lifetime JPH0230198B2 (en) 1985-01-28 1985-01-28 KONSEISHUSEKIKAIROSOCHINOSEIZOHOHO

Country Status (1)

Country Link
JP (1) JPH0230198B2 (en)

Also Published As

Publication number Publication date
JPH0230198B2 (en) 1990-07-04

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