JPS61172330U - - Google Patents
Info
- Publication number
- JPS61172330U JPS61172330U JP5633985U JP5633985U JPS61172330U JP S61172330 U JPS61172330 U JP S61172330U JP 5633985 U JP5633985 U JP 5633985U JP 5633985 U JP5633985 U JP 5633985U JP S61172330 U JPS61172330 U JP S61172330U
- Authority
- JP
- Japan
- Prior art keywords
- output
- switch
- circuit
- delay circuit
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
第１図は本考案の一実施例を示す説明図、第２
図は本考案の他の実施例を示す回路図、第３図お
よび第４図は本考案の変形例を示す説明図、第５
図および第６図は従来のスイツチ切換検出方式を
示すＣＰＵ使用システムの構成図である。
図中、１はＣＰＵ（マイクロプロセツサ）、２
はインターフエース回路、３，３′はスイツチ、
５はスイツチ切換検出回路、Ｒ２，Ｃ１は遅延回
路、ＥＯＲは不一致回路、ＥＮＯＲは一致回路で
ある。
Fig. 1 is an explanatory diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing another embodiment of the present invention, FIGS. 3 and 4 are explanatory diagrams showing modified examples of the present invention, and FIG.
6 and 6 are block diagrams of a CPU-based system showing a conventional switch switching detection method. In the figure, 1 is a CPU (microprocessor), 2
is the interface circuit, 3, 3' is the switch,
5 is a switch change detection circuit, R 2 and C 1 are delay circuits, EOR is a mismatch circuit, and ENOR is a match circuit.
Claims (1)
る遅延回路と、該スイツチ出力および該遅延回路
の出力を２入力とする一致または不一致回路とを
備え、該一致または不一致回路の出力変化を該ス
イツチ出力を取込むマイクロプロセツサへの割込
信号とすることを特徴とするスイツチ切換検知回
路。 It is equipped with a delay circuit that delays a switch output that switches between high and low binary values, and a match or mismatch circuit that has two inputs as the switch output and the output of the delay circuit. A switch switching detection circuit characterized in that the output is used as an interrupt signal to a microprocessor that receives the output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5633985U JPS61172330U (en) | 1985-04-16 | 1985-04-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5633985U JPS61172330U (en) | 1985-04-16 | 1985-04-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61172330U true JPS61172330U (en) | 1986-10-25 |
Family
ID=30579842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5633985U Pending JPS61172330U (en) | 1985-04-16 | 1985-04-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61172330U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818734A (en) * | 1981-07-27 | 1983-02-03 | Seiko Epson Corp | Key input detecting circuit system |
| JPS59136839A (en) * | 1983-01-25 | 1984-08-06 | Mitsubishi Electric Corp | Interruption input device |
-
1985
- 1985-04-16 JP JP5633985U patent/JPS61172330U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818734A (en) * | 1981-07-27 | 1983-02-03 | Seiko Epson Corp | Key input detecting circuit system |
| JPS59136839A (en) * | 1983-01-25 | 1984-08-06 | Mitsubishi Electric Corp | Interruption input device |
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