JPS61171210A - Delay circuit - Google Patents

Abstract

PURPOSE:To attain ease of continuous control of delay in the unit of clock by applying a control signal for setting the delay to two delay circuit sections applying the control of delay while using 2<n>-clock and 1-clock of sampling clocks as the unit respectively. CONSTITUTION:An input signal is divided into 2<n>-phase by a serial/parallel converter 3 in one delay circuit section, each divided signal is inputted respective ly into memory circuits 4,1-4,2<n> and after the same amount of delay is applied, the result is inputted to a parallel/serial converter 5, where they are restored into a single-phase signal so as to attain the control of delay while using 2<n>- clock as one unit. 2<l>-Sets (l=0-n-1) of unit delay elements retarding the input signal by 1 clock are connected in series in the other delay circuit section. Thus, n-set of building blocks, one block of which consists of a selector changing over a signal subject to 2<l>-clock delay by the unit delay elements and a signal before the delay and of a unit delay element connected in series, are constituted and the control of the delay in the unit of clocks ranging 1-(2<n>-1) clocks is attained by changing over the n-set of the selectors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a delay circuit that maintains a single delay path, particularly for signals that require high-speed operation such as III source signals.

[Background of the invention]

An example of using a sampled NFC signal delayed by a certain number of clocks is disclosed in Japanese Patent Laid-Open No. 115995/1983. This is done by delaying the composite power 2-fV visual signal like the NTaC system by one line period or one frame period, and by reducing the correlation with the current signal, the brightness signal and the color light signal are separated. It is something.

When using a semicircular memory as a delay system, the maximum operating frequency is determined by its cycle time, but it is relatively low due to constraints such as memory power consumption and memory capacity.
There are times when you have no choice but to use a device that is

On the other hand, in the case of Gaszuka signal #: tNTSC system, it is approximately 4.2M.
Wait for H2 band. Generally, the sampling frequency is
3. fsc -10.7MHz (fsc brown sub-transmission frequency, approximately 3.58MHz) or 4. fsc-14,5MH
If Z happens, it will require a lot of effort. In addition, even wider-band signals such as high-definition TV cameras)! ii
! When used as an extension circuit, very fast operation is required.

Therefore, for the 1jlII image signal)! ! Using the half-body memory as it is as an extension element may be one step away.

A conceivable method for realizing a continuous operation using high-speed elements is to perform multiphase parallel processing, as shown in FIG. 2, for example.

The input signal ri is first divided into, for example, P phases (P is a positive integer) by the serial/parallel converter 8. Divided fi7' (P phase signal is ne-e, n/%, Lee circuit M19.1-MP9, P
By the same name I! The signal is then input to the parallel-series signal generator 10 and returned to a single-phase signal.

Address generator 11Fi gives an address to the memory and samples the input signal a)/(r) P
/ Change only one output box for each otsuk J
It's a counter. The address is an example of ViO~(K-1
) until it lands, if it is repeated, one mesori circuit will have t values of data)! ! ! can be extended.

Therefore, in this case, i! A'lt-F'i as a circuit
(PXK) Clock delay sound.

By performing parallel processing in this way, the delay circuit operates:
&g degree can be made P times the operating speed of the memory circuit.

The delay sound is controlled by the memory circuit using the address generator 11.
This is done by changing the 1st value to . At this time, if you change only one preset value: I! ! Since the delay sound as a delay circuit changes by P 072, it is not possible to set the amount of delay in units of clocks. Therefore, for delay-type control in clock units, it is necessary to add a circuit that includes (P-1) unit chains iA and purple elements and a selector that selects the output of this unit delay element. be.

In this @ meeting as well, delay-type fine control using 1 clock from 1 to (P-1) clock as 1 unit is performed by the above selector, and rough control using P clock as 1 unit is performed by counter reset i + i It was necessary to perform the process separately, such as at various times, and it was not easy to perform operations to continuously change the delay ti microclocks.

[Purpose of the invention]

An object of the present invention is to provide a delay circuit that can easily perform continuous control of delay-type clock units when constructing a delay circuit capable of high-speed operation using a relatively low-speed semicircular memory. Our goal is to provide the following. , [@requires # of light] In order to achieve the above object, the present invention configures a delay circuit from a first delay circuit section 0 and a second delay circuit section shown below. That is, the first delay circuit section is configured to receive the input signal,
After parallel transformation into 2n phases (n is a positive integer), 2
By inputting it into a single memory circuit and delaying it by the same violet, and then inputting it into a parallel/direct converter and converting it back to a single-phase signal, delay-type control using 2n clocks as one unit can be performed. It is something to do. Further, the second delay circuit section includes t2 (1-1 -
o, 1. -・-, n-1) if column connection [and a selector that switches between a signal delayed by 2' clocks by this series-connected unit delay tree and a signal before being delayed; /=0 to l! It consists of n structural units up to =n-1, and by switching these n selectors, 1 to (
P-1) Controls the amount of delay up to the clock in units of clocks.

In order to control the delay in these two delay circuit sections, a signal expressing the delay amount in binary is used. The n bits from the lower order of the control signal are used as control signals for the n selectors in the second delay circuit section.
Ru. Furthermore, the upper bits starting from the (n+1)th bit from the lower order are used as control signals to the address generator that supplies addresses to the memory of the first delay circuit section.

[Embodiments of the invention]

An embodiment of the present research will be described below with reference to FIG.

1 is a parallel processing circuit, which has the same configuration as in FIG. 3
is a serial-to-parallel converter, and the 4-digit memory circuit 5 is a parallel-to-parallel to IJ converter. 8 is an address generator.

2.0 to 2. (n-1) #i switching circuit, with 2' input signals connected in series (I!+=xQ, 1...
....

This is a circuit that switches and outputs a signal delayed by 2' clocks by m unit series elements of n-1) and an input signal. 6
．． 0 to 6. (n-1) is a selector, 7.1 to y, <l
-1) is a unit delay element.

This is a 9ri delay amount setter.

The operation will be explained below.

The input signal is input to the serial-parallel converter 3 and divided into P phases.
Ru. Here, P is a number that can be expressed as f (n is a positive integer). Each of the signals divided into 2n phases is sent to each n memory circuit M14,1 to MP4. After being input to P and delayed by the same amount, it is input to the parallel-to-serial converter 5 and converted back to a single-phase signal. ! The address generator 8 supplies addresses to each of the memory circuits mentioned above, and is a counter that changes its output value by one every 2r'' clocks.

The output of the parallel-to-serial converter 5 is input to a unit delay element 7.1 and delayed by one clock. The one-clock delayed signal and the undelayed signal are input to selector 806.0, and one of them is selected depending on the required amount of delay.

Next, the output of selector BQ6.0 is connected to unit delay element 7.2,
7.3 is input in series and delayed by 2 clocks. The signal delayed by two clocks and the signal before being delayed are selected by selector st6. t and select one of the nine depending on the amount of delay required.

Thereafter, similar operations are repeated.

The output of the selector 5n-26, (n 2) is connected to the unit delay element y, ? -' to 7. (2"-1) and is input to 2n-1 serially connected signals and delayed by 2n-1 clocks. The signal delayed by t-1 clocks and the signal before the delay are input to the selector 5n-16, (n - and selects and outputs one of n depending on the required delay gf.

In order to control the delay lid, the necessary delay amount is first expressed in binary form by the delay amount setter 9 and output. The lowest bit of this output is input to a bo Fi selector 806.0 and is used as a control signal to switch between a signal delayed by one clock and a signal delayed by :j4Ijg. Also, the second bit b from the bottom of the output of the delay amount setter 9
1 is input to the selector 51t5.1 and is used as a control signal for switching between a signal delayed by two clocks and a signal before the delay. Thereafter, in the same way, the output of the setter 9 from the lower order to the nth bit bn-1 is set to the delay g1.
Selectors SO6, O to 5n-16, (n-1) respectively
It is used as a control signal up to.

On the other hand, the (n+1)th pit bn and above from the lower end of the output of the delay amount setter 9 is input to the address generator 8 which supplies an address to the memory circuit, and is used as a control signal for changing the delay in the memory circuit. Use as 9.

For example, when the delay amount setter 9 sets the power setting 111f1r1 to 7Z, the selector 5o (S, O selects the output of the unit delay system 7.1, and the other selectors select the output of the previous stage). When setting +111 is set to 2, selector so6.
The output of the ori parallel to serial converter 5 is selected, and the selector 816.
1 is two unit delay elements 7, 2.7.5 connected in series.
selects the signal delayed by two clocks. Other selectors select the output of the previous stage. Also, when the set value is 3, both selector 806.0 and selector 816.1
The signal delayed by the unit delay element is selected, and the other selector selects the output of the 1iTJ stage.

In this way, when the set value is up to (2-1), it can be expressed by the lower n bits of the delay amount setter 9, and this AG)n
By inputting these control signals from each SO to the selector at 8n-1t, it is possible to easily match the set value of the M-endo and the total number of unit delay elements passed through.

When the set value exceeds t, the (n+1)th bit from the lower order bit of the output of the delay amount setter 9 turns on and the upper bit changes. After this, the upper bits output a value with two clocks as one unit.

On the other hand, in the memory circuit, the amount of delay is controlled by changing the preset value to the address generator 8 that supplies addresses to the memory circuit. Output fi2 of converter 5
The clock will change. Therefore, the upper bit of the output of the delay amount setter 9 is set to the reset 11! of the address generator 8! By using it as is as I, it is possible to easily control the amount of delay in units of one every two clocks in the memory circuit.

According to this embodiment, the overall operating speed can be made twice the operating speed of the memory circuit by performing serial-parallel conversion into two phases and performing parallel processing. In addition, the first delay circuit section is composed of these 61 memory circuits and is capable of controlling the amount of delay every n2 clocks, and is composed of (2") unit delay elements and n selectors. 1~(2-1) Clock
The control signal for each of the second delay circuit sections that can be controlled every clock up to J can be obtained by simply expressing the delay tk in binary numbers, and the control signal for the delay amount of the entire delay circuit can be obtained by It can be done easily and continuously.

In this embodiment, the second delay circuit section is installed after the second delay circuit section, but the present invention is not limited to this. Fig. 5 shows another embodiment according to the present invention.

In addition, in this example, in order to simplify the explanation, 2
=, 4, that is, fI=m2, in the 0 non-implementation column, the first delay circuit section that controls the fjA extension in units of 4 clocks t-1 is configured such that each clock from 1 to 5 clocks is The second step is to control the S treatment as a unit.
Follow the delay circuit.

First, the input signal is input to the unit delay system 17 and delayed by one clock. The signal delayed by one clock and the signal before being delayed are input to the selection 58015 and switched. Selector 8
The output of 015 is input to two unit Ma elements 18 and 19 connected in series and delayed by two clocks. The selector 5 selects this two-clock delayed signal and the signal before being delayed to -.
116 [Select.

The output ri of the selector 5116 is input to the serial/parallel converter 20 and divided into four-phase signals. These four-phase signals are input to memory circuits 2l, 22, 23, and 24, respectively, and are delayed by the same amount. The four-phase signals output from the four memory circuits are input to the parallel-to-serial converter 25, where they are returned to single-phase signals. and output as a control signal. The lowest pick) bo is input to the selector Ei015, A, 1 clock, I! ! Delayed signal and signal before delay t-4gJ
? It is used as a control signal for 2 from the lower case
The th bit b1 is similarly input to the selector 5116 and is used as a control signal for switching between the signal delayed by two clocks and the signal before the delay. Further, the upper bits starting from the third bit b2 from the lower order are used as one reset for the address generator 26, and are used to control the amount of delay in units of four clocks.

In a non-embodiment, the operating speed of the delay circuit can be made four times the operating speed of the mesori circuit. In addition, the delay amount can also be controlled using the slow IJ & setter 2, which expresses the set value in binary numbers.
By using 7, it can be easily and conveniently performed.

In this implementation series, 11 t
m2, but the present invention is not limited to this. n
is a value that can be determined by a positive divisor, and it's okay.

In addition, in this embodiment, a circuit consisting of a delay system 17 and a selector 15, and a unit M delay system 18.19
Although the circuit is arranged in conjunction with the circuit constituted by the selector 16, the present invention is not limited thereto. st of the first S-mother circuit section
Even if I divide it into rm, I won't use the sword. You can also order the person #
According to the present invention, in a delay circuit that performs multi-phase parallel I processing and enables high-speed production, the delay is set at 141st position in 2 clocks. a first delay circuit section that roughly controls the amount;
1 to (2-1) A second delay circuit section that performs fine control of the amount of delay in units of one clock, and t1.
Both can be controlled by inputting binary values.

Therefore, the delay amount t in the delay circuit is expressed as 4 in binary, and the lower n bits are used as the control signal for the second delay circuit, and the upper bits for the C river are used as the control signal for the first delay circuit. By using this as a clock, it is possible to easily control the amount of delay continuously on a clock-by-clock basis.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment according to the present invention, and FIG.
1072 is a diagram showing a case where the continuous firing circuit is constructed of a memory circuit performing multi-phase parallel processing, and FIG. 3 is a block diagram showing another embodiment according to the present invention. 1...Parallel processing circuit 2...Switching circuit, 5.10.20...Serial-to-parallel converter 4.1-4. P, 11.1-11. P, 2l~24
...Parallel-serial converter

Claims (1)

[Claims] 1. In a delay circuit that delays a sampled input signal by a fixed number of clocks using the sampling clock as the minimum unit, 2^n (n is a positive integer) clock of the sampling clock is used. a first delay circuit section that controls the amount of delay as one unit; a second delay circuit section that controls the amount of delay using one clock of the sampling clock as one unit; and a delay in the two delay circuit sections. and means for supplying a control signal for setting the amount. 2. In claim 1, the first delay circuit section is divided by a serial-to-parallel converter that converts the input signal into 2^n-phase serial to parallel converters, and the serial-to-parallel converter. 2^
Input each of n signals and delay them by the same amount 2^
It has n memory circuits and a parallel-to-serial converter that inputs 2^n signals delayed by the same amount by the 2^n memory circuits and returns them to a single-phase signal. Features a delay circuit. 3. In claim 1 or 2, the second delay circuit section includes 2^l unit delay elements (l= 0, 1, . A delay circuit characterized in that it has n structural units from l=0 to l=n-1. 4. In claims 1 to 3, the control signal for setting the delay amount in the first delay circuit section and the second delay circuit section is a signal expressing the delay amount in binary numbers. A delay circuit characterized by using.