JPH02166919A - Digital pll system - Google Patents

Abstract

PURPOSE:To reduce quantization jitter by fractionating a phase control quantity without setting the clock frequency of a clock source higher by selecting the output of plural variable frequency dividers sequentially by a phase control signal. CONSTITUTION:The subject system is provided with a delay circuit 2 which shifts the phase of the clock source 3, N frequency dividers 1 which input a clock in which a phase generated by the delay circuit is shifted by 360 deg./N, a selection circuit 5 which selects the output 10 of a timing clock, and a control circuit 4 which controls the N variable frequency dividers 1 and the selection circuit 5 setting the phase control signal as input. Therefore, when the phase control signal 9 is inputted from a phase comparator to the control circuit 4, the clock in which a timing is shifted from the present timing clock by 360 deg./RN (R: frequency division ratio) is selected from the frequency division clock of the output of each frequency divider 1. In such a manner, it is possible to set the phase control quantity of one time at 1/N without multiplying the clock frequency of the clock source by N, and to reduce the quantization jitter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital PLL system, and relates to a single circuit configuration suitable for reducing jitter.

[Conventional technology]

Digital PLL method with conventional logic circuit configuration (% formula %) rci6 °C
This is a form that performs phase control only for the clock.

Therefore, in order to narrow one-phase control, the method used is to increase the clock frequency of the clock source. However, as the bit rate increases, it becomes difficult to increase the clock frequency of the clock source due to the limit of gate operation speed.

[Problem to be solved by the invention]

The digital PLL method of the conventional logic circuit configuration shown in Fig. 2 (
Ce5sna and L@vy (Q DPLL or H
a1m@-'s DPXJL), the variable frequency divider 1. It consists of a phase comparator 6, a quantization circuit that converts the comparison result into a total doji, and a loop filter 8, and a variable frequency divider 10 with a frequency division ratio 'J-
Let's say R.

The minimum phase control amount is 5606/R, and the υ frequency division ratio is set to R+1. by the phase control signal 9. Phase control is performed by changing R- and IK. Therefore, in order to enhance the 1-phase control amount,
The method used was to increase the clock frequency of clock source 3 to increase the division ratio of the variable frequency divider, but as the signal bit rate became faster, the operating speed of the variable frequency divider gate increased. Due to the limit of , it is difficult to increase the clock frequency of the clock source. Therefore, quantization jitter cannot be reduced, and at a somewhat high bit rate.

Analog PLL etc. were used. The purpose of the present invention is to
The object of the present invention is to finely control the amount of phase control and completely reduce quantization jitter without increasing the clock frequency of a clock source.

[Means to solve the problem]

In order to achieve the above object, the clock source S and variable frequency divider 1 of the conventional digital PLL system (FIG. 2) are replaced with a delay circuit 2 that shifts the phase t of the clock source 5 as shown in FIG.
and the phase created by its delay direction MK is 5606/N
N variable frequency dividers 1 that receive clocks shifted by 1
, the selection circuit 5 for selecting the timing clock output 11Ji, and the 1-phase control variable number 9 are input, and the N variable frequency dividers 1
A control circuit 4f for controlling the selection circuit 5 is added.

[Effect]

Since clocks with a phase shift of 560°/N are input to the variable frequency divider in FIG. The phase is shifted by (branch ratio). Therefore, when the phase control signal 9 for advancing or delaying the phase from the phase comparator is inputted to the control circuit 4Vc, the current timing clock signal 560 is calculated from the branch clock output from each variable frequency divider 1.
Select the one with °/RN deviation °C. Or, by setting the frequency division ratio of the variable frequency divider 1 to t-R+1 or R-1, a divided clock that is shifted by 560'/RN can be created.
It is outputted via the selection circuit 5 as a timing clock.

This allows you to increase the frequency of the clock source by
The phase control amount k can be set to 1/N.

〔Example〕

Below is a complete circuit block diagram (Fig. 3) and a time chart (Fig. 4) of an embodiment in which two variable frequency dividers are used according to the present invention.
I will explain using

The variable frequency dividers 1 and 12 in FIG. 3 contain the clock 4 of the clock source 5 and its inverted clock! (a clock whose phase is shifted by 18Q°) is used as input for variable frequency division.

In this embodiment, a case is shown in which the frequency division ratio R of the variable frequency dividers 1 and 12 is set to 6. That is, when the signal t - y is "L", the variable division ratio R is 6. When the signal 6° is "H", the variable frequency divider 1 is 5. When the signal f is "H", the variable frequency divider 1 is 5. 12 is 5. When the signal d is “H”, the variable frequency divider 1 is 7. When the signal t is °H°, the variable frequency divider 12 is 7. The control circuit 4 is UP times the phase control signal 9. Each control signal d% A is generated from the signal DOWN signal.When the signal A is °H°, the division clock of the variable frequency divider 12 is -t-, and when the signal A is "Lo, the divided clock number of the variable frequency divider 10 is used as the timing clock. select. The time chart shows the operation when the UP double signal °H” and advances the phase are shown in Figure 4 (a).
) is the branch clock b as the timing clock output 10.
When f is selected, the UP double signal °■゛ becomes the selection circuit 4
[The signal At-"p" is used to switch the °C frequency divided clock O to the timing clock.The input clock of the variable frequency divider 12 has a phase of 180 degrees with the input clock of the variable frequency divider 1.
The phase of 1 branch clock 4 and o is 1 because it is shifted by 0.
It is shifted by 80°/6. Therefore, the phase can be advanced by 180°/6 by switching from the timing clock output 10t to the frequency-divided clock 3 to c.

At this time, set the signal 4 to t-H, set the frequency division ratio of the variable frequency divider 1 to 5, and reverse the phase relationship between the branch clock and G to that before switching (by ct-180°/6 with respect to the branch clock 4). The phase can be advanced by 180°/6 by continuously inputting the UP multiplied signal (by advancing the phase), and by switching from the branch clock G to the 4VC timing clock, by VC. At this time as well, in order to reverse the phase relationship of the divided clocks C to that before switching, the division ratio of the variable frequency divider 20 is set to t-5.

On the other hand, the operation when one phase is delayed is shown in the time chart of Fig. 4 (Raku). 4. The branch clock is set in the same way as when advancing the phase. When the DOWN signal of the cf1 phase control signal 9 reaches °H°, it is alternately switched and used as a timing clock output,
By setting the signal d or t to °H° and setting the division ratio of the variable frequency divider 1 or 12 to 7.

If the phase relationship of the branch clocks Ir and c before switching is reversed, the DOWN signal will be changed to 180°, and the timing clock will be changed to 180°.
'//can be delayed by 6.

As mentioned above, the conventional digital PLLvc% is 1
The phase control amount is the frequency division ratio of the variable frequency divider.

Case 5 when the clock frequency of the clock source is equal to this embodiment
6 D'/6, but according to this example, tao6
The Vc can be made finer by /6 and /2, and the amount of jitter can also be reduced to /2.

〔Effect of the invention〕

According to the present invention, it is possible to control the phase control lid once by 17N without increasing the clock source lock frequency of the digital PLL by t''N times. This has the effect of reducing the amount of energy used.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.
The block diagram of the conventional digital PLL method is shown below.
FIG. 5 is a block diagram showing a specific example of FIG. 1, and FIG. 4 is a timing chart of the fifth factor. 1...Variable frequency divider, 2...Delay circuit. 4...Control circuit. 6...Phase comparator. 8...Loop filter. 3... Clock source. 5...Selection circuit. 7...Quantization circuit. 9...Phase control signal. 10... Timing check output. 11... Inverting circuit, 12... Variable frequency divider. Figure 2

Claims (1)

[Claims] 1. In the digital PLL system, the timing information is extracted from the input information, a quantized phase control signal is created, the clock source clock is variably divided by the control of the phase control signal, and phase synchronization is achieved. A plurality of frequency dividers are provided, and the clock input to each variable frequency divider is changed in phase from the clock of the clock source,
The outputs of the plurality of variable frequency dividers are controlled by the phase control signal,
A digital PLL method characterized by sequential selection.