JPS61171131A - Formation of patterned conductive layer on semiconductor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention relates to the field of antireflection coatings for use in metal layer photolithography in connection with semiconductors.

[Conventional technology and its problems]

In the manufacture of semiconductor devices, it is desirable to form conductive paths on the surface of the device. Conventionally, conductive paths are formed by forming a metal layer on the surface of a semiconductor and patterning the metal layer using standard photomasking techniques. One problem with this prior art was the high reflectivity of the metal layer. In the patterning process, a layer of photoresist is coated over the metal layer and then exposed to form a pattern of conductors. A disadvantage of this method is that more photoresist is exposed than desired. The incident light is reflected from the metal layer at an angle such that areas of the photoresist adjacent to the desired area are also exposed. A subsequent photoresist development step will undercut the photoresist, resulting in a wider opening than desired.

To solve this problem, anti-reflective coating (ARC) is used.

That is, Anti-reflective coating
Previous attempts have been made to use .ngs). ARC
Materials used for polyimide, 5ilN4
, and polysilicon. These materials prevent undercutting of the photoresist layer by absorbing light incident on the device, thereby preventing light from reaching the gold metal layer and being reflected. However, these materials introduced other drawbacks to the IJ) graphic method. For example, Si, N4 and polysilicon require high temperatures (350-400° C.) for deposition, promoting the formation of high spots within the metal layer.

Also, the thickness of coatings formed from these materials is not uniform, resulting in an excess of particles.

Spin-on polyimide AB for name tags
C has been attempted due to its ease of deposition and low processing temperatures. However, spin-on ABC requires a rigorous baking process that must be accurate to plus or minus 2 degrees Celsius, and tight control of the spray developer. Also, spin ARC does not work well for all surface shapes. J U.S. Patent No. 4.23
No. 9.810 discloses sputtering amorphous silicon onto a metal substrate in the manufacture of solar cells.

However, this patent discloses the deposition of an amorphous silicon layer doped with N-type impurities followed by the deposition of an aluminum layer and a silicon layer. And in that patent, the amorphous silicon layer is not used as an anti-reflective coating or to aid in photolithography.

U.S. Pat. No. 4,297,392 discloses the use of thin films of amorphous silicon in the manufacture of thin film photoconductors. Although it has been noted that amorphous silicon absorbs light, its use as an anti-reflection coating in photolithographic processes has not been disclosed.

[Summary of the invention]

It is an object of the present invention to effectively solve the above problems by using sputtered amorphous silicon as an ARC.

In accordance with the present invention, by using a thin sputtered silicon layer as an anti-reflection coating, the formation of nicks and waists caused by undercutting of the photoresist is avoided. The formation of a thin layer (eg, about 50-500 angstroms) of sputtered silicon prior to application of the photoresist layer will result in the formation of the complete photoresist pattern and contours. In addition to the following: 1. This method is less affected by surface conditions and surface shapes. Another advantage is that sputtered silicon and metal layers can be etched in one step. In a preferred embodiment of the invention, amorphous silicon is used as the anti-reflective coating.

〔Example〕

Improvements in metal layer photolithography methods for monomerization are described below. In the following description, numerous specific details are set forth, such as layer thicknesses, etc., in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that such specific details may be practiced without such specific details, so as not to otherwise obscure the invention in unnecessary detail. , well-known processing steps are not described.

In order to better understand the present invention, the prior art will first be explained.

Conventional Photolithography Figures 1 and 2 illustrate conventional photolithography methods. In FIG. 1, a metal layer 12 is formed on a substrate 11. Next, a photoresist layer 13 is formed on the metal layer.

Then, certain areas of the photoresist layer 13 are exposed to light to form a pattern that allows certain portions of the metal layer 12 to be selectively removed by etching, leaving the desired conductive pattern for the intended device. irradiate. However, as shown in FIG. 1, the light incident on the photoresist layer 13 hits the metal layer 12, is reflected at a certain angle, and enters the adjacent photoresist layer 13, thereby exposing the photoresist layer.

After development, the exposed portions of photoresist layer 13 are removed, as shown in FIG. As can be seen from FIG. 2, the edge of the opening 15 is not perpendicular to the metal layer 12, but is undercut. The reason for such undercutting is that the incident light is reflected from the metal layer 12. 6 When the metal layer 12 is etched, the resulting metal strip is notched, similar to the photoresist layer 13. Since the current density is related to the area of the conductive surface, the current density of the resulting strip metal layer can be an order of magnitude higher than the desired current density.

This may result in reduced performance or even failure of the device.

Embodiment of the Invention Similar to the prior art, a substrate 11 as shown in FIG.
A metal layer 12 is formed thereon. The invention applies in this respect. A thin layer 161 of glazed amorphous silicon is formed over metal layer 12. In the preferred embodiment of the invention, amorphous silicon layer 16 is approximately 50 to 500 angstroms thick. This step is carried out at room temperature. This temperature is low enough that it does not promote the formation of high spots (h i Lto e ks ) in the metal layer. High spots, or small bulges, create stresses in the metal. The stress can result in the formation of cracks and voids, both of which have a negative impact on the performance of the device. and polysilicon AB
This is a problem for C.

Next, a photoresist layer 131 shown in FIG. 4 is formed on the silicon layer 16. No further processing of the sputtered silicon layer is required before shaping the photoresist layer. If spin-on ABC was adopted, 14
A severe calcination step carried out at 5±2°C would have been necessary. The present invention generally has the advantage of fewer processing steps and that its application does not involve harsh processing steps. The photoresist layer 13 is then baked and exposed in the same manner as without the Al1 layer.

As shown in FIG. 4, a portion of the photoresist layer 13 where a metal pattern will be formed is irradiated with light. Sputtered silicon layer 16 absorbs the light and prevents it from entering photoresist layer 13 . therefore,
One contour of the pattern is precisely aligned with the incident light.

The photoresist layer 13 is then developed and intensely baked (ha).
rd bake) t-do. Thereby, the opening 17
．． 18 (FIG. 5) is formed in photoresist layer 13.

The development process is performed as if there were no sputtered silicon layer, unlike traditional spin-on ARC, which requires a harsh spray development process. At this point, the silicon layer 16 and the metal layer 12 are simultaneously plasma etched up to the surface K of the substrate 11. The ability to etch the sputtered silicon layer and the metal layer simultaneously is a major advantage. If the metal layer is aluminum, oxides may form on its surface when exposed to light. The aluminum oxide layer makes the etching process more difficult to control. Since there is no need to remove the silicon layer before metal etching, the metal surface remains covered, inhibiting oxide formation. Therefore, metal etching can be performed with better control.

Finally, the remaining photoresist layer 13 is stripped and the remaining silicon layer 16f is removed from the surface of the metal layer 120 of FIG. 6, leaving the desired conductor pattern t-. Application of the present invention results in the formation of a complete pattern in the metal layer 12 without creating nicks in the patterned strip conductor.

Both DC and RF sputtering can be used to deposit the silicon layer. Since this sputtering process is not sensitive to topography, no nicks, bridging, or constrictions in the metal lines are observed.

Although the invention has been described with respect to patterning metal layers, the invention is also useful for patterning refractory metal silicides.

Another advantage of the present invention is improved metal electromigration and a wide processing window for rework. During reprocessing, the sputtered silicon is not affected by photoresist strippers in the same way that conventional ABCs are affected by photoresist strippers. This reduces the rigors of removing the photoresist layer during reprocessing.

The above describes an improvement in metal layer (IJ) graphics that prevents undercutting of photoresist layers. By providing a sputtered amorphous silicon layer, undercutting is eliminated and harsh processing steps are avoided.

[Brief explanation of drawings]

1 is a cross-sectional view of a conventional semiconductor with a metal layer deposited and a photoresist coated over the metal layer; FIG. 2 is a cross-sectional view of a conventional semiconductor after an opening has been formed in the photoresist layer; 3 is a cross-sectional view of the semiconductor with a metal layer and sputtered silicon deposited over the metal layer; FIG. 4 is a cross-sectional view of the semiconductor of FIG. 3 with a photoresist layer deposited; FIG. FIG. 5 is a cross-sectional view of the semiconductor, and FIG. 6 is a cross-sectional view of the fourth factor semiconductor after the opening is formed in the photo resist layer. 6 is a perspective view of the semiconductor of FIG. 5 after removal; FIG. 11@@@@board, 12...0. Metal layer, 1311-・
- Photoresist i, ts...sputtered silicon layer, 1y, ta...opening.

Claims (7)

[Claims] (1) a. forming a layer of sputtered silicon on a conductive layer formed on a semiconductor; b. following formation of the sputtered silicon layer; forming a layer of photoresist thereon; c. patterning the conductive layer by photolithography, wherein light incident on the semiconductor is reflected from the conductive layer during the photolithography; A method for forming a patterned conductive layer on a semiconductor, characterized in that exposure of undesired portions of the photoresist layer is prohibited. (2) The method of claim 1, wherein the silicon layer has a thickness of about 50 to 500 angstroms. (3) The method according to claim 1, wherein the silicon layer is amorphous. (4) A method according to claim 1, characterized in that DC sputtering is used to form the silicon layer. (5) A method according to claim 1, characterized in that RF sputtering is used to form the silicon layer. (6) The method according to claim 1, wherein the conductive layer is metal. (7) The method according to claim 1, wherein the conductive layer is a refractory metal silicide.