JPS61170125A - Output circuit - Google Patents

Abstract

PURPOSE:To transmit an output signal including two voltage modes from an existing output terminal without increasing the number of output terminals by using a switch means to transmit of two inverter circuits in an output circuit recognizing the operating state and stop state of an integrated circuit from the output terminal. CONSTITUTION:When a control signal V2 is at an L level, a P-FET41 and an N-FET42 are turned on, a P-FET31 and an N-FET32 are turned off, the application of a power supply voltage VDD is stopped from the 1st inverter circuit 10. Thus, the 1st output signal V10 or the 2nd output signal V20 is transmitted from an output terminal 3 in either the busy mode or the standby mode. Then whether the integrated circuit is either in the busy mode or in the stand by mode is detected by detecting the voltage level of the output signals V10, V20.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an output circuit provided in an integrated circuit (IC) such as an LSI, and particularly to an output circuit provided in an integrated circuit (IC) such as an LSI.
) and a stand-by mode.

(Prior Art) Conventionally, memory circuits and the like connected to a CPU (Central Processing Unit) are composed of integrated circuits such as LSIs, and output circuits provided in the integrated circuits include, for example, P-type field effect transistors (hereinafter referred to as P-type field effect transistors). Some devices were constructed with an inverter circuit in which an N-type field effect transistor (hereinafter referred to as F, N FET) and an N-type field effect transistor (hereinafter referred to as F, N FET) were connected in series.

In this type of output circuit, 11 integrated circuits are housed in a package, so the number of terminals, etc.
) If you receive the warranty and notify the operating status, the G output terminal may not be installed.

(Problem to be Solved by the Invention) However, when an output circuit without a busy output terminal as described in J- is connected to a CPU, the busy time of the integrated circuit is calculated in the CPU. This puts a load on the CPU because it has to determine the standby mode or standby mode and send a control signal from the CPU to the integrated circuit during standby mode. That is, c
Not only does the PU require a program that calculates the amount of business hours, but other processing cannot be performed while the business hours are being calculated, which places a burden on the CPU, resulting in inconveniences in usage. there were.

This invention solves the problems that the prior art had,
A busy output terminal can be provided subject to restrictions such as the number of terminals on the pan cage, etc., thereby providing an output circuit that solves the problem of placing a load on the CPU.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides P FETs and NF
a first inverter circuit connected in series to the power source and transmitting a first output signal having a voltage amplitude value that is opposite in phase to the input signal and approximately the same as that of the power source from an output terminal; a second input signal having a P FET and an N FET, and sending a second output signal from the output terminal having a voltage amplitude value that is opposite in phase to the input signal and smaller than a voltage amplitude value of the power source; an N control signal having a first voltage level and a second voltage level, and switches the first output signal or the second output signal depending on the voltage level of the control signal; and a switch means for transmitting the signal from the output terminal.

(Function) According to the present invention, since the output circuit is configured as described below, the first and second inverters I'j! Each of the seven output signals is switched by the switch means according to the voltage level of the control signal, and sent out from the output terminal. Therefore, if the first or second voltage level of the control signal is replaced with the busy mode or stand/bay mode inside the integrated circuit, the two modes can be included from the existing output terminals without increasing the number of output terminals. can send output signals. Therefore, the above problem can be eliminated.

(¥ Flow Side) FIG. 1 is a circuit diagram of an output circuit showing a first embodiment of the present invention. In FIG. 1, l is the first input terminal inside the integrated circuit in which the output circuit of this embodiment is incorporated, 2 is the second input terminal inside the integrated circuit, and 3 is the input terminal led out from the integrated circuit. The first input terminal l has a data signal (input signal) Vl inside the integrated circuit, and the second input terminal 2 has a data control signal (UJJ control signal) V2 inside the integrated circuit. Each is input.

Between the first input terminal 1 and the output terminal 3, the first and second
Inverter circuits 10 and 20 are connected in parallel. The first inverter circuit 10 has a configuration in which a train of P FET II and a train of N FET 12 are connected in series, and the gates of both FET II and +2 are connected to the first input terminal l.
In addition, the drains of both FET II, +2 are connected to the lJj power terminal 3, respectively. Further, the second inverter circuit 20 connects the drain of P FET 2+ and the diode 2
The anode of 2 and the cathode of this tie auto 22 are connected in series with a train of N FET 23, and the gates of both FETs 21 and 23 are connected to the first input terminal 1.
The capacitors F of the diodes are connected to the output terminals 3, respectively.

On the other hand, both FETIs constituting the first inverter circuit 10
For each source of I, 12, P FET31 and N FE
Each train of T32 is connected to each other. Also,
Both FETs 21 and 2 forming the second inverter circuit 20
2, each source has a P FET41 and an N FET42.
Each train is connected to each other. And P F
The sources of ET31, 4+ are supplied with the power supply voltage VDD or N F
The power supply voltage VSS is applied to the source ET32 and ET32 (7), respectively. Here, the source voltage VDD is a positive voltage, and VSS is a ground potential. Furthermore, P FET31
The gates of the N FET 32 and the P FET 42 are connected to the second input terminal 2 via the inverter 50.
The 41 gates are each directly connected to the second input terminal 2.

Note that the P FET 31 and N FET 32 constitute a first switch means, and the P FET 41 and N FET 4 constitute a second switch means. Further, in FIG. 1, VIO is the first output signal output from the first inverter circuit 10, and V2O is the first output signal output from the second inverter circuit 2.
This is the second output signal output from 0.

The operation of the output circuit configured as described below-1- will be explained with reference to FIG. Note that FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1.

When the data signal v1 inside the freezing circuit is a rectangular wave as shown in Figure 2, when the control signal v2, which has two levels of "H" and "L'" levels, is at °H" level, P
FET31 and N FET32 are on, P FET
41 and N FET 42 are turned off, the power supply voltage VDD is applied to the first inverter circuit 10, but the power supply voltage VDD is not applied to the second inverter circuit 20. Therefore, P FETII and N FETII
The first output circuit VIO determined by 2 is outputted from the output terminal 3. Here, the first output signal VIO is a rectangular wave that is in opposite phase to the input signal v1 and has approximately the same amplitude as the power supply voltage VDD.

On the other hand, when the control signal v2 is at the "L" level, P F
ET 41 and N FET 42 are on, P FE
Since T 31 and N FET 32 are in the off state,
Application of the power supply voltage VDD to the first inverter circuit 10 is stopped, but power supply voltage VDD is applied to the second inverter circuit 20. Therefore, P FET 21. A second output signal V20 determined by the diode 22 and the N FET 23 is output from the output terminal 3. here,
The second output signal V20 is a rectangular wave whose H level is lower by the voltage drop of the diode 22 than the first output signal VIO.

Therefore, if the output circuit that operates as described above is incorporated into an integrated circuit and the busy mode and stand/hay mode inside the freezing circuit are replaced with the control signal v2, the first The output signal v10 or the second output signal V20 will be sent out from the output terminal 3. Therefore, the output signal VIO, V
By detecting the 20 voltage levels, it is possible to detect whether the integrated circuit is in busy mode or standby mode.

FIG. 3 is a circuit diagram of an output circuit showing a second embodiment of the invention. Note that the same elements as those in FIG. 1 are given the same reference numerals.

The difference between this output circuit and the first embodiment is that the second
The anode of the diode 22 provided in the inverter circuit 120 is connected to the output terminal 3, and the load N FET 12+ is connected to the output terminal 3. Here, the source and gate of the N FET 121 are short-circuited and the power supply voltage VDD is applied thereto, and the 1ζ
rain is connected to output terminal 3.

The operation of this output circuit is as shown in FIG. 4, which is a signal waveform diagram of each part of the circuit in FIG.
The power supply voltage VDD is connected to the second inverter circuit 120 via
is applied to Then, P FET2+, diode 2
2, the output signal v120 determined by N FET23 and N FET121 is sent out from output terminal A3. In other words, in the output signal V120, among the output signals of the second inverter circuit 120, the "L" level is 11 as the resistive element.
<N The waveform is slightly raised by FET12+. Therefore, from the output terminal 3, the control signal V2 is
Two types of output signals VIO and VI20 having different amplitude values are sent out depending on the H''' and L levels.

Therefore, the same effects as the first embodiment are achieved.

In addition, "-" No. 1. In the second embodiment, the diode 22 and the N FET 121 are used as means for changing the amplitude value of the signal output from the second inverter circuit 20, 120.
However, the present invention is not limited to these, and various other modifications are possible.

For example, a resistor 122 as shown in FIG. 5(a) or a P FET diode 123 as shown in FIG. 5(b).

It can be used to replace diode 22 in Figure 1, or
The N FET diode 124 as shown in Figure (C) is connected to the third
Even if the diode 22 in the figure is replaced, it can be used as described in 1. Second
It has the same action φ effect as the embodiment.

FIG. 6 shows an example of application of an integrated circuit incorporating an output circuit according to the present invention. In FIG. 6, 200 is an integrated circuit such as a memory circuit incorporating the output circuit of the present invention;
1 is a GPU 20+ that controls the integrated circuit 200, and 2
02 is a sense circuit 202 that detects a voltage level using a comparator or the like. When a 111 output signal VIO, V20 or V120 as shown in FIGS. 2 and 4 is sent to the sense circuit 202 from the output terminal 3 of the output circuit incorporated in the integrated circuit 200, the sense circuit 202 A change in the level of the output signal VIO, V20 or V120 is detected and a busy signal v202 is given to the CPU 201. This allows the CPU 201 to detect that the integrated circuit 200 is in busy mode and to provide the flJ control signal v201 to the integrated circuit 200. in this way,
If the output circuit of this invention is used, the integrated circuit 200 and the CP
The interface of U201 is simplified and the CP
U20 ] can be reduced.

(Effects of the Invention) As described in detail above, according to the present invention, the output signals of the first and second inverter circuits are switched by the switch means and sent out from the output terminals, so that the number of output terminals is increased. Output signals including two voltage modes can be sent from existing output terminals without having to do so. Therefore, if the output circuit of the present invention is incorporated into an integrated circuit, the load on the CPU controlling the integrated circuit can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an output circuit showing a first embodiment of this invention, FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1, and FIG. 3 is an output showing a second embodiment of this invention. Circuit diagram, 4th
The figure is a signal waveform diagram of each part of the circuit in Figure 3, Figure 5 (a), (
b) and (c) are diagrams showing a modification of the present invention, and FIG. 6 is a diagram showing an application example of an integrated circuit incorporating the output circuit of the present invention. 3... Output terminal, 10... First inverter circuit, 20, 120... Second inverter circuit, 31.32... First switch means, 4
1.42...Second switch means, Vl...
...Data signal (input signal), v2...Control signal, VIO...Output signal of the first inverter circuit, V2O...Output of the second inverter circuit Signal, VDD, VSS...Power supply voltage. Applicant's agent Kakashi Kaki 14 < +4-) 1 Figure 5 ((b) (Figure 6)

Claims (1)

[Claims] 1. A P-type field effect transistor and an N-type field effect transistor connected in series to a power source and supplied with an input signal, having a voltage amplitude value that is opposite in phase to the input signal and approximately the same as that of the power source; a first inverter circuit that sends out a first output signal from an output terminal having a first output signal of a second inverter circuit configured to send out from the output terminal a second output signal having a voltage amplitude value smaller than a voltage amplitude value of the power source; and a second inverter circuit provided with a control signal having first and second voltage levels to control the second inverter circuit. an output circuit comprising: switch means for switching the first output signal or the second output signal according to the voltage level of the signal and sending the signal from the output terminal; 2. The switch means includes a first switch means that turns on and off between the power supply and the first inverter circuit based on a first voltage level of the control signal, and a second switch means that turns on and off between the power supply and the first inverter circuit based on a first voltage level of the control signal. 2. The output circuit according to claim 1, further comprising second switch means for switching on/off between the power source and the second inverter circuit based on a voltage level.