JPS61168953A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61168953A JPS61168953A JP60009436A JP943685A JPS61168953A JP S61168953 A JPS61168953 A JP S61168953A JP 60009436 A JP60009436 A JP 60009436A JP 943685 A JP943685 A JP 943685A JP S61168953 A JPS61168953 A JP S61168953A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- output terminal
- integrated circuit
- power supply
- terminal out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 230000000295 complement effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 16
- 230000003071 parasitic effect Effects 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体集積回路装置、特に、相補製ＭＯ８半導
体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary MO8 semiconductor integrated circuit device.
（従来の技術）
従来、Ｖ相補型ＭＯＳ半導体集積回路装ｒａｔ＜以下Ｃ
ＭＯ８−ＩＣと記す）はＮ型半導体領域内に形成された
ＰチャンネルＭＯＳトランジスタと、Ｐ減半導体領域内
に形成されたＮチャンネルＭＯ８トランジスタにより構
成されるので、これらを構成するＰ散拡散層とＮｆｉ拡
赦拡散の間で寄生バイポーラトランジスタが形成される
。(Prior art) Conventionally, a V-complementary MOS semiconductor integrated circuit device rat<hereinafter C
MO8-IC) is composed of a P-channel MOS transistor formed in an N-type semiconductor region and an N-channel MO8 transistor formed in a P-reduced semiconductor region. A parasitic bipolar transistor is formed between the Nfi amended diffusions.
（発明が解決しようとする問題点） 上記のような０ＭＯ８−ＩＣの出力端子にサージ。(Problem to be solved by the invention) A surge occurs at the output terminal of the 0MO8-IC as shown above.
電圧が印加されると、寄生バイポーラトランジスタが導
通状態になシ、いわゆるラッチアップと呼ばれる現象が
生じ、このため、０ＭＯ８−ＩＣに大電流が流れ、素子
が破壊するという欠点があった。When a voltage is applied, the parasitic bipolar transistor becomes non-conductive, resulting in a phenomenon called latch-up, which causes a large current to flow through the 0MO8-IC, resulting in destruction of the device.
このラッチアップ現象について図面を用いて説明する。This latch-up phenomenon will be explained using the drawings.
第７図は従来の０ＭＯ８−ＩＣの一例の回路図である。FIG. 7 is a circuit diagram of an example of a conventional 0MO8-IC.
この０ＭＯ８−ＩＣは、ソースが電源端子ＶＤＤに接続
され、ドレインが出力端子ＯＵＴに接続され、ゲートが
入力端子ＩＮに接続されたＰチャンネル間０８トランジ
スタＱ！と、ソースが電源端子■８８＃こ接続され、ド
レインが出力端子ＯＵＴに接続され、ゲートが入力端子
ＩＮに接続されたＮチャンネルＭＯＢ）ランジスタＱ２
とから成シ、出力端子ＯＵＴから否定論理信号を取シ出
すＣＭＯ８論理回路である。This 0MO8-IC has a P-channel 08 transistor Q! whose source is connected to the power supply terminal VDD, whose drain is connected to the output terminal OUT, and whose gate is connected to the input terminal IN. and an N-channel MOB transistor Q2 whose source is connected to the power supply terminal 88#, whose drain is connected to the output terminal OUT, and whose gate is connected to the input terminal IN.
This is a CMO8 logic circuit which takes out a negative logic signal from an output terminal OUT.
第８図は第７図の回路を半導体基板に実現したときに生
ずるラブチアツブ現象を説明するための模式的断面図で
ある。FIG. 8 is a schematic cross-sectional view for explaining the love drop phenomenon that occurs when the circuit of FIG. 7 is implemented on a semiconductor substrate.
第８図において、１はＮ型半導体基板、２はｒをアイラ
ンド％ ３はＰチャンネルＭＯＳトランジスタＱ、のソ
ースとなるＰ＋拡散層、４はトランジスタＱ、のドレイ
ンとなるＰ 拡散層、５はＮチャンネルＭＯＳトランジ
スタＱ、のソースとなるＮ＋拡散層、６はトランジスタ
Ｑ２のドレインとなるＮ＋拡散層、７はＶＤＤ 電位
供給用Ｎ＋拡散層、９は絶縁層、１０はトランジスタＱ
１のゲート絶縁層、１１はトランジスタＱｚのゲート絶
縁層、１２はＶＤＤ 電源端子、１３はＶ８８ 電
源端子、１４はトランジスタＱｓのゲート電極、】５は
トランジスタＱ２のゲート電極、１６はトランジスタＱ
！のドレイン電極、１７はトランジスタＱ２のドレイン
電極である。In FIG. 8, 1 is an N-type semiconductor substrate, 2 is an island% r, 3 is a P+ diffusion layer that becomes the source of the P-channel MOS transistor Q, 4 is a P diffusion layer that becomes the drain of the transistor Q, and 5 is an N 6 is an N+ diffusion layer that becomes the source of the channel MOS transistor Q, 6 is an N+ diffusion layer that becomes the drain of transistor Q2, 7 is an N+ diffusion layer for supplying VDD potential, 9 is an insulating layer, 10 is transistor Q
1 is the gate insulating layer, 11 is the gate insulating layer of the transistor Qz, 12 is the VDD power supply terminal, 13 is the V88 power supply terminal, 14 is the gate electrode of the transistor Qs, ]5 is the gate electrode of the transistor Q2, 16 is the transistor Q
! 17 is the drain electrode of the transistor Q2.
この０ＭＯ８−ＩＣの半導体滅域１〜８の部分は、破線
で示した等価回路で表わすことができる。すなわち、Ｑ
３は、６ｆｔエミツタ、２をベース、１をコレクタとす
るＮＰＮ トランジスタであ！０．Ｑ４は、 ５ｔ−エ
ミッタ、２をベース、１會コレクタとするＮＰＮトラン
ジスタである。また、Ｑｓｔｉ、３ｔ−エミッタ、１を
ベース、２をコレクタとするＰＮＰ）ランジスタであり
、Ｑ６は４′ｆ：エミッタ。The semiconductor areas 1 to 8 of this 0MO8-IC can be represented by an equivalent circuit shown by a broken line. That is, Q
3 is an NPN transistor with a 6ft emitter, 2 as a base, and 1 as a collector! 0. Q4 is an NPN transistor with 5T emitter, 2 base, and 1 collector. Also, Qsti is a 3t-emitter, a PNP (PNP) transistor with 1 as the base and 2 as the collector, and Q6 is 4'f: emitter.
１′？：ベース、２をコレクタとするＰＮＰ ）−ラン
ジスタである。Ｒ１はＮ−半導体基板内の電＃、ｙ＆子
ｖＤＤに至るまでの抵抗、Ｒ２はＰ−ｆｉアイランド内
の電源端子Ｖａ８に至るまでの抵抗である。1′? : A PNP transistor with base and collector 2. R1 is a resistance up to the voltage VDD in the N-semiconductor substrate, and R2 is a resistance up to the power supply terminal Va8 in the P-fi island.
第９図は第８図に破線で示した寄生素子が作る寄生回路
の回路図である。FIG. 9 is a circuit diagram of a parasitic circuit created by the parasitic elements shown in broken lines in FIG.
今、出力端子ＯＵＴに正のサージ電圧が印加されると、
トランジスタＱ６のベース、エミッタおよび抵抗Ｒ１を
通して出力端子ＯＵＴと電源端子ＶＤＤ間に電流が流れ
、これによりトランジスタＱ−が導通状態になプ、トラ
ンジスタＱ６のコレクタ電流は抵抗Ｒ２を通して電源端
子ＶＳＳに流れる。Now, when a positive surge voltage is applied to the output terminal OUT,
A current flows between the output terminal OUT and the power supply terminal VDD through the base and emitter of the transistor Q6 and the resistor R1, thereby turning on the transistor Q-, and the collector current of the transistor Q6 flows through the resistor R2 to the power supply terminal VSS.
この電流によｐトランジスタＱ４のベース・エミッタ間
が順バイアスされ、トランジスタＱ４が導通し、電流が
電源端子ＶＤＤから抵抗Ｒ１とトランジスタＱ４を通っ
て電源端子Ｖｌ１ｇへ流れる。これによって、更にトラ
ンジスタＱｓのエミッタ・ベース間が順バイアスされ、
トランジスタＱｉが導通し、トランジスタＱ４のベース
電流を供給するので、上述の出力端子ＯＵＴへのサージ
入力がな（なってもトランジスタＱｓとＱ４によるサイ
リスタ構成のために電源端子ＶＤＤ ｖｓｓ間に大き
な電流が流れ続け、素子を破壊に至らしめる。This current forward biases the base and emitter of the p-transistor Q4, making the transistor Q4 conductive, and the current flows from the power supply terminal VDD to the power supply terminal Vl1g through the resistor R1 and the transistor Q4. This further forward biases the emitter-base of the transistor Qs,
Since the transistor Qi is conductive and supplies the base current of the transistor Q4, there is no surge input to the output terminal OUT as described above. It continues to flow and destroys the element.
また、出力端子ＯＵＴに負のサージ電圧が印加された場
合には、電源端子Ｖｓｓから抵抗Ｒ２及びトランジスタ
Ｑｓのベース・エミッタを通して電流が流れ、トランジ
スタＱ、が導通状態になシ、トランジスタＱ３のコレク
タｌｌＩＣ流は抵抗Ｒｔを通して電源端子ＶＤＤから供
給される。この電流によシトランジスタＱｓのエミッタ
・ベース間が順バイアスされ、トランジスタＱｓが導通
し、電流が電源端子ＶＤＤからトランジスタＱｓ及び抵
抗ＵＺを通って電源端子ＶＢＩＣ流れる。これによって
更にトランジスタＱ４のベース・エミッタ間が順バイア
スされ、トランジスタＱ４が導通し、トランジスタＱｓ
のベース電流を引出すので、上述の出力サージ入力がな
くなりてもトランジスタＱｓとＱ４によるサイリスタ構
成のために電源端子ＶＤＤ−Ｖ８３間に大きな電流が流
れ続け、素子を破壊に至らしめることになる。Furthermore, when a negative surge voltage is applied to the output terminal OUT, a current flows from the power supply terminal Vss through the resistor R2 and the base/emitter of the transistor Qs, causing the transistor Q to become conductive and the collector of the transistor Q3 to become conductive. The llIC current is supplied from the power supply terminal VDD through the resistor Rt. This current forward biases the emitter and base of the transistor Qs, making the transistor Qs conductive, and current flows from the power supply terminal VDD through the transistor Qs and the resistor UZ to the power supply terminal VBIC. As a result, the base and emitter of transistor Q4 are further forward biased, transistor Q4 becomes conductive, and transistor Qs
Therefore, even if the above-mentioned output surge input disappears, a large current continues to flow between the power supply terminals VDD and V83 due to the thyristor configuration formed by the transistors Qs and Q4, leading to destruction of the device.
このように、従来の０ＭＯ８−ＩＣではラッチアップを
起すと素子が破壊されるという致命的欠陥があった。As described above, the conventional 0MO8-IC has a fatal defect in that the device is destroyed when latch-up occurs.
本発明の目的は、上記欠点を除去し、ラッチアップ耐量
の大きい半導体集積回路装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor integrated circuit device with high latch-up resistance.
（問題点を解決するための手段）
本発明の半導体集積回路装置は、Ｎ屋半導体領域内に形
成されたＰチャンネルＭＯＳトランジスタとＰｆｉ半導
体領域内に形成されたＮチャンネルＭＯＳトランジスタ
によシ構成された相補１ＭＯ８集積回路を含む半導体集
積回路装置において、電源端子と出力端子との間にシｌ
ットキーバリアダイオードを挿入したことを特徴として
構成される。(Means for Solving the Problems) A semiconductor integrated circuit device of the present invention includes a P-channel MOS transistor formed in the Nya semiconductor region and an N-channel MOS transistor formed in the Pfi semiconductor region. In a semiconductor integrated circuit device including a complementary 1MO8 integrated circuit, a shield is connected between the power supply terminal and the output terminal.
It is characterized by the insertion of a cut-key barrier diode.
（実施例） 次に１本発明の実施例について図面を用いて説明する。(Example) Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
この実施例は、ＰチャンネルＭＯＳトランジスタＱ、と
ＮチャンネルＭＯＳトランジスタＱ２とを有する相補１
１ＭＯ８集積回路において、電源端子ＶＤＤと出力端子
ＯＵＴとの間にシッットキーパリアダイオードＤ１を挿
入することにより構成されている。この実施例の論理動
作は第７図に示した従来の０ＭＯ８−ＩＣと全く同じで
ある。This embodiment is a complementary transistor having a P-channel MOS transistor Q and an N-channel MOS transistor Q2.
In a 1MO8 integrated circuit, a Schittky parier diode D1 is inserted between a power supply terminal VDD and an output terminal OUT. The logic operation of this embodiment is exactly the same as the conventional 0MO8-IC shown in FIG.
第２図は第１図に示した回路を半導体基板に実現した０
ＭＯ８−ＩＣの模式的断面図である。Figure 2 shows the circuit shown in Figure 1 realized on a semiconductor substrate.
FIG. 2 is a schematic cross-sectional view of MO8-IC.
絶縁層９の一部を窓あけし、アノード電極１８を形成し
て半導体基板１とでシ■ットキーバリアダイオードＤＩ
を形成する。このアノード電極１８を出力端子ＯＵＴ
に接続する。それ以外は第８図に示した従来例と同じで
ある。A window is formed in a part of the insulating layer 9, an anode electrode 18 is formed, and a Schottky barrier diode DI is formed with the semiconductor substrate 1.
form. This anode electrode 18 is connected to the output terminal OUT.
Connect to. The rest is the same as the conventional example shown in FIG.
第３図は第２図に示す０ＭＯ８−ＩＣにおける寄生素子
による寄生回路の回路図である。FIG. 3 is a circuit diagram of a parasitic circuit formed by parasitic elements in the 0MO8-IC shown in FIG. 2.
第３図を用いて第１の実施例の効果について説明する。The effects of the first embodiment will be explained using FIG. 3.
出力端子ＯＵＴに正のサージ電圧が印加された場合、出
力端子ＯＵＴと電源端子ＶＤＤとの間の電位差は、シｌ
ットキーバリアダイオードＤ１の順方向電圧にクランプ
される。このダイオードＤ１の順方向電圧をトランジス
タＱ６のエミッタ・ベース間順方向電圧よシ小さい値に
設定しておくことによりトランジスタＱ−が導通せず、
遮断状態のまま保たれ、これによりトランジスタＱｓ＝
Ｑ４及びＱｓ も遮断状態のまま保たれ、従来の０ＭＯ
８−ＩＣで見られたトランジスタＱ４とＱｓによるサイ
リスタ動作が起らないため、ラッチアップ現象も発生し
ない。When a positive surge voltage is applied to the output terminal OUT, the potential difference between the output terminal OUT and the power supply terminal VDD is
It is clamped to the forward voltage of the cut-key barrier diode D1. By setting the forward voltage of this diode D1 to a value smaller than the forward voltage between the emitter and base of the transistor Q6, the transistor Q- is not turned on.
remains in the cut-off state, which causes the transistor Qs=
Q4 and Qs are also kept in the cut-off state, and the conventional 0MO
Since the thyristor operation caused by the transistors Q4 and Qs seen in the 8-IC does not occur, the latch-up phenomenon does not occur either.
このように、出力端子ＯＵＴと電源端子ＶＤＤとの関に
シｌットキーバリアダイオードＤ１を挿入することｌこ
よシ、出力端子ＯＵＴに印加される正のサージ電圧に対
し、ラッチアップ耐量の大きい０ＭＯ８−ＩＣが実現で
きることがわかる。In this way, by inserting the Schittky barrier diode D1 between the output terminal OUT and the power supply terminal VDD, it is possible to use a 0MO8 diode with high latch-up resistance against the positive surge voltage applied to the output terminal OUT. - It can be seen that IC can be realized.
第４図は本発明の第２の実施例の回路図である。FIG. 4 is a circuit diagram of a second embodiment of the present invention.
出力端子ＯＵＴに正、負いずれのサージ電圧が印加され
た場合においても、ラッチアップ耐量の大きな０ＭＯ８
−ＩＣを実現したものである・第７図に示す従来例との
違いは、電源端子ＶＤＤと出力端子ＯＵＴとの間にシｌ
ットキーバリアダイオードＤ１が挿入されていることと
、出力端子ＯＵＴと電源端子ｖａｎとの間にシ目ットー
バリアダイオードＤ２が挿入されていることであ）、論
理動作は第７図の回路と全く同じである。0MO8 with high latch-up resistance even when either positive or negative surge voltage is applied to the output terminal OUT.
-The difference from the conventional example shown in Figure 7 is that there is a shield between the power supply terminal VDD and the output terminal OUT.
The logic operation is the same as the circuit shown in Figure 7. It's exactly the same.
Ｎ５図は′ｓ４図に示す回路を半導体基板に実現した０
ＭＯ８−ＩＣの模式的断面図である。Diagram N5 shows the circuit shown in diagram 's4 realized on a semiconductor substrate.
FIG. 2 is a schematic cross-sectional view of MO8-IC.
この０ＭＯ８−ＩＣは、電源端子ＶＤＤと出力端子ＯＵ
Ｔとの間に、１８をアノード電極とし、Ｎａ！１半導体
基板１をカソードとするシｌットキーバリアダイオード
Ｄ１が挿入されていること、及び出力端子ＯＵＴと電１
２＠端子ＶＳＳとの間に、１９ｔアノード！極とし、Ｎ
−拡散層２０ｔカソードとするシ曹ットキーバリアダイ
オードＤ２が挿入されていることを除いて第８図に示し
た従来例と全く同じである。This 0MO8-IC has a power supply terminal VDD and an output terminal OU.
18 as an anode electrode between Na! 1. A Schittky barrier diode D1 with the semiconductor substrate 1 as a cathode is inserted, and the output terminal OUT and the voltage 1 are connected.
2 @ 19t anode between terminal VSS! As a pole, N
- The diffusion layer 20t is exactly the same as the conventional example shown in FIG. 8, except that a silicon barrier diode D2 serving as a cathode is inserted.
ｗｉ６図は第５図に示す０ＭＯ８−ＩＣにおける寄生素
子による寄生回路図である。Figure wi6 is a parasitic circuit diagram of parasitic elements in the 0MO8-IC shown in Figure 5.
Ｎ６図を用いて第２の実施例の効果について説明する。The effects of the second embodiment will be explained using the N6 diagram.
出力端子ＯＵＴに正のサージ電圧が印加された場合のシ
讐ットーバリアダイオードＤ１の効果については、前述
した第１の実施例の場合と全く同 。The effect of the Shimetto barrier diode D1 when a positive surge voltage is applied to the output terminal OUT is exactly the same as in the first embodiment described above.
じてあり、ここでは、出力端子ＯＵＴに負のサージ電圧
が印加された場合についてのみ説明する。Here, only the case where a negative surge voltage is applied to the output terminal OUT will be explained.
出力端子ＯＵＴに負のサージ電圧が印加された場合、電
源端子Ｖｓｓと出力端子ＯＵＴとの間の電位差は、シ璽
ットキーバリアダイオードＤ２の頭方向電圧にクランプ
される。このダイオードＤ２の順方向電圧をトランジス
タＱ３のベース・エミッタ間順方向電圧より小さい値に
設定しておくことによりトランジスタＱ３が導通せず、
遮断状態のまま保たれ、これによりトランジスタＱ４．
Ｑ１１及びＱｓも遮断状態のまま保たれ、従来の０ＭＯ
８−ＩＣで見られたトランジスタＱ４とＱｓによるサイ
リスタ動作が起らないため、ラッチアップ現象も発生し
ない。When a negative surge voltage is applied to the output terminal OUT, the potential difference between the power supply terminal Vss and the output terminal OUT is clamped to the voltage in the head direction of the shutter key barrier diode D2. By setting the forward voltage of this diode D2 to a value smaller than the forward voltage between the base and emitter of the transistor Q3, the transistor Q3 is prevented from conducting.
remains cut off, thereby causing transistor Q4.
Q11 and Qs are also kept in the cut-off state, and the conventional 0MO
Since the thyristor operation caused by the transistors Q4 and Qs seen in the 8-IC does not occur, the latch-up phenomenon does not occur either.
このように、電源端子ＶＳＳと出力端子ＯＵＴとの間に
シ嘗ットキーバリアダイオードＤ２を挿入することにょ
）、出力端子ＯＵＴに印加される負のサージ電圧に対し
て、ラッチアップ耐量の大きい０ＭＯ８−ＩＣが実現で
き、前述のシ１ットキーバリアダイオードＤｌの効果と
併せると、正、負いずれのサージ電圧に対してもラッチ
アップ耐量の大きな０ＭＯ８−ＩＣが実現できることが
わかる。In this way, by inserting the shut-key barrier diode D2 between the power supply terminal VSS and the output terminal OUT), the 0MO8 which has a large latch-up resistance against the negative surge voltage applied to the output terminal OUT is inserted. -IC can be realized, and when combined with the effect of the above-mentioned shut-key barrier diode Dl, it can be seen that an 0MO8-IC with large latch-up resistance against both positive and negative surge voltages can be realized.
（発明の効果）
本発明は、以上説明したようｌこ０ＭＯ８−ＩＣにおい
て、電源端子ＶＤＤ−出力端子ＯＵＴ間、あるいは出力
端子０ＵＴ−電源端子Ｖｎｎ間に挿入したシ■ットキー
パリアダイオードの順方向電圧を小さく設定することに
ょシ、ラッチアップ現象の原因となる寄生バイポーラト
ランジスタの導通を防ぎ、ラッチアップ耐量の向上ｔ−
実現することができるという効果を有する。(Effects of the Invention) As explained above, the present invention provides a forward direction of the shut-key pariah diode inserted between the power supply terminal VDD and the output terminal OUT or between the output terminal 0UT and the power supply terminal Vnn in the 1 MO8-IC. Setting the voltage to a small value prevents conduction of the parasitic bipolar transistor, which causes latch-up, and improves latch-up resistance.
This has the effect that it can be realized.
第１図は本発明の第１の実施例の回路図、第２図は第１
図に示した回路を半導体基板に実現した０ＭＯ８−ＩＣ
の模式的断面図、第３図は第２図に示す０ＭＯ８−ＩＣ
における寄生素子による寄生回路の回路図、第４図は本
発明の第２の実施例の回路図、第５図は第４図に示した
回路を半導体基板に実現した０ＭＯ８−ＩＣの模式断面
図、第６廓は第５図に示す０ＭＯ８−ＩＣにおける寄生
素子による寄生回路の回路図、第７図は従来の０ＭＯ８
−ＩＣの一例の回路図、第８図は第７図に示す回路を半
導体基板に実現したときに生ずるラッチアップ現象を説
明するための模式的断面図、＠９図は第８図に示したＣ
ＭＯ５−ＩＣにおける寄生素子が作る寄生回路の回路図
である。
１・・・・・・Ｎｆｉ半導体基板、２・・・・−Ｐ−型
アイランド、３，４・・・・・・Ｐ＋拡散層、５，６．
７・・・・・・Ｎ＋拡散層、８ ・−−−−−Ｐ＋拡散
層、９，１０．ｌｌ・−−−−絶縁層、１２〜１９・・
・・・・電極、２ｏ・・・・・・Ｎ−拡散層、ＤｌｐＤ
ｘ・・・・・・シ１ットキーバリアダイオード。
ＩＮ・・・・・・入力端子、ＯＵＴ・・・・・・出方端
子、Ｑｌ・・・・・・ＰチャンネルＭＯ８トランジスタ
、Ｑｌ・・・・−・ＮチャンネルＭＯＳトランジスタ、
Ｑｌ−Ｑ４・・・・・・ＮＰＮ ）ランジスタ、Ｑｓ
、Ｑｓ ＝ ・” Ｐ Ｎ Ｐ ）ランジスタ、Ｒ１＃
Ｒ２”” ””抵抗、Ｖｎｎ ｅ Ｖｓ ｓ ＝ ＝
’ＭＥｆｉｌ端子。
ＶＤＪ） ＩＮ Ｏｕｒ Ｖ
ｓｓ第２図
ＶＤＤ ＯＵＴ
慢６図
ＶＤＤ ＩＮ ＯＵＴFIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
0MO8-IC that realizes the circuit shown in the figure on a semiconductor substrate
3 is a schematic cross-sectional view of the 0MO8-IC shown in FIG.
4 is a circuit diagram of a second embodiment of the present invention, and FIG. 5 is a schematic cross-sectional view of an 0MO8-IC in which the circuit shown in FIG. 4 is realized on a semiconductor substrate. , the sixth section is a circuit diagram of a parasitic circuit using parasitic elements in the 0MO8-IC shown in FIG. 5, and FIG. 7 is a circuit diagram of the conventional 0MO8-IC.
-A circuit diagram of an example of an IC, Figure 8 is a schematic cross-sectional view to explain the latch-up phenomenon that occurs when the circuit shown in Figure 7 is implemented on a semiconductor substrate, @ Figure 9 is shown in Figure 8. C
FIG. 2 is a circuit diagram of a parasitic circuit created by parasitic elements in MO5-IC. 1...Nfi semiconductor substrate, 2...-P- type island, 3, 4...P+ diffusion layer, 5, 6.
7...N+ diffusion layer, 8 ----P+ diffusion layer, 9, 10. ll・----insulating layer, 12-19...
...electrode, 2o...N-diffusion layer, DlpD
x...Shi1 key barrier diode. IN: input terminal, OUT: output terminal, Ql: P channel MO8 transistor, Ql: N channel MOS transistor,
Ql-Q4...NPN) transistor, Qs
, Qs = ・”PNP) transistor, R1#
R2”” ””Resistance, Vnn e Vs s = =
'MEfil terminal. VDJ) IN Our V
ss 2nd figure VDD OUT arrogant 6th figure VDD IN OUT
Claims (1)
ンジスタと、Ｐ型半導体領域内に形成されたＮチャンネ
ルＭＯＳトランジスタにより構成された相補型ＭＯＳ集
積回路を含む半導体集積回路装置において、電源端子と
出力端子との間にショットキーバリアダイオードを挿入
したことを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device including a complementary MOS integrated circuit configured with a P-channel MOS transistor formed in an N-type semiconductor region and an N-channel MOS transistor formed in the P-type semiconductor region, a power supply terminal and an output terminal A semiconductor integrated circuit device characterized in that a Schottky barrier diode is inserted between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60009436A JPS61168953A (en) | 1985-01-22 | 1985-01-22 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60009436A JPS61168953A (en) | 1985-01-22 | 1985-01-22 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168953A true JPS61168953A (en) | 1986-07-30 |
Family
ID=11720264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60009436A Pending JPS61168953A (en) | 1985-01-22 | 1985-01-22 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168953A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5639062A (en) * | 1979-09-08 | 1981-04-14 | Nippon Shinyaku Co Ltd | Slufenamide derivative |
| JPS5998552A (en) * | 1982-11-03 | 1984-06-06 | ウエスチングハウス エレクトリック コ−ポレ−ション | Field effect transistor |
-
1985
- 1985-01-22 JP JP60009436A patent/JPS61168953A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5639062A (en) * | 1979-09-08 | 1981-04-14 | Nippon Shinyaku Co Ltd | Slufenamide derivative |
| JPS5998552A (en) * | 1982-11-03 | 1984-06-06 | ウエスチングハウス エレクトリック コ−ポレ−ション | Field effect transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3386943B2 (en) | Semiconductor device | |
| JPH10340996A (en) | Protection circuit | |
| JP3184298B2 (en) | CMOS output circuit | |
| JPH02188028A (en) | Analog signal input circuit | |
| JPH08227991A (en) | Circuit that prevent conduction of parasitic element in integrated circuit | |
| JPS61168953A (en) | Semiconductor integrated circuit device | |
| JPH09102551A (en) | Semiconductor device | |
| JPH1079472A (en) | Semiconductor integrated circuit | |
| JP2805198B2 (en) | Power supply circuit and semiconductor integrated circuit device for the power supply circuit | |
| JP2914408B2 (en) | High voltage integrated circuit | |
| JPH0358620A (en) | Bimos semiconductor integrated circuit | |
| JPS5819137B2 (en) | Complementary MOS transistor | |
| JP2557534B2 (en) | Semiconductor integrated circuit device | |
| JPS61187265A (en) | Semiconductor integrated circuit device | |
| JP2821294B2 (en) | Latch-up prevention circuit | |
| JPS6048905B2 (en) | Semiconductor integrated circuit device | |
| JPS63316475A (en) | Input protective circuit | |
| US5543642A (en) | P-channel transistor | |
| JP2971666B2 (en) | Semiconductor circuit | |
| JP2979716B2 (en) | CMOS integrated circuit | |
| JP2755686B2 (en) | Semiconductor device protection circuit | |
| JP3437831B2 (en) | CMOS output circuit | |
| JPH09306999A (en) | Semiconductor device | |
| JPH04147666A (en) | Semiconductor integrated circuit | |
| JPH04330773A (en) | Semiconductor device |