JPS6048905B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention The present invention relates to a complementary field effect transistor (hereinafter referred to as CM
The present invention relates to a semiconductor integrated circuit device that eliminates the drawbacks caused by bipolar transistors parasitic to an OS (OS).

Various CMOS circuits have been known in the past, and the CMOS inverter circuit shown in FIG. 1 will be described as a typical example.

This inverter circuit is composed of a P-channel type MOS transistor Q1 and an N-channel type MOS transistor Q2, and the source electrode of the transistor Q is connected to the positive power supply VDD.
At the same time, the drain electrode of this Q1 is connected in common with the drain electrode of transistor Q2 to output W)
It is connected to UT, and the source electrode of transistor Q2 is connected to negative power supply Vss. Also, transistors Q,,Q. The gate electrodes of both are connected to the input terminal IN to form an inverter. FIG. 2 is a cross-sectional view of this circuit completed on a semiconductor wafer.

In this example, a so-called p-well layer 2 having a P-type impurity of about 2 x 10'' atoms/C77f is formed on an N-type substrate 1 having a concentration of about 1 x 10'' atoms/d. 2. P-type regions 3 and 4, which will become P-channel MOS transistors, are formed by diffusion in an external N-type substrate 1 to a concentration of, for example, about 10' atoms/d.

On the other hand, a P-type region that serves as a stopper for the N-channel MOS transistor is also provided inside the p-well layer 2.
In the L layer 2, N-type regions 5 and 6, which will become N-channel MOS transistors, are formed by diffusing N-type impurities to about 1 Patoms/d. After that, a thin silicon oxide film of approximately 1500A is provided at the position that will become the gate of each MOS transistor.
A necessary part is opened and a conductor Cli circuit such as N is connected. If necessary, a protective film is also provided on the substrate 1 to obtain a CMOS semiconductor element. This process description is brief and serves as an example only. The stopper is used for bias connection of the substrate electrode of each MOS transistor and is actually connected to the power supply VDD or V, but this stopper may be omitted. C with such a structure
Since the threshold voltages Vth of the N and P channel MOS transistors of the MOS circuit have opposite polarities, the MOS circuit operates completely oppositely to the input voltage, and its operating power is extremely small.

For example, if the power supply V,, is grounded (GND), the input I
If a +5V signal is supplied to N, transistor Q2 becomes conductive and transistor Q, becomes non-conductive, so power supply V,...
No direct current flows between -VDD. Conversely, when zero volts is applied to the input source, transistor Q2 is non-conducting;
Transistor Q becomes conductive, and similarly the power supply -V. ,−
No direct current will flow between VDD. Therefore, C
MOS circuits generally consume almost no operating power, and the transistors Q, , Q are used in the pulse transient region of input information. are conducting together and an instantaneous transient current flows, or P
Leakage occurring at the N junction; current only flows to charge and discharge the current and the load capacitance at the output end. Therefore, in general, the power of a CMOS circuit can be extremely small. However, even in such a CMOS circuit system, when impulse noise is added to the output or input, a large DC current (several + MA) is generated between the power supplies VSS and VDD.
~ several hundred MA) flows, and even after the noise disappears, a phenomenon is observed in which a large current continues to be maintained steadily.

3 This phenomenon is generally called a thyristor phenomenon or a latch-up phenomenon, and the polarity of the impulse noise is positive.
Both negative cases occur, and in order to eliminate this phenomenon, it is necessary to lower the power supply VDD below a certain voltage or to turn off the power supply 4r of the CMOS circuit system.

And if the CMOS circuit latches up,
The advantage of minimal power is completely lost, and on the other hand, thermal breakdown may occur, resulting in a significant decrease in the reliability of the circuit system. Furthermore, since the CMOS circuit structure is one in which thyristor effects can occur at all times, not only in the inverter circuit described above, it is necessary to take some measures against foreign nozzles in order to maintain good electrical characteristics. It was hot. The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit device that suppresses the occurrence of the thyristor phenomenon in a CMOS circuit system using a simple method.

Embodiments of the present invention will be described below with reference to the drawings.

The thyristor phenomenon in a CMOS circuit system is caused by the fact that a thyristor circuit as shown in FIG. 3 is constructed in a CMOS structure, for example, the inverter shown in FIG. The thyristor circuit shown in FIG. 3 includes parasitic bipolar transistors Tr2 and Tr4 in a P-well region 2 formed on an N-type semiconductor substrate 1 along the thickness direction of the substrate 1.
However, parasitic bipolar transistors Trl and T are formed in the substrate 1 outside the P-Well region in a direction perpendicular to the thickness direction.
r3 is formed, and the resistor T7! held by the P-Well region 2 and the substrate 1 is also formed. LRpwell,RNSUbl,RNS
Ub2 is formed. Then, as shown by the dashed-dotted line arrow in the figure, when positive impulse noise is added to the output 0UT,
A current of α3×Iin flows bypassing the Swell region, and the voltage drop is VBE. When I became a Tr. A current flows through the base of. Ib2ΣA3Iin(Rpwel
l>Rbe2) (1) Ic2β212=β2 α3I
in(2) where 2 and IC2 are the base and collector currents of the transistor Tr2, and α1, α2, α3, and α4 are the transistors Tr, Tr.

, Tr. , Tr, current amplification factor, βn = -color L (n is 1
~4), Iin is an impulse-like noise 1-αns current.

Similarly, Ic2 becomes the drive current and RN. U. When the voltage drop between the two terminals becomes VBE, the transistor Tr
The base current Ibl of 1 flows and becomes conductive.

11) 1:IC2(RNSUb2≧Rbel)) (3
)Icl=βIlbi=β1β2α3Iin (4) In order for the current to be maintained between the power supply VDD and GND, that is, between Tr, Tr2 even if the following external noise is removed, 11
), ≦Ic, as long as the condition is satisfied.

This is therefore expressed by the following equation. α, Iinkuβ,
β. α. Hin(5) β1β2≧1 (6) When β1β2>1 holds true, the transistors Tr,,Tr.

In the loop circuit, the base current Ib'' in the next cycle is larger than the base current L' in one cycle, so by repeating L cycles, the current flowing through the CMOS circuit system increases.And β, . When this current reaches a steady state determined by β2, the thyristor circuit is latched up.Figure 4a shows an example of a CMOS circuit according to the invention.

This is a step of forming an inverter circuit similar to that shown in FIG. A P type semiconductor region 14 and a P type semiconductor region 15 are formed outside the region 13, respectively. That is, output terminal 0UT and power supply terminals VDD, V, . Between the vertical transistor Trv and the lateral transistor T,
The noise absorbing circuit is constructed by positively inserting the transistors L to prevent the thyristor phenomenon in the thyristor circuit caused by the above-mentioned parasitically formed transistors Trl to Tr4. When providing a noise absorption circuit in this way, the P-well region 13 is a CMOS (
7) A P゛ type semiconductor region 16 which is formed separately from the region 12 forming the N-channel type MOS transistor Q2 and serves as a stopper region is formed around it in order to minimize the sheet resistance here. N type substrate 11
In order to minimize the sheet resistance of the N-type semiconductor region 1
7 is provided as a stopper area. FIG. 4b is an equivalent circuit diagram of FIG. It is. In this embodiment of the present invention in which a noise absorption circuit is provided for the output terminal 0UT and the output signal is taken out to the outside by relaying this noise absorption circuit, the noise generated by the external nozzle or internal operation is It is processed and absorbed in various ways.
That is, for positive impulse noise, the base electrode of transistor TrV is equal to VDD, and its on
'(The condition is VB≧VDD+VBE, so VDD=
+3v and VBE=0.7v, the lateral transistors T and L are turned on by noise of +3.7 volts or more. Therefore, noise above +3.7 volts is
It is not transmitted to the inside of the OS circuit system, but is absorbed by the power supply Vss (ground) via the transistor TL, and the parasitic transistor T
Since ra remains off, the thyristor circuit will not latch up. In addition, for negative impulse noise, the base electrode of the transistor T,v is equal to Vs, and its ON condition is VB≧VBE, and VDD=
If +3V and VBE=0.7v, noise above -0.7 volts turns on the above-mentioned partical transistors T and v.

Therefore, negative noise with a magnitude of 0.7 volts or more is
The transistor Trv is not transmitted to the inside of the CMOS circuit system.
is absorbed into the power supply VDD via the parasitic transistor Tr.
. will remain off, so the thyristor circuit will not latch up. In this way, in the above embodiment, similar bipolar transistors are used to configure the thyristor circuit to prevent latch-up in the CMOS circuit system.

On the one hand, in order to prevent latch-up in the CMOS circuit system, the effect of parasitic transistors is suppressed, and this has been effective to some extent. This indicates that the above bipolar transistor is actively utilized. Further, the structure of the noise absorption circuit using transistors is extremely simple, and it is also possible to enhance the noise absorption effect by using it in combination with a diode or a resistor.
Note that this invention is not limited to the above embodiments,
It can be applied to various CMOS circuits in which a suffix resistor circuit is formed other than the inverter circuit shown in FIG.
The MOS structure may also be a P-type semiconductor substrate with an N-well region, or may be a silicon gate CMOS.

As described above, according to the present invention, a noise absorbing circuit using a transistor is provided for the noise that causes the thyristor phenomenon in the CMOS circuit 5 system, so that the semiconductor integrated circuit device can reduce power consumption and improve circuit characteristics. can be provided.

[Brief explanation of the drawing]

o Fig. 1 is an inverter circuit diagram showing an example of a CMOS circuit system, Fig. 2 is a side sectional view showing the structure of a CMOS semiconductor element, Fig. 3 is a circuit configuration diagram showing a thyristor circuit formed parasitically, and Fig. Figures 4a to 4c are explanatory diagrams showing one embodiment of the present invention. 1...N-type semiconductor substrate, 12...P
-Well territory Trv. ．． ．． ．．・．． Particle transistor, TrL. ．． ．． ．． ．． ．． Lateral transistor.

Claims (1)

[Claims] 1 A semiconductor region of the opposite conductivity type is formed on a semiconductor substrate, MOS transistors of different channel types are formed inside and outside this semiconductor region, and these are formed parasitically by forming the MOS transistors. A semiconductor integrated circuit device in which a thyristor circuit is constituted by transistors, comprising: a vertical transistor provided between one of the power supplies and an output terminal of the semiconductor integrated circuit device, the base of which is connected to the other of the power supplies; A semiconductor integrated circuit device comprising a noise absorbing circuit comprising a lateral transistor provided between a terminal and the other of the power supplies, the base of which is connected to one of the power supplies.