JPS61168724U

JPS61168724U -

Info

Publication number: JPS61168724U
Application number: JP5186185U
Authority: JP
Priority date: 1985-04-08
Filing date: 1985-04-08
Publication date: 1986-10-20

Description

[Brief explanation of the drawing]

第１図ａ，ｂはそれぞれ本考案の第１、第２の
実施例を示す回路ブロツク図、第２図は第１図ａ
，ｂにおける動作を説明するための波形図、第３
図ａ，ｂはそれぞれ第１図ｂにおける第１、第２
の具体例を示す回路図、第４図は従来の逓倍回路
の一例を示す回路ブロツク図、第５図は第４図に
おける動作を説明するための波形図である。１……入力端子、２……中間端子、３……カツ
プリングコンデンサＣ、４，５……トランジスタ
Ｑ、６，７ａ，７ｂ，７ｃ，７ｆ，７ｇ，７ｊ，
８ａ，１３ａ，１３ｃ……抵抗、７……エミツタ
バイアス回路、７ｈ，７ｉ，８ｃ，１３ｄ……ダ
イオード、８，４０，４１……インバータ、８ｂ
……ＰＮＰトランジスタ、９……出力端子、１３
……負荷、１３ｂ……ＮＰＮトランジスタ、１４
……電源、４２……ＥＸ―ＯＲ回路。 Figures 1a and 1b are circuit block diagrams showing the first and second embodiments of the present invention, respectively, and Figure 2 is the same as Figure 1a.
, waveform diagram for explaining the operation in b, third waveform diagram.
Figures a and b are the first and second positions in Figure 1b, respectively.
4 is a circuit block diagram showing an example of a conventional multiplier circuit, and FIG. 5 is a waveform diagram for explaining the operation in FIG. 4. 1...Input terminal, 2...Intermediate terminal, 3...Coupling capacitor C, 4, 5...Transistor Q, 6, 7a, 7b, 7c, 7f, 7g, 7j,
8a, 13a, 13c...Resistor, 7...Emitter bias circuit, 7h, 7i, 8c, 13d...Diode, 8, 40, 41...Inverter, 8b
...PNP transistor, 9...Output terminal, 13
...Load, 13b...NPN transistor, 14
...Power supply, 42...EX-OR circuit.

Claims

[Scope of utility model registration request]

first and second transistors having complementary polarity characteristics, each having a rectangular wave signal inputted to its base via a coupling capacitor; the emitters of the first and second transistors connected to each other; a resistor connected to the base, a bias circuit that biases the emitter, and a polarity inversion circuit that provides an input to the collector of the first transistor, the second transistor connected to the polarity inversion circuit; A multiplier circuit characterized by obtaining an output from the collector of a transistor.