JPS61168063A - Data input-output device - Google Patents
Data input-output deviceInfo
- Publication number
- JPS61168063A JPS61168063A JP936585A JP936585A JPS61168063A JP S61168063 A JPS61168063 A JP S61168063A JP 936585 A JP936585 A JP 936585A JP 936585 A JP936585 A JP 936585A JP S61168063 A JPS61168063 A JP S61168063A
- Authority
- JP
- Japan
- Prior art keywords
- information
- input
- central processing
- output
- processing means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Input From Keyboards Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は中央処理装置の制御に基づいて動作する周辺装
置にデータを入出力するデータ入出力装置の改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a data input/output device that inputs and outputs data to a peripheral device that operates under the control of a central processing unit.
この種の従来装置として第2図に示すものがあり、同図
において従来のデータ入出力装置は、周辺装置の動作に
必要な演算処理を行なう演算処理部(11)及び該演算
処理部(11)の演算処理に基づき周辺装置に供給され
るカード情報を格納するアドレスRAM(12)を備え
る中央処理手段(1)と、該中央処理子l13)(1)
のアドレスRAM(12)に格納されたユニットナンバ
ー、スロットナンバー及ヒ■70点数等からなるカード
情報ガ送出される入出カニニット(2)、(2)と、該
入出カニニット(2)、(2)及び中央処理手段(1)
を接続するバス(3)とを備えて構成される。A conventional device of this kind is shown in FIG. 2, in which the conventional data input/output device includes a calculation processing section (11) that performs calculation processing necessary for the operation of peripheral devices; ); a central processing means (1) comprising an address RAM (12) for storing card information supplied to a peripheral device based on the arithmetic processing of the central processor (1);
The card information including the unit number, slot number, and 70 points stored in the address RAM (12) of the input/output crab unit (2), (2) is sent, and central processing means (1)
and a bus (3) for connecting.
次に上記従来装置の動作について説明する。まず、電源
が投入されると、中央処理手段(1)は演算処理部(1
1)の処理動作に基づき各入出カニニット(2)、(2
)よりカード情報を読出し、該読出されたカード情報の
内容をアドレスRAM(12)に自己の使用言語にて格
納する。Next, the operation of the above-mentioned conventional device will be explained. First, when the power is turned on, the central processing means (1) operates the arithmetic processing section (1).
Based on the processing operation of 1), each input/output crab unit (2), (2
) and stores the contents of the read card information in the address RAM (12) in the own language.
さらに、中央処理手段(1)がアドレスRAM(12)
に格納された情報を送出する場合は、演算処理部(11
)よりアドレスRAM(12)に指令を送り、この指令
を上記アドレスRAM(12)にて実体アドレスに変換
して指定の入出カニニット(2)に情報を送出し、この
情報に基づき指定の入出カニニット(2)を動作させる
こととなる。Further, the central processing means (1) has an address RAM (12).
When sending out the information stored in the arithmetic processing unit (11
) sends a command to the address RAM (12), converts this command into an actual address in the address RAM (12), sends information to the designated input/output crab unit (2), and based on this information, the designated input/output crab unit (2) will be operated.
従来のデータ入出力装置は以上のように中央処理手段(
りに各入出力二二ッ) (2)、(2)のカード情報を
格納するアドレスRAMを設ける必要があり、中央処理
手段(1)の製作費が高くなり、構造自体も複雑化する
という欠点を有していた。Conventional data input/output devices utilize central processing means (
It is necessary to provide an address RAM for storing the card information (2) and (2) for each input/output (2), which increases the production cost of the central processing means (1) and makes the structure itself complicated. It had drawbacks.
本発明は上記点に鑑みてなされたもので、中央処理手段
が自己の使用言語で各入出カニニットへの指令を行ない
得、中央処理手段の製作費を低減し延いては安価なデー
タ入出力装置を得ることを′目的とする。The present invention has been made in view of the above points, and allows the central processing means to issue instructions to each input/output unit in its own language, thereby reducing the manufacturing cost of the central processing means and resulting in an inexpensive data input/output device. The purpose is to obtain.
本発明に係るデータ入出力装置は、周辺装置の動作に必
要な演算処理を行なう中央処理手段と、該中央処理手段
と周辺装置の間にあって、E記周辺装置の情報を格納す
ると共に上記中央処理手段から送出される情報が自己の
情報か否かを判断して該当する情報を入出力する入出力
手段と、上記中央処理手段と入出力手段との間を接続す
るバスとを備えて構成されるものである。The data input/output device according to the present invention includes a central processing means that performs arithmetic processing necessary for the operation of a peripheral device, and is located between the central processing means and the peripheral device, and stores information on the peripheral device E. The computer is configured to include an input/output device that determines whether the information sent from the device is its own information and inputs and outputs the relevant information, and a bus that connects the central processing device and the input/output device. It is something that
本発明においては、中央処理手段が各入出カニニットか
らカード情報を読出し、このカード情報の内容を該当す
る入出カニニットのデータ記憶部に格納し、上記中央処
理手段より各入出カニニットに情報を送出した場合に該
当する入出カニニットが自分への情報か否かをデータ判
断部で判断しテ入出カニニットが動作する。In the present invention, when the central processing means reads card information from each input/output crab unit, stores the contents of this card information in the data storage section of the corresponding input/output crab unit, and sends the information from the central processing unit to each input/output crab unit. The data judgment unit determines whether the input/output crab unit that corresponds to is information for the user, and the input/output crab unit operates.
以下、本発明の一実施例を第1図に基づいて説明する。 An embodiment of the present invention will be described below with reference to FIG.
第1図に本実施例に係るデータ入出力装置の全体回路ブ
ロック図を示し、同図において本実施例は1周辺装置(
図示を省略する)の動作に必要な演算処理を行なう中央
処理手段(1)と、該中央処理手段(1)と周辺装置の
間にあって、上記中央処理手段(1)にて読取られたカ
ード情報の内容を中央処理手段(1)の使用言語で格納
するデータ記憶部(21)及び該データ記憶部(21)
に格納されたデータと上記中央処理手段(1)から送出
される情報とを比較して自己の情報か否かを判別するデ
ータ判断部(22)を有し、上記データ判断部(22)
の判断結果に基づいて動作する入出カニニット(2)、
(2)と、該り記中央処理手段(りと入出カニニット(
2)、(2)との間を接続するバス(3)とを備えて構
成される。FIG. 1 shows an overall circuit block diagram of a data input/output device according to this embodiment, and in the same figure, one peripheral device (
A central processing means (1) that performs the arithmetic processing necessary for the operation of (not shown), and card information that is located between the central processing means (1) and peripheral devices and read by the central processing means (1). a data storage unit (21) for storing the contents of in the language used by the central processing means (1);
and a data judgment unit (22) that compares the data stored in the central processing means (1) with the information sent out from the central processing means (1) to determine whether or not it is own information, and the data judgment unit (22)
Input/output crab unit (2) that operates based on the judgment result of
(2) and the central processing means (rito input/output crab unit)
2), and a bus (3) connecting between the two.
上記カード情報は、中央処理手段(1)にて各入出カニ
ニット(2)、(2)より読出されるユニットナンバー
、スロットナンバー、 I10点数等からなるものであ
る。The card information includes the unit number, slot number, I10 score, etc. read out from each input/output crab unit (2) by the central processing means (1).
上記データ記憶部(22)は例えばTTLやECLもし
くはCMO9等のゲートアレイにより構成される。なお
、このデータ記憶部(22)は、上記ゲートアレイに限
定されず他の記憶手段により構成することもできる。The data storage section (22) is constituted by, for example, a gate array such as TTL, ECL, or CMO9. Note that this data storage section (22) is not limited to the gate array described above, but can also be configured by other storage means.
次に本実施例に係るデータ入出力装置の動作について説
明する。Next, the operation of the data input/output device according to this embodiment will be explained.
まず、電源が投入される場合には、中央処理手段(1)
は各入出カニニー/ ) (2)、(2)によりカード
情報を読出し、このカード情報の内容を中央処理手段(
1)の演算処理動作に基づき中央処理f・段(1)の使
用言語による情報が各入出力ユニッ) (2)、(2)
に送出される。この各入出カニニット(2)、(2)は
送出される情報の内自己の情報をデータ記憶部(21)
に格納する。First, when the power is turned on, the central processing means (1)
reads the card information according to (2) and (2), and the content of this card information is sent to the central processing means (
Based on the arithmetic processing operations in (1), information in the language used by the central processing stage (1) is transmitted to each input/output unit) (2), (2)
will be sent to. Each input/output crab unit (2), (2) stores its own information among the sent information to the data storage unit (21).
Store in.
上記電源投入後中央処理手段(1)から入出カニニット
(2)、(2)に情報が送出された場合には、各入出力
二二ッ) (2)、(2)は送出された情報が自己の情
報か否かをデータ判断部(22)で判断し、自己の情報
と判断したときには送出された情報に基づいて動作を開
始することとなる。If information is sent from the central processing means (1) to the input/output crab units (2), (2) after the power is turned on, each input/output unit (2) (2), (2) The data determining unit (22) determines whether or not the information is one's own, and when it is determined that the information is one's own, an operation is started based on the sent information.
本発明に係るデータ入出力装置は各入出カニニット(2
)、(2)が中央処理手段(1)の使用言語で情報を格
納し、中央処理手段(1)からの情報を各入出カニニッ
ト(2)、(2)自体が各々の情報か否かを判断して動
作することから、上記中央処理手段(1)内に周辺装置
のカード情報を記憶する記憶手段としてのアドレスRA
Mを設ける必要がなくなる。The data input/output device according to the present invention includes each input/output crab unit (2
), (2) store information in the language used by the central processing means (1), and each input/output unit (2), (2) itself uses the information from the central processing means (1) to determine whether or not it is the respective information. Address RA serves as a storage means for storing card information of peripheral devices in the central processing means (1) because it operates based on judgment.
There is no need to provide M.
なお、上記各入出力ユニッ) (2)、(2)内にデー
タ記憶部(21)を別途設ける必要が新たに生じたが、
このデータ記憶部(21)がゲートアレイにて構成でき
ることから、入出力装置全体としてみれば安価に製作す
ることができることとなる。In addition, it has become necessary to separately provide a data storage section (21) in each of the above input/output units (2) and (2).
Since this data storage section (21) can be configured with a gate array, the input/output device as a whole can be manufactured at low cost.
以上説明した通り1本発明は周辺装置の動作に必要な演
算処理を行なう中央処理手段と、該中央処理手段と周辺
装置の間にあって、上記周辺装置の情報を格納すると共
に上記中央処理手段から送出される情報が自己の情報か
否かを判断して該当する情報を入出力する入出力手段と
、上記中央処理手段と入出力手段との間を接続するバス
とを備える構成を採ったことから、上記中央処理手段内
で周辺装置の情報を記憶せず、中央処理手段が自己の使
用言語で直接に各入出力手段に指令を行ない、該指令を
各入出力手段が自己への情報か否かを判断できることと
なり、中央処理手段の製作費を低減し延いては安価なデ
ータ入出力装置を得る効果を奏する。As explained above, the present invention includes a central processing means that performs arithmetic processing necessary for the operation of a peripheral device, and is located between the central processing means and the peripheral device, and stores information of the peripheral device and transmits information from the central processing means. This is because the system is configured to include an input/output means that determines whether the information received is own information and inputs/outputs the relevant information, and a bus that connects the central processing means and the input/output means. , the central processing means does not store information on peripheral devices within the central processing means, and directly issues commands to each input/output means in its own language, and each input/output means transmits the commands to each input/output means as to whether or not the information is for itself. This has the effect of reducing the manufacturing cost of the central processing means and, by extension, obtaining an inexpensive data input/output device.
第1図は本発明の一実施例に係るデータ入出力装置の全
体回路ブロック図、第2図は従来のデータ入出力装置の
全体回路ブロック図を示す。
(1)・・・中央処理り段、(2)・・・入出カニニッ
ト、(3)・・・バス、 (12)・・・アド
レスRAM、(21)・・・データ記憶部、(22)・
・・データ判断部。FIG. 1 shows an overall circuit block diagram of a data input/output device according to an embodiment of the present invention, and FIG. 2 shows an overall circuit block diagram of a conventional data input/output device. (1)... Central processing stage, (2)... Input/output crab unit, (3)... Bus, (12)... Address RAM, (21)... Data storage unit, (22)・
...Data judgment department.
Claims (2)
理手段と、該中央処理手段と周辺装置の間にあって、上
記周辺装置の情報を格納すると共に上記中央処理手段か
ら送出される情報が自己の情報か否かを判断して該当す
る情報を入出力する入出力手段と、上記中央処理手段と
入出力手段との間を接続するバスとを備えて構成される
ことを特徴とするデータ入出力装置。(1) A central processing means that performs the arithmetic processing necessary for the operation of the peripheral device, and a central processing means that is located between the central processing means and the peripheral device, and stores information on the peripheral device and stores information sent from the central processing means. The data input device is characterized in that the data input device comprises an input/output means for inputting/outputting the information by determining whether the information is the same or not, and a bus for connecting the central processing means and the input/output means. Output device.
ード情報の内容を中央処理手段の使用言語で格納するデ
ータ記憶部と、該データ記憶部に格納されたデータと上
記中央処理手段から入出力手段に送出される情報とを比
較して自己の情報か否か判断するデータ判断部とを備え
、上記データ判断部の判断結果に基づいて動作する構成
としたことを特徴とする特許請求の範囲第1項記載のデ
ータ入出力装置。(2) The input/output means includes a data storage unit that stores the contents of the card information read by the central processing unit in the language used by the central processing unit, and the data stored in the data storage unit and the central processing unit. A patent claim characterized in that the data determining section compares the information sent to the input/output means and determines whether the information is own information or not, and operates based on the determination result of the data determining section. The data input/output device according to item 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP936585A JPS61168063A (en) | 1985-01-22 | 1985-01-22 | Data input-output device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP936585A JPS61168063A (en) | 1985-01-22 | 1985-01-22 | Data input-output device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61168063A true JPS61168063A (en) | 1986-07-29 |
Family
ID=11718448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP936585A Pending JPS61168063A (en) | 1985-01-22 | 1985-01-22 | Data input-output device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61168063A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55118120A (en) * | 1979-03-02 | 1980-09-10 | Fuji Electric Co Ltd | Setting system for type-based information of input/output card |
JPS58106932A (en) * | 1981-12-18 | 1983-06-25 | Ricoh Co Ltd | Terminal machine recognizing device |
-
1985
- 1985-01-22 JP JP936585A patent/JPS61168063A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55118120A (en) * | 1979-03-02 | 1980-09-10 | Fuji Electric Co Ltd | Setting system for type-based information of input/output card |
JPS58106932A (en) * | 1981-12-18 | 1983-06-25 | Ricoh Co Ltd | Terminal machine recognizing device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2766216B2 (en) | Information processing device | |
JPS61168063A (en) | Data input-output device | |
JPH02500692A (en) | Integration of computational elements in multiprocessor computers | |
JPS5864528A (en) | Data transfer system of plural microprocessors | |
NL8301669A (en) | MICROCOMPUTER SYSTEM WITH TWO CENTRAL PROCESSING UNITS. | |
JPH0114616B2 (en) | ||
JPS62217350A (en) | Bus control system | |
JP2632331B2 (en) | Character display device | |
JPS642971B2 (en) | ||
JP2870200B2 (en) | Data processing device | |
JPS6379161A (en) | Semiconductor memory device | |
JPS61151745A (en) | Interruption processing system | |
JPH05189382A (en) | Communication method between processors | |
JPS57139833A (en) | Interruption controlling circuit | |
JPS59147236U (en) | Interface control device | |
JPH01209560A (en) | Human interface controller | |
JPH04100103A (en) | Mechanism controller | |
JPS63127361A (en) | Data processor | |
KR880014450A (en) | Real-time data input / output device | |
JPH0452250U (en) | ||
JPS58101322A (en) | Data transfer controlling circuit | |
JPH01162316U (en) | ||
JPH01102944U (en) | ||
JPS6394362A (en) | Bus coupling device | |
JPH04312154A (en) | Terminal equipment |