JPS61167244A - Communication control equipment - Google Patents

Abstract

PURPOSE:To ensure frame synchronization by judging it as starting of the frame when the outputs from two detecting circuits are obtained simultaneously. CONSTITUTION:The + side and - side of AMI code on a bus 1 are received separately using a transformer 17 of a receiving circuit 4 and comparators 22, 23 and signals 39, 40 are outputted. This is converted to a receiving signal 11 of RZ code in a code converting circuit 7 and transmitted to each section. A pattern detecting circuit 7 detects a pattern from the receiving signal 11 and clock 41 and outputs a detection signal 12. On the other hand, a violation detecting circuit 8 detects violation from signals 39, 40 and a clock signal 41 and outputs a detection signal 13. A signal 14 is outputted in a state supervisory circuit 9 when detection signals 12, 13 are outputted simultaneously, and a communication controlling circuit 10 judges it as frame starting. When only detection signal 13 from the detecting circuit 8 is outputted, it is judged as occurrence of an error in transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a communication control device, and particularly to a method suitable for ensuring frame synchronization. .

[Background of the invention]

HDLC is one of the typical transmission methods.

(High Level Data Link Con
Trol ) method is available. This has become an international standard and is also specified in JIS.

The details are given in J.I.8-C6565.

It is. In this HDLC method, the frame is open.

The beginning and end are the same, called a flag sequence.

° Determined by period code. This is “01111□
(.

110'' using a specific pattern of flags.

The start of a frame by detecting a specific pattern of.

Or it determines the end. but,.

Simply this is not enough for the data part that follows the flag.

Since any pattern can be taken, there is a possibility that a pattern matching the flag may occur in the 1° portion of the data by chance. Therefore, in order to prevent such a phenomenon, a method called zero insert is used in the HDLC system. This means that the data part other than the flag is set to "1" during transmission.
If there are 5 consecutive bits, a zero value is inserted into the input at the 6th bit, and the flag pattern is the same.

- This is to prevent the -n from appearing. Then, on the receiving side, the zero inserted on the sending side is removed (
(zero remove), the correct data is received.

Now, like in this HDLC system, the start of a frame is flagged with a specific pattern (i.e., synchronization).

code) on the data.

It is necessary to take measures to prevent the same pattern from occurring. This not only complicates the control circuit, but in the case of methods such as zero insert, the frame length becomes variable depending on the data content due to the insertion of bits that have no meaning as data. Transmission efficiency will decrease.

[Purpose of the invention]

An object of the present invention is to provide a communication control device that can reliably detect the start of a frame without reducing transmission efficiency.

[Summary of the invention]

The key point of the present invention is to use code conversion rules as synchronization codes.

Contains bits or bit strings that violate the rules.

If the signal is received using a predetermined specific bit pattern 1, it violates the detection circuit for detecting the specific bit pattern 5 and the code conversion rules.

A detection circuit that detects a bit or bit string.

, and the outputs from these two detection circuits are simultaneous.

It is determined that the start of the frame is obtained.

There it is.　 　 　 　 　 　 　 　 　 　

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail based on examples.

Ru. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a transmission line (bus) that transmits signals, 2
5 is a transmitting circuit; 4 is a receiving circuit; and 5 converts the received transmission code into N RZ (Non ELtttLrn t).

Zero) code and RZ (Rgtu, rn, to
6 is a clock control circuit that generates various clocks from the received signal;
7 is.

The same beep as the predetermined synchronization code.

Bata detects the code pattern from the received signal.

- tone detection circuit, 8 is a predetermined mark.

A bit or bit string that violates the code conversion rules.

(This is considered a violation).

9 is a pattern detection circuit 7.
A status monitoring circuit 10 monitors the transmission status such as the start of a frame and transmission errors by using the output signals from the violation detection circuit 8;

11 is a signal line that sends the received signal converted into an NRZ code etc. to the communication control circuit 10; 12 is an output signal line from the pattern detection circuit 7, which detects the same bit pattern as the synchronization code; A signal is output when 15 is an output signal line from the violation detection circuit, 14 and 15
14 is an output signal line from the status monitoring circuit, 14 is a signal line that sends a frame synchronization signal indicating the start of a frame, and 15
16 is a signal line for transmitting a transmission error detection signal, for example, and the communication control circuit 10 is a bus.

Transmits a transmission signal to be transmitted to another device through 1.

This is the transmission signal line.

Explain the operation.

First, when transmitting a signal on bus 1, for example, only data in synchronization with a synchronization code on bus 1.

tx, from the communication control circuit 10.

The transmitted signal is converted by the code conversion circuit 2.

The data is code-converted 1 according to predetermined code conversion rules, and then transmitted onto the bus 1 via the transmission circuit 3. 1 again.

When data is sent on bus 1 along with a synchronization code.

In this case, the synchronization code is converted by the code conversion circuit 2.

When converting the code, part or all of the synchronization code is subjected to an operation that violates predetermined code conversion rules, that is, a violation, and then transmitted onto the bus 1. Next, the reception operation will be explained. The signal transmitted on the bus 1 is converted into a reception signal such as an NRZ code through a reception circuit 4 and a code conversion circuit 5, and is sent to a communication control circuit 10 through a signal line 11. At the same time, the pattern detection circuit 7 detects a pattern identical to a predetermined synchronization code from the received signal and sends it to the status monitoring circuit 9 through the signal line 12.

Also, biolage.

The Yon detection circuit 8 detects bits or bit strings that violate predetermined code conversion rules, and
The signal is sent to the status monitoring circuit 9 through.

In the status monitoring circuit 9, signals are sent to signal lines 12 and 16.

is monitored, and if both occur at the same time, that is the start of the frame. Furthermore, if the detection signal from the pattern detection circuit 7 is not output to the signal line 12 even though the detection signal from the violation detection circuit 8 is output to the signal line 15, a transmission error occurs. shall be taken as a thing.

The respective signals are then sent to the communication control circuit 10 through signal lines 14 and 15.

Next, regarding the reception circuit 4, code conversion circuit 5, pattern detection circuit 7, violation detection circuit 8, and status monitoring circuit 9, the code on the bus 1 is an AMI code (Altgrn
A specific example of a circuit using the Mark Inversion will be described in detail.

Figure 2 shows a concrete example of the circuit, and Figure 3 shows its operation.

FIG. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals.

17 is a transformer, 18-21 are resistors, 22 and 23
teeth.

Voltage comparator (comparator), 24 is OR gate, 25
is a shift register (for example, Hitachi IC, H8D74
LS164), 26 is an AND gate, 27 and 28° are inverter gates, and 29 to 34 are D-type bistable circuits.

vibrator (e.g. Hitachi IC-HD74°L87
4A), 35 is an OR gate, 36 is a NOR gate.

- gate, 67 is an inverter gate, 68 is an AND gate,
39 is a signal line that transmits a signal received only on the + side of the AMI code on bus 1, 4o is a signal line that transmits a signal received only on one side, and 41 is a clock synchronized with the signal on bus 1. This is a clock signal line that sends signals. Figure 3 is the second
2 is a timing diagram for explaining the operation shown in the figure, where the symbols in 0 correspond to the symbols in FIG. 2 and indicate the signal waveforms on the corresponding signal lines.

Explain the operation.

First, here, the synchronization code is shown in FIG. 5 (1).

A bit butter called "01110111".

Then add bio-region to the 8th bit.

The code shall be an AMI code with The AMI code is the signal “1
" is a five-value code that follows the code rule that "1" appears alternately on the + side and - side. In this case, a violation means that "1" appears consecutively on the + side or - side. Therefore, Tong.

When errors occur due to normal data transmission.

often appears as a violation. 1. Now, as for the method of detecting such a synchronization code using a circuit as shown in FIG.
AM of bus 1 using comparators 22 and 26.
The + side and - side of the I code are received separately, and the
), outputs the signal shown in (40). Code conversion circuit 5
Then, the OR gate 24 converts the RZ code received signal (1
1) and transmit it to each part. Pattern detection circuit 7
Then, from the received signal (11) and clock signal (41),
Shift register 25 and inverter f-), 27.28
rolllollJ by yohi AND agate 6
Detects the pattern and outputs a detection signal (12). - On the other hand, in the pie ray scene detection circuit 8, the + side is determined from the signals (39) and (40) and the clock signal (41).

Violence is a violet with consecutive signal "1" on the - side.

- detect the motion and output the detection signal (13).

Ru. In the condition monitoring circuit 9, the detection signals (12) and (13)
From, NOR gate 36, inverter 571・AN
Using D gate 58, signals (12) and (13) are simultaneously generated.

(In this case, if both are "1", O When the signal (14) is selected, the signal (14) is output.

Therefore, the communication control circuit 10 determines that the frame has started.

Also, the detection signal (12) from the pattern detection circuit 7
(signal (12) is rOJ).

Detection signal from biolage 1 detection circuit 8 4iK13)
When only the signal (15) is output (meaning that the signal (15) becomes "1"), a signal appears on the signal line 15, and the communication control circuit 1
0 determines that a transmission error has occurred and performs error control. However, since such a state is not shown in Fig. 5, the signal (
15) remains "0".

FIG. 4 is a diagram showing another embodiment of the present invention.

Ru. Figure 4 shows the pattern detection diagram in Figure 1.

iolation detection and status monitoring circuit.

This is an example of a circuit in which frame synchronization detection is performed simultaneously, and the same parts as in FIGS. 1 and 2 are the same.

- code, 42 is a frame synchronization detection circuit, 43 to 4
6 is a shift register (for example, Hitachi IC.

HD74LS164), 47-50 is NAN I)
Gates 51 and 52 are OR gates, 53 is a NAND gate, 54 to 76 are inverter gates, and 74 is a detected frame synchronization signal. With this circuit, FIG.

A method for detecting the synchronization code shown in (1) will be described.

The + side and - side of the AMI code on the bus 1 are received separately by the receiving circuit 4, and from the signals 1'□, that is, the signals (39) and (40) in Fig. 3,
45 , 44 , 47 of the frame synchronization detection circuit 42 ,
Signal (39) by 4B, 51, 54S-63
is “01010011J” and the signal (40) is “0010
0100'' is detected, and the detection signal (
That is, the same frame synchronization signal as in FIG. 3 (14) is output to the signal line 74.

That's why. In addition, in the case of AM Ding code,

Maruka is often not determined, and it seems that way.

In this case, the synchronization code shown in FIG. 3(1) is used.

Therefore, in the embodiment shown in FIG. 4, the synchronization code in that case is 4.
5, 46, 49, 50, 52, 64-75.

Detect. In addition, in the example of FIG. 4, it is bio.

It is not possible to detect only the ration, and pi:1 When performing error control using error detection.

requires a separate circuit.

As described above, the present invention is implemented by hardware.

Although the embodiment has been described in which the communication control circuit 10 is configured to use an arithmetic processing unit, most of the functions can be implemented by software. In that case, part or all of the functions of the code conversion circuits 2 and 5, the clock control circuit 6, the pattern detection circuit 7, the violation detection circuit 8, and the state monitoring circuit 9 in FIG.

It is possible to realize part 11 by software. Furthermore, although the above embodiments have described the case where the AMI code is used, other codes, such as the CM/I code (Code
Mark Inversion).

can be applied in the same way.

In addition to the pattern shown in Figure 3 (1), various other patterns are considered for the synchronization code.

It will be done. For example, the HDLC synchronization code “0111111
An example of application to 0J is shown in FIG. .

(1) and (2) are cases where the position of the violation has been changed.

(6) is the case where two violations are performed.

It shows. In short, the predetermined bi.

The bit pattern that is the same as the bit pattern is detected.

pattern detection circuit and a predetermined pattern detection circuit.

It has a violation detection circuit that detects bits or bit strings that violate code conversion rules, and when detection outputs are obtained from two detection circuits at the same time, it is judged as the start of a frame, and only the detection output from the violation detection circuit is detected. In this case, it can be determined that a transmission error has occurred.

〔Effect of the invention〕

According to the present invention, it is possible to realize a communication control device that can reliably achieve frame synchronization without reducing transmission efficiency with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 2 shows the main part of the communication control device according to the present invention. FIG. 5 is a timing chart TII for explaining the operation of FIG. FIG. 4 shows another embodiment of the invention, and FIG. 3 shows an example of a synchronization code used in the invention. It is a diagram. 1... Transmission line (bus) 2... Code conversion circuit 1゜3... Transmission circuit 4... Receiving circuit 5... Code conversion circuit 7... Pattern detection circuit 8... Violation Detection circuit 9... Status monitoring circuit 10... Communication control circuit 15

Claims (1)

[Claims] 1. In a communication control device that performs data communication using a code string of multiple bits as one frame, including a synchronization code consisting of multiple bits, a first bit pattern consisting of a predetermined multiple bits is detected. a second detection means for detecting a bit or a bit string that violates a predetermined sign change rule; and a third detection means for detecting that detection outputs from the first and second detection means occur simultaneously. 1. A communication control device comprising: a detection means, and a frame start is determined by an output from the third detection means. 2. The communication control device according to claim 1, wherein when only a detection output from the second detection means occurs, it is assumed that a transmission error has occurred and error control is performed.