JPS6156551A - Method and device for transmission of data - Google Patents

Abstract

PURPOSE:To attain a data transmission system which secures a highly stable working with a simple circuit by converting an input code into a precoding code at the transmission side, delivering a synchronizing code at the reception side after detecting a specific pattern out of a received code and detecting the violation of the received code through a violation detecting circuit. CONSTITUTION:An input code (a) is expressed in a quadruple number (N=4) and therefore an operation is carried out by an adder circuit. Thus a precoded code (b) is obtained. A received code (g) is equal to the data signal underwent the polarity inversion control through a transmission part and transmitted via a transmission line. The code (g) is also supplied to a violation detecting circuit 25, and the violations are detected twice and continuously to a code that is intensionally operated at the transmission part. A single violation is detected in many cases to a code error due to noises, etc. When the violations are detected twice and continuously by a violation detecting circuit 26, the output of the circuit 25 is inhibited by a code error inhibiting circuit 27. In other cases, a code error signal (j) is delivered for a received signal.

Description

[Detailed description of the invention] [Technical field] Block synchronization by intentionally giving a violation of encoding rules to a partial response code (hereinafter referred to as class 1% rP, R code) The present invention relates to a data transmission system and a data transmission device having the function of transmitting sub-information such as signals.

[Prior art]

In data transmission using a class ■P-R code, a violation is given to the class ■P-R encoded code at the transmitter under certain conditions.

It is possible to transmit sub-information such as a professional synchronization signal by utilizing violations characteristically detected by the receiving section (Japanese Patent Application No. 57-26823).

For the following explanation, [1), class ■P in formula 123
- Indicates the encoding rule.

bn=an■J)n-2・・−・−−−・(1)c=
b-b ・・・・・・・・・ (
2)! 'Inn-2 +1), +23 In the formula, the symbol ali input sign, b
is the precoded code, C is the class ['-R,
The number R, and the subscript ni attached to each symbol is the time nT.
(assuming that the input code a is added in units of T seconds). Ma7'Cbn-2 is bot-
It represents a code delayed by 2T seconds. Note (1)
The equation is an operation called precoding, where the symbol ■ represents addition modulo N, and the value of the input code is expressed as an N-ary number.

Class 17P - Intentional violation of code.

In a conventional data transmission device that transmits sub information by giving a code, the time series of the code bn expressed by the above equation (1) is monitored, and when a specific code sequence pattern is detected, the above (2) is performed. A violation was given to one code on the time series of codes Cn expressed by the formula. Therefore, there is a drawback in that it greatly impairs one of the features of the Class 17F-C code, which is the good straight-line performance.

In the transmitting section of another conventional data transmission device, the first means described below is to reduce the degree of loss of ``good flow balance''.

(1) Even if a specific pattern appears on the bn time series, a violation is not given, but a violation is given only when a specific pattern is detected several times.

(2) Prepare conditions for a violation operation that converts a positive polarity sign to a negative polarity sign and a violation operation that converts a negative polarity sign to a positive polarity sign, and perform a violation of positive polarity and negative polarity. (Japanese Patent Application No. 57-088987).

On the other hand, the receiving section of this data transmission device requires special synchronization protection to prevent the synchronization circuit from malfunctioning due to code errors caused by noise on the transmission path (Japanese Patent Application No. 45314/1982).

・　　Purpose of the invention〕 The purpose of the invention is to overcome the drawbacks of conventional devices.

It is an object of the present invention to provide a data transmission system and a data transmission device that achieve stable operation with a simple circuit.

[Structure of the invention]

In the data transmission system of the present invention, on the transmitting side, an input code is converted into a precoding code, the input code is converted into a class ■partial response code, a specific pattern is detected from the precoding code, and the specific pattern is When the detection time is within the valid period of the reference phase signal, a control signal is output, the partial response code is delayed in units of 2T seconds by the first delay means, and the output of the first delay means is further delayed by the second delay means. The delay means is used to delay in units of 2T seconds.

When the control signal is output, the polarity of the output of the first delay means and the second delay means is inverted and transmitted, and on the receiving side, the received code is demodulated to reproduce the class ■ partial response code, Detecting a specific pattern from the received code and outputting a synchronization code, detecting a violation of the received code with a violation detection circuit, and when the violation is detected twice within a predetermined period, the violation detection circuit The present invention is characterized in that the output of the violation detection circuit is completely prohibited, and when the violation is detected once within a predetermined period, the output of the violation detection circuit is output as a code error signal.

〔Example〕

Next, the data transmission system according to the present invention will be explained in detail with reference to all the drawings.

FIGS. 1 and 2 are a diagram of a coding circuit of a transmitter according to an embodiment of the present invention, and a timing chart for explaining the entire operation of the diagram. In FIG. 1, if the input code a is expressed as a quaternary number (N=4), then the modulo-4 addition circuit 1 performs the calculation of equation (1) above, and a precoded code is obtained. . code b
After being delayed by 2T seconds by H delay circuit 5, adder circuit 1. It is added to the subtraction circuit 2. However, the input code a is a code sequence added every T seconds, and the value at time nT is represented by the symbol an. The code C is a class ■P-code code expressed by the above equation (2).

The signal delayed by 2T seconds by circuit 5 is further delayed by 2T seconds each in delay circuits 11 to 15, and the output codes of 1% delay circuits 11 to 15 are applied to pattern detection circuit 16 in parallel. On the other hand, the code C is delayed by 2T seconds in each of the delay circuits 6 to 10 and becomes the output code d. However, the polarity of the output codes of the delay circuits 7 and 10 is controlled by the polarity inversion control signal f and the polarity inversion circuit 3.4. Signal e is a refined signal that provides a phase reference signal for achieving block synchronization in the receiving section, and its relationship with input and output code sequences is shown in FIG.

In FIG. 2, jan) represents the time series of input code a, and the symbols A, B, and C are 3-channel parallel signals t-2,
This shows the position of the code of each channel when converted to parallel signals. (Cn)U Represents the time series of the class ■P/C code calculated using the formula (1) and +21 above, where P represents the polarity (P)1.

If the time when the predetermined pattern is detected in the circuit 16 of FIG. 1 is within the high level period of the signal e, the AND gate 1
7, that is, the polarity inversion control signal fU''1'.The broken line at signal f in FIG. 2 shows the waveform when the above conditions are satisfied.

Next, an example of polarity reversal control using gold in Table 1 will be shown.

However, the X mark indicates the other interleaved code sequence,
Y and Z are values that follow the sign rule of the above equations t1) and +2).

In FIG. 1, the pattern detection circuit 16 is used.

The code sequence (bnJ pattern was monitored and the (bn) pattern shown in Table 1 was obtained, and the time and
When the signals e match, the signal f becomes 11'', and the polarity of the sign input to the polarity inverting circuit 3.4 is inverted.

In Table 1, (Cfl) is the normal class VIP-R
In the code series, (C-) is a code series whose polarity has been inverted according to the above condition, and the code indicated by () has had its polarity inverted. In both of the conventional data transmission devices, since only one code was used for polarity reversal, the DC balance was greatly disturbed and various countermeasures were required.As is clear from Table 1, according to this embodiment. DC balance collapse
- Since the polarity reversal of the sign for immediate correction is performed subsequently, the collapse of the DC balance can be reduced compared to the conventional method. ′! ! By appropriately increasing the length of the monitored (bn) pattern, the number of inversion controls is reduced, and therefore a circuit for limiting the number of inversion controls is not required.

Figure 3 and! FIG. 4 is a schematic diagram of a decoding circuit of a receiving section in an embodiment of the present invention, and a timing diagram for explaining the entire operation of the block diagram. In FIG. 3, the received code g is a Yonetomo data signal which is subjected to polarity inversion control in the transmitter and is sent via the transmission path. The code g is decoded by the class IVP decoding circuit 18, and its output code will be the same as the input code a of the transmitter if there is no code error in the transmission path.

The code failure is also supplied to the violation detection circuit 25 of the class ffP-R code rule, and by intentionally operating it in the transmitting section, a violation is detected twice in a row for the next code, and due to noise etc. In most cases, a code error is detected as a single biorearing. If the double consecutive violation detection circuit 26 detects two consecutive violations, the code error prohibition circuit 27 inhibits the output of the detection circuit 25, and in other cases, outputs it as a code error signal j of the received signal. , used for monitoring transmission quality, etc. (see Japanese Patent Application No. 57-26823).

Furthermore, the signal g is delayed by t seconds in each of the delay circuits 19 to 23, and the output signal of each delay circuit is sent to the pattern detection circuit 2.
4 in parallel.

However, XI:I] indicates the other interleaved code sequence, and the subscript nfc attached to each code indicates the code at time nT. Also, parentheses ( ) indicate a code sequence.

In Figure 84, code i has no code error and (C") = (
gn), it is detected in synchronization with the code of channel A. Therefore, by phase-synchronizing the timing of the receiving section with the code i, it becomes possible to separate the signals that have been time-division multiplexed.

In conventional data transmission devices, a violation operation is performed on one code in a code sequence, and a complicated synchronization protection circuit is required to prevent malfunctions caused by noise. The pattern of the code sequence is long, and 2.

Because the biorake operation is performed on each code, even if code errors occur due to noise, etc.

The probability that signal I will be detected erroneously is much smaller than in the past. In other words, the reliability of the detected code 5 becomes high.

Above, we have described an example of how to synchronize with Zun Pro, but violation operations are also possible in addition to those shown in Table 1, and there are many combinations of n codes, and sub information other than block synchronization. and a combination of those codes to perform a violation operation.

0 or more is a quaternary 7-value class that can also transmit multiple sub-information.
2-1) Value class ■P-code can be similarly extended.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to simplify the encoding circuit in the transmitting section of the data transmission device, and increase the reliability of the detected phase reference and correct signal in the receiving section. This makes it possible to realize a more stable data transmission method.

[Brief explanation of the drawing]

#I1 is a diagram showing a data transmitting device in an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of FIG. 1, and FIG. 3 is a block diagram showing a data receiving device in an embodiment of the present invention. 4 are timing diagrams showing the operation of FIG. 3. 1... Addition circuit, 2... Subtraction circuit, 3
．． 4...Polarity inversion circuit, 5-15...
Delay circuit, 16... Pattern detection circuit, 17.
...AND gate, 18...Class ■Barkyard response decoding circuit. 19-23...delay circuit, 24...pattern detection circuit, 25...biorea 1 detection circuit, 26...2 consecutive violation detection circuit , 27... code error] prohibition circuit. Figure 2 Figure 4

Claims (2)

[Claims] (1) On the transmitting side, convert the input code into a precoding code, convert the input code into a class IV partial response code, detect a specific pattern from the precoding code, and detect the specific pattern at the reference phase. When the signal is within the valid period, a control signal is output, the partial response code is delayed by a first delay means in units of 2T seconds, and the output of the first delay means is further delayed by a second delay means for 2T seconds. unit, and when the control signal is output, the polarity of the output of the first delay means and the second delay means is inverted and transmitted, and on the receiving side, the received code is demodulated to generate the class IV partial response. regenerating the code, detecting a specific pattern from the received code and outputting a synchronization code;
A violation of the received code is detected by a violation detection circuit, and when the violation is detected twice within a predetermined period, output of the violation detection circuit is prohibited, and when the violation is detected once during the predetermined period, the violation is detected once during the predetermined period. A data transmission system characterized in that, when a violation is detected, the output of the violation detection circuit is output as a code error signal. (2) means for converting an input code into a precoding code; means for converting the input code into a class IV partial response code; pattern detection means for detecting a specific pattern from the precoding code; and detecting the specific pattern. a gate that outputs a control signal when a time point is within the valid period of the reference phase signal; a first delay means that delays the partial response code in units of 2T seconds; and a gate that delays the output of the first delay means for an additional 2T seconds. A data transmitting device comprising: second delay means for delaying in units; and means for inverting the polarities of the outputs of the first delay means and the second delay means when the control signal is output.