JPS61166626A - Related arithmetic processor - Google Patents

Abstract

PURPOSE:To perform related arithmetic with exclusive hardware and to shorten the related arithmetic processing time, by adding a new identifier to the relation code with which the arithmetic conditions are satisfied. CONSTITUTION:An arithmetic part OPP of a related arithmetic processor contains the U buffers 20U and 20L which store the 1st and 2nd relations, the output registers 24U and 24L which store the read data on said U buffers and a comparator 23. An MOP register 39 of a main control part 38 in a control part CNTP designates a merge operation. While the data on the merge operation is set to a command register 41 connected to a CPU. The outputs of the registers 24U and 24L are applied to a URB buffer 30U and an LRB buffer 30L of an output selection part OSP as the data equivalent to a record respectively. Then a new identifier is added to the relation code with which the arithmetic conditions are satisfied. Thus the related arithmetic is carried out by the hardware at a high speed and in a short processing time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention particularly relates to a relational operation processing device that executes relational operations required in relational database processing.

[Technical background of the invention and its problems] One of the main processes in a relational database is a relational operation between two relations. As a relational operation,
Join, Restriction,
Projection and the like are well known.

This type of relational calculation has generally been handled by software. Therefore, a large amount of processing time is required for relational calculations. Therefore, there has been a demand for a dedicated hardware device that can speed up the above-mentioned relational calculations.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a relational calculation processing device as dedicated hardware that can efficiently perform relational calculations.

Another object of the present invention is to provide a relational arithmetic processing device that can add a new identifier to a relation record for which arithmetic conditions have been met.

[Summary of the invention], 1. In this invention, the first relation is stored l
A first buffer and a second buffer storing a second relation are provided. Further, in the present invention, a first register that holds an operation code indicating the operation type and a buffer specification pit that specifies either the first or second buffer, and a relation stored in the first or second buffer are provided. a second register that holds record number information indicating the number of records constituting the register;
A third register holds record bunch information indicating the record length of the records constituting the relation stored in the buffer, and a fourth register holds key field length information indicating the key field length of the relation.

If load processing is specified by the operation code held in the first register, the first or second
The number of records specified by the second register above in the buffer specified by the buffer specification bit above,
Then, a relation of the amount of data indicated by the record length specified in the third register is written. In addition, even when relational operation processing is specified by the operation code held in the first register, the buffer specified by the buffer 7 specification pit among the first or second buffers is specified by the second register. The relation between the number of records to be processed and the amount of data indicated by the record length specified in the third register is written. However, if relational calculation processing is specified, a record read operation is performed in parallel with the above writing to read data from each of the first and second buffers, one record at a time.

Further, in the present invention, a third buffer temporarily stores data for one record read from the first buffer, and a second buffer.
a fourth buffer that temporarily stores data for one record read from the buffer; a comparison circuit that compares both records read from the first and second buffers between key fields specified by the fourth register; and a first output control means. The first output control means performs address updating control for the first and second buffers according to the comparison result of the comparison circuit and the operation code held in the first register, and temporarily stores the addresses in the third and fourth buffers. External output control of both records or either record is performed.

Furthermore, in the present invention, a counter whose initial value can be set via an input/output bus, a counter control means, and a second output control means are provided during relational calculation processing. The second output control means outputs the contents of the counter to the outside as an identifier of the output record when the first output control means outputs the record.

Further, the counter control means updates the counter according to the record output by the first output control means.

[Embodiment of the Invention] FIG. 1 shows the configuration of a marsha (relational processing unit) 10 according to an embodiment of the invention, and the second factor is the relational database engine (which applies merge 1 to 10 in FIG. 1). below,
RDBE). In the RDBE shown in FIG. 2, 11 is a CPU that controls the entire RDBE, and 12 is a sorter (sort processing bag) that applies a two-way merge sort method. Sorter 12 has 12 stages of sort cells 1
It consists of 2-O to 12-11, and records can be sorted into a maximum of 4. 13 is sorter 12
IN aligner (sort preprocessing device) installed on the input side of
, 14 is a sort checker that monitors whether the sort results of the IN aligner 13 are correct.

Marsha 10 is connected to sort checker 14 and is configured to perform relational operations at high speed between one or two relations that are being sorted by sorter 12 . The IN aligner 13, sorter 12, sort checker 14, and marsha 10 constitute an engine core 15, which is dedicated hardware that performs pipeline processing synchronized with input data by linking sorting processing and relational calculation processing. do. 16.17 is an RDBE and a double-layer structure memory subsystem (hereinafter referred to as HM) not shown.
Ink 7, -yu. 1□88 Yaatsuau, Tsue, HM
HM A 16 is an 8MA input port for data to the engine core 15.
17 acts as an output port for data from engine core 15. 18 is the input/output bus of CP Ll 11,
19 is a DMA bus. The input/output bus 18 includes each component of the engine core 15 including the Marsha 10,
CPU 11 and 8MA16.17 are connected,
DMA bus 19 includes CPU 11 and 8MA16.
．． 17 are connected.

As shown in FIG. 1, the marsha 10 includes a calculation section OPP, an output selection section O5P, and a control l1 section CNTP that controls the calculation section OPP and the output selection section O8P.

In the calculation unit OPP, 20U is a U (Upper) buffer (hereinafter referred to as UB) that stores the first relation, and 20L is an L (LO) buffer that stores the second relation.
W8r) Buffer 1 (hereinafter referred to as 1B). 21
1J is an input register (INU register) that holds data to be written to UB20U, and 21L is an input register (INL register) that holds data to be written to La2O2. 22U is a register (LIPR register) that holds data read from the UB 201J, and 22L is a register (LOW register) that holds data read from the LB 20L. 23 is a comparator (hereinafter referred to as CMP) that compares the contents of the UPR register 22U and the LOW register 22L.
), 24U is an output register (OTU register) that transmits the contents of the UPR register 22U to the output selection unit O8P side, and 24L is an output register (OTL register) that transmits the contents of the LOW register 22L to the output selection unit O8P side. be. 25U is a write address register (WAtJ register) as a write pointer for U320U
, 25L is a write address register (WAL register) as a write pointer for L820L.

261J is a read address register (RAU register) as a read pointer for UB20U, 26L is L
This is a read address register (RAL register) as a read pointer for B20L. WAIJ register 25U, WAL register 25U, RAU register 26
U and RAL register 26L have a counter function. 27U is a backup register (BUU register) that holds the contents of the RAU register 26U, and 27L is a backup register (BLJL register) that holds the contents of the RAL register 26L. 28U is a comparator (CMP) that compares the contents of WAU register 25U and RAU register 26U, and 28L is WAL register 25.
This is a comparator (CMP) that compares the contents of the L and RAL registers 26L. 29LI is WALJ register 25
The contents of LI or RAtJ register 26U are transferred to UB20U.
The multiplexer 29L selects the contents of the WAL register 25L or the RAL register 261 as the memory address for the LB20L.

In the output selection section O8P of FIG. 1, 30LJ 1. t
The record buffer (URB) stores one record's worth of data from the UB20U, and the record buffer (LRB) 30L stores one record's worth of data from the LB20L. 31LI is 0TIJ register 24
Input register (INUR register) 31 that holds the contents of 1J as write data for URB 30U.
L is an input register 31 (INL) that holds the contents of the OTL register 241 as write data to the LR8301.
P register). Reference numeral 32 denotes an identification number counter (NTID counter) that generates an identification number NTID attached to a record output from the marsher 10. The NTID counter 32 is connected to an input/output interface 40, which will be described later. The NTID counter 32 has a clock terminal OK to which a counter strobe signal 95 is supplied, a count up enable terminal E to which a count up enable signal 90 is supplied, and a load terminal to which a load signal 109 is supplied. 37N is NTID counter 3
Output the identification number NTID generated in step 2 as the control signal 91N.
Gate to gate according to, 37U is U RB 30U
A gate 37L gates read data from the LR830L in response to the output control signal 91tJ, and a gate 37L gates read data from the LR830L in response to the output control signal 91L. 33 outputs the output data from the gates 37N, 37U, and 37L to latch f according to the strobe signal 93.
76mjEI, t')l'l (ROLIT, 925)
T alo. , f□34U is the write address register (WA
LJR register) 1.1'4 L is the write address register (W
ALR register). 35U is a read address register (RALIR register) as a read pointer for U R830tJ, and 35L is a read address register (RALIR register) as a read pointer for LRB3OL.
ALR register). WAUR register 34U, W
ALR register 34L, RAUR register 35U, and RALR register 35L have a counter function.

36U is a multiplexer that selects the contents of WAUR register 34U or RAUR register 351J as the memory address for URB 30U, and 36L is WAL.
This is a multiplexer that selects the contents of the R register 34L or the RALR register 35L as a memory address for the LR830L. The NT and ID counter 32 can be set up in advance by the CPU 11 shown in FIG.

In the control unit CNTP in FIG. 1, 38 is the control unit CNT.
The main control section 39, which forms the center of P, is an 8-bit merge operation register (MOP register) provided in the main control section 38.As shown in FIG. A 5-bit merge operation specification code (MRG-0P code) that specifies the sort order, a sort order specification bit (AS/DSS/upper) that specifies the sort order, and UB
For the 20U roll, merge operation designation information including a buffer designation bit (U/L bit) that designates LB20L is set. In this example, ascending order is AS/DS-0, and AS/DS
-1 specifies descending order. Also, with U/L=O, UB20
U is U/L-1 and LB20L is specified.

40 is an input/output interface that is an interface to the CPU 11 (its input/output bus 18); 41 is a command register (CM) provided in the input/output interface 40;
D register). The CMD register 41 contains the CPU
According to the specification from 11, 8-bit command data is set. The 0th bit of this command data is a register designation bit (REG, IND) as shown in FIG.

The REG and IND bits indicate whether the command data is used as data that specifies (the register number of) the register in the merger 10 (in the case of REG, IND-1), or as the original operation specification data of the command data. Specify whether it is used (in case of REG, IND-0). REG
, lN0=O, as shown in FIG. The engine start designation bit (ENG, Go bit) to specify, the 4th bit specifies the start of only the Marsha 10 (MRG, Go bit), and the 6th bit clears the RAU register 26U and FUEMP521J, which will be described later. The 7th bit of the specified U retry designation bit (URTRY bit) is the RAL register 261 and the FLE described below.
L retry designation bit (
LRTRY bit). Note that the operation designation of each bit described above is valid when the logic is "1".

Referring again to FIG. 1, 42 brushes B20U or LB
The total record number register (T
RN register), 43U is a record size register (R8U register) indicating the record length R8U of the relation stored in U B 20U, and 431 is a record size register (R3L register) indicating the record length R8L of the relation stored in LB20L. be. 44 is a multiplexer that selects the contents of R8U register 43U or R8L register 431; 45 is multiplexer 4;
Load the selected output data from 4 as the initial value, and
Write counter (WRC counter) that counts down when writing to 20U or LB20L, 46 is TR
Load the contents of the N register 42 as an initial value, and
This is a record number counter (STC counter) that counts down in response to a borrow signal from the counter 45.

47 is the comparison target in the merge operation, 612 . -8
Kaya-7<-)1. = h1% (□Data l″: Long V
Valid data length register (VDL register) indicating DL)
, 48 loads the contents of the VDL register 47 as an initial value, and a valid data length counter (
VCT counter).

MoP register 39, CMD register 41, TRNL/
register 42, R8U register 43U, R8L register 4
3L and VDL register 47 are CPIJ in FIG.
It can be set up in advance using ll.

49U is a read counter (RCLI counter) that loads the contents of the R8U register 43U as an initial value and counts down when reading data from tJB20U.
L is a read counter (RCL counter) which loads the contents of the R8L register 43L as an initial value and counts down when reading data from LB2OL. 50U
is set in response to a borrow signal from the RCU counter 49U, and is a record end flag (
FUE flag), 50L is a record end flag (FLE flag) that is set in response to a borrow signal from the RCL counter 49L and indicates that the data read from LB 20L is the last data of one record.

51U is a write completion flag (FLJWED flag) indicating that writing to tJB20U is completed, 51L is L
This is a write completion flag (FLWED flag) indicating that writing to B20L has been completed. 521J is UB20
Empty flag (F) indicating that LJ is empty
UEMP flag), 52L is an empty flag (FLEMP flag) indicating that LB20L is empty.
It is. 53U is an output instruction flag (FUO flag) that instructs external output of data from U320U, and 53L is an output instruction flag (PLO flag) that instructs external output of data from LB20L.

54U is a register (O8UA register) as an extraction pointer that specifies the first extraction position for the read record from U R830jJ, and 54L is LRB3OL.
A register (oSLA register) as an extraction pointer that specifies the first extraction position for the record read from URB 30U, 55U is a register (O8UB register) as an extraction pointer that specifies the second extraction position for the record read from URB 30U, 55L is LRB30
This register (O8LB register) serves as a cutout pointer that specifies the second cutout position for records read from L. 56 is U RB 30U or LRB3
A counter (CTR counter) that counts up when data is read from 0L, 57U a comparator (CMP) that compares the contents of the CTR power counter 56 and the 08UA register 54U, and 57L a comparator (CMP) that compares the contents of the CTR counter 56 and the 08LA register 54L. A comparator that compares the contents (
CMP). 58tJ is a comparator (C
MP), 58L is a comparator that compares the contents of the CTR counter 56 and the 08LB register 55L.CMP), 5
9U is CTR counter 56 and R8U register 43U
A comparator (CMP) that compares each content of , 59L is CTR
This is a comparator (CMP) that compares the contents of the counter 56 and the R8L register 43L. oSUA register 54
U10SU8 register 55U, 08LALz register 54
The LSO3LBLz register 55L is the CPU of FIG.
11, it can be set up in advance.

Next, the configuration of the main control section 38 shown in FIG. 1 will be explained with reference to FIG. 5. In FIG. 5, 60 is the FtJE flag 5
A control timing generation circuit 61 determines the timing of generating various control signals according to the 0U and FLE flags 50L, the CMD register 41, etc.; This is a clear circuit that clears each part at the timing of the start instruction. 62 is CMP
a comparison control unit 6 which determines the comparison result of the key field of each record from U320U and LB20L based on the comparison result of 23 and the output from the VCTCTR counter;
Reference numeral 3 denotes an interrupt control section that generates an interrupt to the CPU 11 in FIG. 64 is an output control unit that controls the output of data to the outside; 65 is a control timing control unit according to the content of the MOP register 39 and the comparison result of the comparison control unit 62;
This is a control signal generation circuit that generates various control signals for UB20U readout control, LB20L readout control, interrupt control, output control, etc. at timings according to instructions from the 1' generation circuit 60.

Next, the configuration around the interrupt control section 63 in FIG. 5 will be explained with reference to FIG. 6. In FIG. 6, 66 is an inverter to which the tJ/L bit from the MOP register 39 is input, and 67U is the output of the inverter 66 and the STC counter 4.
AND gate (A) into which the borrow signal from 6 is input.
, 67L is an AND gate (A) to which the U/L bit from the MOP register 39 and the borrow signal from the STC counter 46 are input.

The FUWED flag 511J is set according to the output signal from A67tJ, and the FLWED flag 51L is set according to the output signal from A67L. 68U is an AND gate (A) into which the comparison result (coincidence detection signal) of CMP28U and the output signal from the FUWED flag 51U are input, and 68L is the comparison result (coincidence detection signal) of CMP28L and the FUWED flag 51
This is an AND gate (A) into which the output signal from L is input. 69tJ is a gate that gates the output signal from A68U at the specified timing from the control timing generation circuit 60, and 69L is a gate that gates the output signal from A68L at the specified timing from the control timing generation circuit 60. FUEMP flag 52U is connected to gate 69LI, F
LEMP flag 52L is set in response to the output signal from gate 69L. A decoder 70 decodes the contents of the MOP register 39 (merge operation designation information). When the merge operation specification information specifies loading the first relation to the UB20U, the decoder 70 performs
When the load signal 71U specifies loading of the second relation to L820L, the load signal 71L is output.

72U is the load signal 71U from the decoder 70 and FUW
The AND gate (A) to which the output signal from the ED flag 511J is input, and 72L is an AND gate (A) to which the load signal 71L from the decoder 70 and the output signal from the FLWED flag 51L are input. 73tJ is the interrupt enable signal 74U from the control signal generation circuit 65 and FUEMP.
The AND gate (A) 731 receives the output signal from the flag 52U, and the AND gate (A) 731 receives the interrupt enable signal 74L from the control signal generation circuit 65 and the output signal from the FLEMP flag 52L. . Interrupt permission signals 74tJ and 74L are generated from control signal generation circuit 65 according to the contents of MOP register 39. For example, 5ORT (sort) operations and RESTRICT (
When a constraint) type operation is specified, interrupt permission signals 74U and 741 are output, and when a JOIN type operation is specified, only the interrupt permission signal 74U is specified. Also, if a PASS type operation is specified, U/L-0 (i.e., UB20U specified)
If so, the interrupt enable signal 74U is U/L-1 (that is, L
B2OL designation), an interrupt permission signal 74L is output. 75 is an OR gate (O
R), 76 is an interrupt generation circuit that generates an interrupt signal ATN in response to the output signal from the OR 75.

Next, the configuration around the clear circuit 61 in FIG. 5 will be explained with reference to FIG. 7. In FIG. 7, 77 is an inverter to which the U/L bit from the MOP register 39 is input;
78U is an AND gate (A) into which the output signal from the inverter 7 and the ENG and Go bits in the command data held in the CMD register 41 are input, and 78L is a Mo
The /L bit from P register 39 and the above ENG, Go
This is an AND gate (A) into which a bit is input. 79
U is an OR gate (OR") into which the output signal from A78U and the R8T bit from CMD register 41 are input.
, 79L is an OR gate (OR) into which the output signal from A78L and the R8T pit are input. 80U is 0
Output signal from R79U and U from CMD register 41
OR gate (OR) to which the RTRY bit is input, 8
0L is the output signal from 0R79L and CMD register 41
The output signals of OR'79U7'81U, 0R79U7'l', which are input with the LRTRY bit from WAU register 25UF3 and FUWED
As a clear signal for the flag 51U, the control signal is output from the control timing generation circuit 60 at a specified timing.
The gate 81L gates the output signal from the 0R79L at a specified timing from the control timing generation circuit 60 as a clear signal for the WAL register 251 and the FLWED flag 51L. 82U is a gate that gates the output signal from 0R80U as a clear signal for the RAU register 26U and FUEMP flag 52U at a specified timing from the control timing generation circuit 60; 82L is a gate for 0R80U;
The output signal from L is sent to the RAL register 26L and FL
This is a gate that is gated at a specified timing from the control timing generation circuit 60 as a clear signal for the EMP flag 52L.

Next, the configuration around the output control section 64 in FIG. 5 will be explained with reference to FIG. 8. In FIG. 8, reference numeral 83 indicates U RB according to the states of the FUO flag 53tJ and FLO flag 53L and the contents of an output selection control register (not shown).
This is an output sequence control unit that controls the output order of data from 30U and LRB 30L. The output selection control register is used to instruct the addition of the identification number NTID and the output order when the U-side and L-side codes are output together. The output sequence control section 83 outputs a count-up enable signal 90 to the NTID counter 32 in FIG. 1 during the output sequence control period, and outputs a counter strobe signal @92 every time one sequence ends.

84N is the identification number N generated by the NTID counter 32
The NTID output control section controls the TID output. N
The TID output control section 84N is the output sequence control section 83
In response to the output start instruction from the output control signal 91N (for the gate 37N in FIG.
7N to perform identification number N T4D output control.

84tJ is a tJRB read control unit that controls data read from the IJ RB 30U, and 84L is an LRB read control unit that controls data read from the LRB 301. The read control units 84U and 84L start the record read control operation in response to a read start instruction from the output sequence control unit 83, and perform the read control operation in response to the comparison result (coincidence detection signal) of the CMPs 59U and 59L in FIG. stop. During the read control period, the read control units 37U and 37L output control signals 91U and 91L (for the gates 37U and 37N in FIG. 1), and a strobe signal 87U,
Outputs 87L. Further, the flags 53U and 53L are output instruction signals 85U and 85L from the control signal generation circuit 65.
Set accordingly. 86 is a control unit 84N, 84U
, Z-trope signal from 84L 87N , 871
J, 87L is input off gate (OR), 88
is a gate that gates the output signal from the OR 86 and outputs a strobe signal 93 to the ROUT register 33. 89 follows instructions from the output sequence control section 83,
CM P57U, 58tJ or CMP57L, 5
An extraction control section 94 monitors the comparison result of 8L and controls the gate 88 according to the monitoring result, and a counter strobe signal 92 from the output sequence control section 83 and an input signal (supplied via the input/output interface 40) are provided. An OR gate (O
R>.

The output signal of 0R94 is supplied as counter strobe signal 95 to NTID counter 32 (see FIG. 1).

Next, the configuration of the input/output interface 40 in FIG.
This will be explained with reference to the figures. In FIG. 9, 101 is an input/output driver that inputs and outputs various control signals to/from the input/output bus 18, 102 is an input driver that inputs data from the input/output bus 18, and 103 is an input/output bus 18.
This is an output driver that outputs data to. The output target control signal of the input/output driver 101 includes C in FIG.
There is an interrupt signal ATN for PU11. The input target control signals of the input/output driver 101 include a command signal CMD that indicates the output of command data, a write signal WD that specifies data writing, a read signal RD signal that specifies data reading, and a status (information) read signal that specifies reading. Status signal STS and the above interrupt signal AT
There is a response signal (interrupt acknowledgment signal) ACK to N.

Command signal CM input from input/output driver 101
D is used as a strobe signal for the CMD register 41.

Reference numeral 104 denotes an inverter to which the Q pit of the output data (command data) of the CMD register 41, that is, the REG and IND pits, is input. This is a gate that gates according to a signal. gate 10
The output data from 6 is supplied to main control section 38 of FIG. 106 is the output data of the CMD register 41 (the first
7th bit) to its 0th bit (REG, IND
bits), 107, 108
is a decoder (DEC) that decodes the output data from the gate 106. The DEC 107 is enabled by the write signal WD input from the input/output driver 101, and generates load signals for various registers and counters in the marsher 10, such as the O-do signal 109 for the NTID counter 32 in FIG. Also DEC108
is the read signal RD input from the input/output driver 101
It generates various output control signals that instruct the output of the contents of various registers and counters in the marsher 10 to the input/output bus 18.

One of these output control signals is an output control signal 110 that instructs output of the identification number NTID generated by the NTID counter 32 to the input/output bus 18 . 111 is NTID
A gate 112 gates the identification number NTID generated by the counter 32 in response to the output control signal 110, a gate 112 gates the equipment number of the marsher 10 in response to the response signal ACK, and 113 gates the status (information) of the marsher 10. This is a gate that is gated in response to the status signal STS. Output data from gates 111-113 is supplied to output driver 103.

Next, regarding the operation of the above configuration, RESTRICT
Taking the case of system operations as an example, explanation will be given with reference to FIGS. 10 to 12. FIG. 10 shows a sequence of commands for executing RESTRICT operations, and the FtJWED flag 51U, WAU register 25tJ, and RAU register 26 at startup and termination by these commands.
U, FLWED flag 51LSWAL register 25LS
The correspondence relationship with each content (state!!I) of the RAL register 26L is shown. In FIG. 10, ■ to ■ indicate the order of execution of commands.

In addition, FIG. 11 is a diagram illustrating changes in the write position (solid line) and read position (broken line) to UB20U and LB2OL at the end of execution of each command shown in FIG.
FIG. 2 is a diagram showing the input/output logic of the control signal generation circuit 65 when the RESTRICT type operation (1EsT-EQ operation) is specified.

In the RESTRICT type calculation, the condition data is stored in advance in the U320U as a first relation (stream), and the calculation is started while storing the target relation in the LB20L as a second relation (stream). Then, the designated key field of the condition data is compared with that of the target relation, and when the calculation condition is satisfied, the L side code is sent to the output selection unit oSP as the output target. Note that it is also possible to output the U-side code together with the L-side code.

Now, in the following explanation, the first relation is assumed to be 81, and the second relation is assumed to be $2. In RESTRICT type operations, first the setup for S1 is C
This is done based on instructions from P IJ 11. That is, c
Marcia 10 is specified as a device by p u il,
Thereafter, the command data is transferred to marsher 10 via input/output bus 18 along with command signal CMD. C.P.
Command data from LJ 11 is supplied to CMD register 41 via input driver buffer 02 in input/output interface 40 of marsher 10. Further, the command signal CMD is supplied to the CMD register 41 via the input/output driver 101 within the input/output interface 40. Thus, command data from the CPU 11 is held in the CMD register 41 in accordance with the command signal CMD. In this case, the command data has its Q-th bit, that is, the REG and IND bits set to logic "1", and specifies the registers (register number) in the marsher 10. If the REG, INO bit is logic '1', the gate 106 in the input/output interface 40
The command data (first to seventh pits) held in the D register 41 is gated.

As a result, the command data is supplied to the DECs 107 and 108 via the gate 106.

CPtJll [, above LID? Door day 91. ： に'
), When a register is specified, the data (setup data) to be set in the corresponding register is sent onto the input/output bus 18 together with the write signal WD. Therefore, the write signal WD on the input/output bus 18 is
0 input/output driver 10 in the input/output interface 40
1 to the DEC 107, the OR94 shown in FIG. 8, and the various registers shown in FIG. The DEC107 is enabled by the write signal WD, and the gate 1
It outputs a decode signal of command data from CMD register λ1 supplied from CMD register λ1. Now, assuming that the above command data specifies the NTID counter S2, the DEQ 107 outputs a load signal 109. This load signal 109 is the NTID in FIG.
It is supplied to the load terminal of the counter 32. Also, 0R
The write signal WD supplied to the NTID counter 94 is supplied to the clock terminal CK of the NTID counter 32 as a counter strobe signal 95. This NTID counter 32 has C
Setup data (in this example, the initial value of the identification number NTID) from the P tJ 11 is supplied via the input/output bus 18 and the input driver 102 in the input/output interface 40 . However, the above setup data is
Counter strobe signal 95 corresponding to write signal WD
The NTID counter 32 is set (loaded) accordingly.

Thus, in this embodiment, the CMD register 41 holds (REG, 'lND pit is logic "'1"
N in Marsha 10 specified by the command data of
The set-up data on the input/output bus 18 transferred to the write signal WD is sent to the TrO counter 32 as the same signal WD.
can be set accordingly. This is Marcia 1
The same applies to registers and counters other than the NTID counter 32 at 0.

Thereafter, in the same manner, for example, the MRG-OP code specifying load of the relation, UB
Merge operation specification information (LOAD (U) command) including the U/L bit of logic "O'' specifying 20U is set, information indicating the first field position of the record is set in the 08UA register 54U, and the osus register is set. Information indicating the last field position of the record is shown in 55 (
That is, the record length R8tJ) is set. Also, R
3t, the record length R8U (record length of each record in the first relation S1) is set in the I register 43U, the effective data length VDL indicating the key field length in the record is set in the VDL register 47, and the TRN register 42 is set. A total record number TRN of 81 is set. Note that (true value - 1) is actually adopted as R5IJ and VDLlTRN.

Note that the CMD register 41 is provided with a counter function, and the RE
CPl, ill when G, IND bit is logic “1”
The count may be incremented in response to the write signal WD from. In this case, if the register numbers of the registers to be set up are consecutive, once the merger 10 is designated as a ta device and the command data is transferred, it is simply written along with the desired data (setup data). It is sufficient to repeatedly output the signal WD onto the input/output bus 18.

Next, the CPU 11 again specifies the marsher 10 as a device, and this time sets command data in which the REG and IND bits are logic "O" to the CMD register 41 in the input/output ink face 40 of the marsher 100. This command data is an ENG, Go command whose third bit, ie, the ENG, Go bit, is set to logic 11111. Note that the R8T bit, MRG, GO bit, 1. ,
The IRTRY bit and the LRTRY bit are set to logic 'O'.
It is n. The above ENG, Go commands are Go commands for the engine core 15, which input the relation (stream data) from the HMA 16 to the marsher 10 via the IN aligner 13, sorter 12, and sort checker 14, and perform the merge operation. It is used when performing processing and outputting to 8MA17. In this case, Marsha 10 is
Data processing will be performed using data newly stored in UB20U or LB2OL. In contrast,
As a Go command for Marsha 10 only, MRG
, Go commands are provided.

Processing is performed on the significant data already stored in LB20L.

When the REG and IND bits of the command data set in the CM[) register 41 are logic "0", the gate 105 in FIG. 9 is enabled. As a result, the command data (first to seventh bits) set in the CMD register 41 is supplied to the main control section 38 via the gate 105. Marsha 10 is activated by ENG and Go commands set in CMD register 41. At this time, the clear circuit 1 clears the WAtJ register 25.
tJ, RAtJ register 26U, FUWED flag 51
U1 and FUEMP flag 52U are cleared (reset). That is, the U/L bit of the merge operation designation information set in the MOP register 39 is logic "O", and the CMD
Command data set in register 41 (however, RE
G.

ENG, Go bit in IND-0) is logic 111 I
In the case of +, the AND condition of A78U in the clear circuit 61 is satisfied, and a logic "1P" signal is output from A78U.The logic "°1P" signal from A78U is sent to the gate 81U via 0R79U. Along with being guided, OR79U.

It is led to gate 82U via 80U. Gate 81U
.

e2U is the clear timing by the start timing generation function of the control timing generation circuit 60, and the logic i
Gate the f 1 I+ signal. The logic “1” signal from gate 81U is sent to WAU register 25U and FUW.
Guided by the ED flag 51tJ, the logic "1" signal from the gate 82LI is sent to the RAU register 26U and FIJE.
It is guided by the MP flag 52tJ. As a result, the WAU register 25U, RAIJ register 26U, FUWED flag 51U1, and FtJEMP flag 52U are cleared. In this state, the marsha 10 processes the data specified by the (7) LOAD (U) command in the MOP register 39 at a speed synchronized with the input to the engine core 15. This data processing will be described below.

In Marsha 10, in response to the LOAD (U) command,
Under the control of the main controller 11i38, an operation is performed to store data (S1 in this example) in the UB 201J.

At this time, the corresponding data (Sl) is supplied from the sorter 12 via the sort checker 14 to the marsher 10 in units of predetermined bytes at a constant cycle. Sort checker 1
The data from UB2 is held in the INU register 21U in synchronization with the output cycle from the sort checker 14.
Guided by 0U. In the case of the LOAD (U) command, the main control unit 38 uses the WAU register register 5U to
Write data to U. That is, the main control section 38
A write control unit (not shown in the figure) writes the data held in the INU register 21U to the UB specified by the WAU register 25LJ selected by the 9 multiplexer 29U.
Write to that address in 201J, WAtJ register 2
Write control to increment 5U by 1 is repeatedly performed. The WAU register 25U is reset at startup as described above (see Figure 10), so S1 is UB20U.
are written sequentially starting from address 0.

When writing data to the UB20U, the main control unit 38 sets the contents of the R8U register 43U (record length R8U) to the WRC counter 45 via the multiplexer 44 at the start of its operation, and writes the contents of the TRN register 42 (total number of records) to the WRC counter 45 via the multiplexer 44. TRN) is set in the STC counter 46. The WRC counter 45 has a WAU register 25U (
In case of writing to L B 20L, WAL register 2
5L) is incremented by +1, it is decremented by -1. As a result, WR
The C counter 45 enters an underflow state when writing the final data of one record, and outputs a borrow signal. W
The borrow signal from the RC counter 45 is sent to the STC counter 4.
6, thereby decrementing the STC counter 46 by -1. As a result, the STC counter 46 enters an underflow state when writing the final data of the final record of Sl, and outputs a borrow signal. The borrow signal from the STC counter 46 is commonly led to one end of A67U and 67L.

A The other end of 67U has U/L inside the MOP register 39.
The pit is guided through the inverter 66, and the IJ/L bit is directly guided to the other end of 467L. Therefore, in this example, which is U/L-0, the AND condition of A 67U is satisfied, and from A 67U the FUWED flag 5
A logic "1" signal is output for 1U. As a result, the FUWED flag 51.U is set (see column ①LOAD (U), ENG, and Go commands in FIG. 10). The write control section in the main control section 38 is
A borrow signal from the TC counter 46 stops the write control operation. As a result, the WAU register 25U is
The count-up operation is stopped when the storage address of the final data of S1 (of the final record) is indicated.

In FIG. 10, "endJ" indicates that the contents of the relevant register at the end of execution of the relevant command will be the storage address of the final data (of the final record) of the relation, such as the contents of the WALJ register 25U described above. ing.

The set output signal from the FUWED flag 51U is A7
It is led to one end of 2tJ. A load signal 71U from the decoder 70 is guided to the other end of A72U. Decoder 7
0 has already decoded the contents of the MOP register 39,
In the case of the LOAD (U) command as in this example, a load signal 71U of logic "1" is output.

Therefore, in this example, by setting the FUWED flag 51U, the AND condition of A72U is satisfied, and A721
From J (UB2 by executing the LOAD (U) command
A logic 111N signal (indicating completion of writing to 0U) is output. The logic 11111 signal from A72U is O
It is led to the interrupt generation circuit 16 via R75, and thereby the interrupt generation circuit 76 generates an interrupt signal ATN for CPU II. When the CP tJ 11 receives an interrupt from the marsher 10 (the interrupt generation circuit 7G therein), the CP tJ 11 registers a status register (not shown) in the marsher 10 (this register contains the FUWED flag 51U, the FLWED flag 51U, and the FLWED
Flag 51LSFUEMP Flag 52tJ, FLEMP
(consisting of flag 52L, etc.) is read out,
Determine the cause of the interrupt.

When CPU 11 determines completion of writing the relation (Sl) to UB 20U by reading the status from Marsha 10, CPU 11 writes the next relation, that is, the second relation.
Perform setup regarding relation (S2). The setup in this case is substantially the same as the setup for S1 described above.

Note that the effective data length VDL is the first relation S
1 (75 and is common to each record of the second relation S2, so set-up is not necessary in the case of S2. Therefore, the registers to be set up in the case of S2 are MOP register 1, ○SLA register 54L, 08LB register 55, R8L register 4
3L1 and TRN register 42. However, MOP
The register 39 contains an MRG-OP code that specifies a RESTRICT type operation (REST-EQ in this example), an As10S bit that specifies sorting, and a merge operation specification that includes the U/L bit of logic "1 pass" that specifies LB2OL. The information (REST-EQ (L) command) is set.Then, $
As in case 1, marsha 10 is started again by setting the ENG and Go commands. At this time, the clear circuit 61 causes the WAL register 25L,
The RAL register 26L, FLWED flag 51L, and FLEMP flag 52L are cleared (reset). That is, the U/L bit of the merge operation designation information set in the MOP register 39 is logic "1", and the command data set in the CMD register 41 (however, REG, IN
If the ENG and Go bits in D-0) are logic “1”,
The AND condition of A78L in the clear circuit 61 is satisfied, and A
78L outputs a logic "'1" signal.A78L
The logic II 1 I+ signal from
is guided to the gate 82L via the gate 82L. Gates 81L, 82
L is the clear timing by the start timing generation function of the control timing generation circuit 60, and the logic 1 is
′′ signal is gated. Logic 1 from gate 81L
'' signal is guided to the WAL register 25tJ5 and the FLWED flag 51L, and the logic ``1'' signal from the gate 82L is guided to the RAL register 26L and the FLEMP flag 51L.
Guided by 2L. As a result, the WAL register 25L,
RAL register 26L, FLWED flag 51L1 and FLEMP flag 52L are cleared. In this state, the marsha 10 registers the REST-
EQ (L) Performs data processing specified by the command. About this data processing 91''''3 Holo6・Na5・
RE S T −E Q +, t・condition de;
1” - indicates that the target relation is output when the evening key field and that of the target relation are equal.

In the marsha 10, in response to the REST-EQ (L) command, 1. f- to LB20L
The operation of storing the data (S2 in this example) can be performed.

At this time, the corresponding data (S2) is supplied from the sorter 12 via the sort checker 14 to the marsher 10 in predetermined byte units at a constant cycle, and is held in the INL register 21L in synchronization with this supply cycle. Ru. REST-E
In the case of the Q (L) command, the main control unit 3 of the Marsha 10
The write control tank (not shown) in 8 is the WAL register 25L.
Data is written to LB2OL using . That is, the write control section in the main control section 38 writes the data held in the INL register 21L to the address of LB 20L specified by the WAL register 25L, and
Write control to increment the register 25L by 1 is repeatedly performed.

The WAL register 25L is reset at startup (■REST-EQ (L), ENG in FIG. 10).

(See Go command column), therefore S2 is LB20L.
are written sequentially starting from address O.

In the case of data writing to 3201, the main control unit 38 sets the contents of the R8L register 43L (record length R8L) to the WRC counter 45 via the multiplexer 44 at the start of its operation, and writes the contents of the TRN register 42 (total record length R8L) to the WRC counter 45 via the multiplexer 44. TRN) is set in the STC counter 46. The WRC counter 45 is connected to the WAL register 25L (
In the case of writing to U B 20U, it is decremented by -1 every time the WAtJ register 25U) is incremented by +1. As a result, WR
The C counter 45 enters an underflow state when writing the final data of one record, and outputs a borrow signal. W
The borrow signal from the RC counter 45 is sent to the STC counter 4.
6, and the STC counter 46 is decremented by 1. As a result, the STC counter 46 goes into an underflow state when writing the final data for the final record of S2, and outputs a borrow signal. The borrow signal from the STC counter 46 is commonly led to one end of A67U and 67L. The other end of A 67U has U/ in MOP register 39.
The L bit is guided through the inverter 66, and the U/L pit is directly guided to the other end of A67L. Therefore, in this example, which is U/L-1, the AND condition of A67L is satisfied, and the FLWED flag 51L is output from A67L.
, a logic “1” signal is output. As a result,
The FLWED flag 51L is set (■ in Figure 10).
(See REST-EQ (L), ENG, Go command columns). The write control section in the main control section 38 stops the write control operation in response to the borrow signal from the STC counter 46. As a result, the WAL register 25L of B2 (JI
The count-up operation is stopped at the state (end) indicating the storage address of the final data (of the II record).

In this example, read/write operations for U B20U (L B20L > are performed in a time-sharing manner. That is,
One operation cycle in marsha 10 is divided into two parts: a read cycle and a write cycle. R.E.
In the case of the ST-EQ (L) command, a read control unit (not shown) in the main control unit 38 operates a CMP 28L that compares the contents WAL of the WAL register 25L and the contents RAL of the RAL register 26L, and the contents WAU and WAU of the WAU register 25U. The comparison result of the CMP 28U which compares the content RAU of the RAU register 261J is monitored.

And if RAL<WAL, RAU<WA (J,
The read control unit determines that data can be read from LB 20L, and in the read cycle, the RA
Data read from LB20L using L register 26L and RA (UB20 using J register 26LI)
Data is read from U at the same time, and then RAU
Register 26(], the contents of RAL register 26L are +1
do. At this time, if the FLWED flag 51L is not set, the write control unit uses the WAL register 251 as described above in the next write cycle.
Write data to 20L. Then, the above operation is repeated. The RAU register 26U1RAL register 26L is reset at startup as described above (see Fig. 10), and the T U B 20tJ.
LB20L"oo"""""9Hml, <"Conducted from location 0111.

When reading data from IJB20U and LB20L, when reading the first data of one record, the contents of RAU register 26U and RAL register 26L are stored in BUU register 27U and BUL register 27L, and the contents of R8U register 43U and R8L register 43L are stored in RCtJ counter. 49LI, RCL counter 49L, and VDL
The contents of the register 47 are loaded into the VCT counter 48 at the timing specified by the control timing generation circuit 60 in the main control section 38 to start processing one record. The RCU counter 49tJ, the RCL counter 49tJ, and the VCT counter 48 are U B 20LI.

It is decremented by 1 every time data is read from LB20L. In this example, the records supplied to merge t10 are preprocessed by the IN aligner 13 so that the key field to be compared is at the beginning. therefore,
The VCT counter 48 enters an underflow state when reading the final data of the key field, and outputs a borrow signal indicating the end of the key field. VCT counter 48
The borrow signal from is guided to the comparison control section 62. In addition, the RCU counter 49U and RCL counter 49L are the U side code whose record length is R8U, and the record length is R3L.
When reading the final data of the L side code, an underflow state occurs and a borrow signal indicating the end of the record is output. Borrow signals from the RCU counter 49U and RCt counter 49L are the FUE flag 50U.

It is guided by the FLE flag 50L. As a result, the same flag 5
01J and 50L are set to indicate that the final data of one record is being read.

The data read from UB20U and LB20L is
It is held in the R register 22USLOW register 22L. The data held in the UPR register 22 and the USLOW register 22L is led to the CMP 23. Also, the data held in the UPR register 22U and LOW register 22L is 0TIJ.
IN via register 24LI and OTL register 24L
It is also guided to the UR register 31U and INLR register 31L, and held in the same registers 31U and 31L.

The CMP 23 compares the magnitude of both data from the UPR register 22U% and the LOW register 22L. The comparison result of the CMP 23 is guided to the comparison control section 62 within the main control section 38. A borrow signal indicating the end of the key field from the VCT counter 48 is also guided to the comparison control section 62 . If the comparison result from the CMP 23 is U>L or U<L, the comparison control unit 62 at that point selects the U-side code (in this example, one record in S1) and the L-side code (in this example, Then, the comparison result between the designated key field and the specified key field (one record in S2) is determined, and the comparison result of CMP 23 is transmitted to the control signal generation circuit 65. On the other hand, in the case of U-L,
Since the comparison result cannot be confirmed, the comparison result is not confirmed until the comparison result for the next data is given. However, if the end of the key field (key field end) is detected by the borrow signal from the VCT counter 48, UL is determined and the match detection result from the CMP 23 is transmitted to the control signal generation circuit 65. ,
In the above description, U indicates read data from UB20U, and L indicates read data from 1820L.

On the other hand, INUR register 311J, INLR register 3
The read data from UB20U and LB20L held in 1L is sent to CMP23. In parallel with the comparison operation by U
Written to RB30U and LRB30L. This URB
The write address for the RB 50L is specified by the RAUR register 35U and the RALR register 35L. RAUR register 35U, RALR
Register 35L is cleared when one record is written, so UB20U, LB
Read data from 2OL is URB30U, LRB3
It is written from address O of OL.

The control timing generation circuit 60 in the main control section 38
The states of the E flag 50U and FLE flag 50L are monitored. Then, the control timing generation circuit 60
When it is detected that both the UE flag 50Ui and the FLE flag 50L are set, that is, when the reading of the final data of the record with the longer record length among the U side code and the L side code is detected, (URB3ou (or assuming that reading and outputting one record from the LRB 30L becomes possible) gives timing instructions for outputting various control signals to the control signal generating circuit 65.

The control signal generation circuit 65 is a control timing generation circuit 60.
At the specified timing, the read address for UB20 (J, LB20L, It generates various control signals for controlling the interrupt control section 63, the output control section 64, etc. The control signal generation circuit 65 is, for example, a ROM.

When the control signal generation circuit 65 is determined to perform a RESTRICT system operation by the MRG-OP code (i.e.,
In the case of REST-EQ calculation as in this example) various control signals are output according to the input/output logic shown in FIG. However, the input/output logic in FIG.
) are sorted in ascending order (As/DS-0). In this case, the control signal generation circuit 65
If the comparison result is U<L, the next record is read from the UB 20U, and a control signal is output that instructs the current record to be read again from the LB 20L. This control signal is, for example, RAU register 26U, RAL register 26U,
6m, and in this case, a load signal to the RAL register 26L is output. When a load signal to the RAL register 26L is output, the start address of the current record loaded into the BIJL register 27L (from the RAL register 26L at the start of record processing) is loaded into the RAL register 26L. This results in
In the same way as the data reading from B20L described above,
It becomes possible to read out the current record again in order starting from the first data. On the other hand, the RAU register 26U indicates the address of the next data (in this case, the start address of the next record), and there is no change in the answer. in this case,
In the same way as reading data from the UB20U described above,
It becomes possible to read the next record sequentially starting from the first data. On the other hand, if the comparison result is U-L or U>L, the control signal generation circuit 65 generates a control signal that instructs the current record to be read again from the UB 20U and the next record to be read from the LB 20L. Output. Especially U
-L (that is, the REST-EQ condition is met), the control signal generation circuit 65 outputs an output instruction signal 85L (of logic "1") that instructs the output of the record written in the LR 830L. Further, the control signal generation circuit 65
Interrupt permission signals 74U, 74 valid regardless of comparison results
Outputs 1.

Now, by the control signal from the control signal generation circuit 65, tJ
Reading of the current record from B20U and reading of the next record from LB20L is instructed, and the logic “
It is assumed that the output instruction signal 85L of 1'' is output.The output instruction signal 85L of the logic 111IT from the control signal generation circuit 65 is guided to the FLO flag 53L, thereby setting the FLO flag 53L.

The output sequence control unit 83 monitors the states of the FtJO flag 53U and the FLO flag 53L, and when at least one of the flags 53U and 53L is set,
Output control is performed according to the states of the flags 53U and 53L and the contents of an instruction in an output selection control register (not shown).

For example, the identification number NTID is set by the output selection control register.
FLO is specified as described above.
When the flag 53L is set, the output sequence control section 83 first sends the NTID to the NTID output control section 84N.
Instructs the output of the identification number NTl0 from the counter 32. Further, the output sequence control section 83 outputs a count-up enable signal 90 to the NTID counter 32, regardless of whether or not there is an instruction to add the identification number NTID by the output selection control register.

The Nto ID output control unit BAN is the output sequence control unit 8.
3, output control signal 91N and strobe signal 87N. Output 11iII Ill
Signal 91N is provided to gate 31N of FIG. As a result, the gate 37N is enabled, and the identification number NTID, which is the count value of the NTID counter 32, is
7 to the ROUT register 33.

On the other hand, the strobe signal 87N is passed through OR86.
−“°°′″″I″1・′−“°°°“′″″f! L
IIi+I Ill,... In response to the output permission from the section 89, the output signal from the OR8B (in this example, the strobe signal 87N) is sent to the ROU as the strobe signal 93.
Output to T register 33.

In addition, regarding the control operation of the cutting control section 89, the JOI
We plan to explain N-based operations in detail as an example, and here we will discuss N-based operations in detail.
TID output control unit 84NSLIPB readout control unit 84U
It is assumed that output permission is given to the gate 88 during an output control operation period of either of the LRB readout control section 84L and the LRB readout control section 84L, and a description thereof will be omitted.

When the strobe signal 93, which is the output signal from the gate 88, is output to the ROUT register 33 by the output permission from the cutout control unit 89, the ROUT register 33 (via the gate 37N)
NTID counter 32 (led to T register 33)
The identification number NTID from is latched into the ROUT register 33. The data latched in the ROUT register 33 is then transferred to the HM (not shown) via the HM A 17.

When the NTID output control section 84N finishes outputting the identification number NTID from the NTID counter 32, it notifies the output sequence control section 83 of the end of the output. Thereby, the output sequence control unit 83 instructs the LRB readout control unit 84L to read and output records from the LRB 30L. Note that when the flags 53U and 53L are both set, the output sequence control unit 83
B read control unit 84U and LRB read control unit 84L
A read instruction is given to the output terminals in the output order specified by the output selection control register.

ShiRe! ! The output control section 84L outputs an output control signal 91L in response to an instruction from the output sequence control section 83. This output control signal 91L is guided to gate 37L in FIG. This enables gate 37L. In this state, LRB read control section 84L clears RALR register 35L and CTR counter 56, and then reads data from L R 830L using RALR register 35.1. Furthermore, every time a predetermined byte of data is read from the LRB 30L, the LRBM output control unit 841 increments the contents of the RALR 35L and the CTR counter 56 by 1, and outputs a strobe signal 87L. This strobe signal 87L is supplied to the gate 88 via the OR 86, and is supplied to the ROUT register 33 as a strobe signal 93. As a result, (gate 37L
LRB3 (which is routed to the ROUT register 33 via
The read data from the OL is latched in the ROUT register 33 and sent to the HM via the HM A 17 as described above.
will be forwarded to. During the data read period from LR830L, the next record is read from UB20U and LB20L, and the same record is read in predetermined byte units from URB30U and L.
It is also possible to write from address O of R830L. In this case, read/write operations for U RB50U and L RB50L need to be performed in a time-sharing manner, similar to those for UB20U and LB20L.

In this way, one record of read data from the LR830L (following the identification number NTID) is sent to Marsha 1.
It is assumed that the output starts from 0. At this time, the comparison result of the CMP 59L, which compares the contents of the CTR counter 56 and the record length of the L side ration (S2 in this example) indicated by the R8L register 43L, shows a match. L.R.B.
The read control unit 84L determines the end of read output of one record by detecting a match in the CMP 59L, and notifies the output sequence control unit 83 of the end of output. (In this example where the FUO flag 53U is not set) The output sequence control unit 83 determines the end of the 1-output sequence based on the output end notification from the iRBM output control unit 84L, and outputs the counter strobe signal 92 to the OR 94. do.

0R94 outputs the counter strobe signal 92 from the output sequence controller 83 to the clock terminal GK of the N T ID counter 32 in FIG. 1 as a counter strobe signal 95. The count-up enable terminal E of the NTID counter 32 is supplied with the count-up enable signal 90 from the output sequence control section 83 as described above. Therefore, the NTID counter 32 counts up in response to the counter strobe signal 95. As a result, the identification number NTID is incremented by 1.

The above operation is repeated, and for example, as shown in FIG. 10, the contents of the RAL register 26L are changed to the WAL register 25L.
shall correspond to that of In this case 1:: case,
The CMP 28L, which compares the contents of the WAL register 251F3 and the RAL register 26L, outputs a coincidence detection signal of logic "1". This coincidence detection signal is guided to one end of A68L. FLWED flag 51 on the other end of A68L
The logic 411 I+ output signal from L is led.

This is because the FLWED flag 51L is in the set state as described above. In this case, the AND condition of A68L is satisfied, and a logic "1" signal is output from A68L. This logic "1" signal from A68L is
When writing of the relation to LB20L (S2 in this example) is completed, the RAL register 26L
This indicates that the read address indicated by matches the write address of the WAL register 25L, that is, LB2OL is in an empty state. A logic "1" signal from A68L is directed to gate 691. The gate 69L gates the logic +111+ signal from the A68L at the designated timing (record end detection timing) from the control timing generation circuit 60. As a result, the logic from A68L"
1” signal is output to the FLEMP flag 52L,
The same flag 52L is set. FLEMP flag 52L
The logic ``1'' (set) output signal from is routed to one end of A73L. An interrupt enable signal 74L from the control signal generation circuit 65 is led to the other end of A73L. In this case, the interrupt enable signal 74L is at logic “1” as described above.
(See FIG. 12), so A73L outputs a logic "1" signal.

The logic "1 pass" signal from A73L is led to the interrupt generation circuit 76 via OR75, which causes the interrupt generation circuit 76 to generate an interrupt to CPU II.

The CPU 11 is connected to the interrupt generation circuit 76 in the Marsha 10 (
), the contents of a status register (not shown) in the marsher 10 are read and the cause of the interrupt is determined.

By reading the status from the marsher 10, the CPU 11 determines that LB2OL has become empty, that is, that the operation in the marsher 10 has ended. This also applies when a coincidence detection signal is output from the CMP 28U that compares the contents of the WAU register 25U and the RAU register 26tJ, and the FUEMP flag 52U is set. c p u ii is the relational operation (RES
T-EQ), if you want to know the number of records output from Marsha 10 (if the conditions are satisfied) (or the number of records if output to U (II II and L measuring instruments), then use the following method. The contents of the NTID counter 32 are read.

The CPU 11 first specifies the Marsha 10 as a device, and
Thereafter, command data (REG, IND-1) specifying the NTID counter 32 is output to the input/output bus 18 together with the command signal CMD. The command data on the input/output bus 18 is sent via the input driver 102 in the input/output interface 40 of the marsher 10, and the command signal CMD is sent via the input/output driver 101 to the CMD register 4.
1. Thus, command data specifying the NTID counter 32 is held in the CMD register 41 in response to the command signal CMD. CMD register 41
The command data held in REG
, IND-1, D E C through gate 106
107 and 108.

When the CPU 11 transfers the command data specifying the NTID counter 32, the CPU 11 transfers the read signal RD to the marsher 10 via the input/output bus 18. CPLllll
Is the read signal RD from merge? D E via the input/output driver 101 in the input/output interface 40 of 10
0108. The DEC 108 is enabled by the read signal RD and outputs a decode signal of command data from the CMD register 41 supplied from the gate 106. The above command data is NTI
In this example, which specifies the D counter 32, D E C
An output control signal 110 is output from 108. This output control signal 110 is supplied to a gate 111. The gate 111 has an identification number NTr from the NTID counter 32.
D is supplied. The gate 111 is D E C10
N
Gate the identification number NTID from the TID counter 32. As a result, the identification number N from the NTID counter 32
The TID is output to the output driver 103 via the gate 111, and sent to the input/output bus 18 by the driver 103. i.1: The CPU 11 can know the number of output records (number of sets) by taking in the identification number NTID on the input/output bus 18 and subtracting the initial value from that value.

By the way, when the desired relational calculation is completed, tJB2
There are cases where it is desired to perform another calculation on the data stored in 0U and LB20L. In this case, Marsha 10
Use the Go command to launch MRG only. Specifically, as shown in (■) in FIG. 10, the LJRTRY sequence 1. :MRG with LRTRY specified, Goal cloak, i.e. MRG, Go-LJ
RTRY-LRTRY=1, REG, IND-R3T-
ENG, MRG with Go=O, and Go commands are applied. As shown in the clear circuit 61 of FIG. 7, the URTRY pit is guided to one end of OR80U, and the LRTRY bit is guided to one end of OR80L. Therefore, URTR
In this example with Y-LRTRY=1, 0R80U, 80L
The output level of is logic "1". Therefore, at the start timing from the control timing generation circuit 60, UR
RAU registers 26U and F correspond to the TRY bit.
The UEMP flag 52U is cleared, and the RAL register 26L and FLEMP flag 52m are cleared in correspondence with the LRTRY bit. On the other hand, WAU register 25U
, WAL register 25L, FUWED flag 51U, F
Regarding the LWED flag 51L, the previous state, that is, the first
REST-EQ (L), ENG, G shown in ■ in Figure 0.

Retains the state at the end of command execution. therefore,
Perform a desired operation (in this example, REST) on the data stored in UB20U1LB20L from the first data.
-NE (L) operation). In addition, R
In the EST-NE command, the key field of the condition data is not equal to that of the target relation, and
The U-side data (record) when a record is updated to 820L is to be output.

Next, perform RESTRI CT operations (REST-EQ operations) on the target relation that exceeds the capacity of LB20L.
Item i) will be explained with reference to FIGS. 13 and 14. Furthermore, Fig. 13 is similar to Fig. 10, and Fig. 14 is similar to Fig. 11.
Corresponds to the figure. Now, the first relation as condition data is 81, the target relation (second relation)
is 82. Further, it is assumed that S2 is divided into 821 to 323 depending on the capacity unit of LB20L. It is assumed that the condition data S1 does not exceed the capacity of the UB20U. In this case, first LOAD (U), ENG
, Go commands are given. As a result, the registers and flags related to U320U are cleared (■ in Figure 13).
(See LOAD (U), ENG, Go command columns)1
．． Sl is written in predetermined byte units starting from address 0 of the UB 20U. When the writing of S1 is completed, the CPU 11 sends REST-EQ l), ENG,
A Go command is given. As a result, the registers and flags related to 1820L are cleared (■ in Figure 13).
REST-EQ (L), ENG.

(See Go command column), the operation of writing 821 to the area starting from address O of L82OL is started. L820L
When data writing to u starts, as described above,
Data reading from s20U and LB20L is started, and comparison of key field portions specified by VDL register 47 is performed. And FUE flag 50t
When both the J and FLE flags 50L are set, LI R830U, L is set based on the comparison result between records, MRG, Go command, and AS/DSS/.
Output instructions for records written to RB50L,
and record update is controlled, proceeding to the next record processing. Of course, at this time, output control for the identification number NTID is also performed.

In this way, REST-EQ (L), ENG, G
The operation specified by the O command is executed, for example, the 13th
As shown in the figure and ■ in Fig. 14, the RAL register 2
The contents of 6L match that of WAL register 25L, and C
It is assumed that a coincidence detection signal is output from the MP28L.

In this case, the above-mentioned RESTRICT operation (REST
-EQ) 5°, the FLEMP flag 52L is set and an interrupt is generated for CP'1J11. As a result, the CPU 11 performs S 1
The end of the calculation between and 821 is determined. The CPU 11 is
REST between next 822 and 81 in U B 20U
-For EQ calculation, REST-
Give EQ (L), ENG, and Go commands. However, as for B1, it is necessary to read it again from the first record, so as shown in ■ in FIG. 13, ENG and G with tJRTRY specified.

Commands, namely ENG, GO=URTRY-1, REG
, IND-R8T=MRG, E of Go-LRTRY-0
NG and Go commands are applied.

In this case, when starting up the marsha 10, the clear circuit 61 shown in FIG. 7 causes the RAU register 26kJ and the FUEMP flag 52 to
U is cleared, ENG with logic °゛1''.

WAL register 25L and FLWED flag 5 according to Go bit (and LB20L specified by U/L bit)
1L, RAL register 26L, FLEMP flag 52L
is cleared. Also, WAIJ register 25U, FU
The previous state of the WED flag 51U is maintained.

Therefore, it becomes possible to read S1 already written in the UB 20U from its first record. In addition, correct detection is also possible when all of Sl has been read and the UB 20U is in an empty state. On the other hand, it is clear that data 322 is written to the LB 20L from its first record and read from the same first record.

In this way, REST-EQ (L) as well as UR
The operation specified by the ENG and Go commands specified by TRY is executed, and for example, as shown in Figures 13 and 14, the contents of the RAU register 26U match those of the WAU register 25U, and the contents of the CMP 28tJ match. It is assumed that a detection signal is output.

In this case, the FUEMP flag 52U is set and the Cpl
An interrupt is generated for Jll. Thereby, the CPU 11 determines the end of the calculation between S1 and S22.

c p u ii is the next 823 and 81 in UB20U
In order to perform a REST-EQ operation between the two terminals, the marsher 10 is given REST-EQ (L) and ENG and GO commands specified by URTRY. This allows UB2
The REST-EQ operation between S1 already written in 0U and 823 newly written in LB20L is performed from the first record.

Next, regarding the relational calculation processing by Marsha 10, JO
The case of IN type calculation will be explained as an example. The JOIN type operation is a so-called two-stream input synthesis output type operation in which specified key fields of two relations are compared and a new relation is created using a set where a condition is met. For example, JOIN-E, which is one of the JOIN-based operations,
In the Q operation, two records whose specified key fields match are combined and output as one record. In the JOIN operation by Marsha 10, after storing the first stream in U B 201J by specifying the LOAD (U) operation, and storing the second relation in LB20L by specifying the JOIN (L) operation, the JOIN operation is performed. will be carried out. Then, the specified key field of the read record from UB20U (U side code) is compared with that of the read record from LB20L (L side code),
When the calculation condition is satisfied, an instruction to output the U-side and L-side codes is given from the control signal generation circuit 65. JOI
FIG. 15 shows the input/output logic of the control signal generation circuit 65 in the N-EQ calculation. However, the input/output logic in FIG. 15 is based on the premise that the input relations to the marsher 10 are sorted in ascending order. Note that in JOIN-based operations, the first and second relations are UB20U,
The capacity of L82OL must not be exceeded, and the sorts must be the same. The fact that the sort types are the same means that the REST
The same applies to RICT-based operations.

Now, the read records from U320U and 1B2OL are read from UR830t in parallel with the comparison operation by CMP23.
J, written to LRB30L. When the FUE flag 5oua and the FLE flag 50L are both set, that is, when the reading of the final data of the U-side code and the L-side code are both detected, the control signal generation circuit 6
5 is the above-mentioned RESTRICT system m l[+7)li
(!: Similar 1c, URB30U, LRB
(Instructs to output the record written in '30L and controls record update. In this example of the JOIN-EQ operation, assuming that U-L has been determined by the comparison control unit 62, a control signal is generated. The circuit 65 outputs logic "1" output instruction signals 85U and 85L as shown in the input/output logic of FIG.
U, 85L are FUO flag 53U, FLO flag 53
L, thereby setting the flags 53tJ and 53L. The output sequence control unit 83 monitors the FUO flag 53U and the FLO flag 53L, and when at least one of the flags 53U and 53L is set,
Output control is performed according to the states of the flags 53U and 53L and the contents of an instruction from an output selection control register (not shown).

For example, the identification number NTID is set by the output selection control register.
FUO is specified as described above, and the output order of U-side code → L-side record is specified.
When the flag 53U and FLO flag 53L are set, the output sequence control section 83 first instructs the NTID output control section 84N to output the identification number NTID from the NTID counter 32.

Furthermore, the output sequence control unit 83 controls whether or not there is an instruction to add the identification number NTID by the output selection control register.
A count-up enable signal 90 is output to the NTID counter 32.

The NTID output garden system unit 84N includes an output sequence control unit 8
In response to the instruction from 3, the output control signal 91N and strobe signal 87N are output in the same manner as in the RESTRICT system operation combination described above, and the identification number NTID generated by the NTrD counter 32 is latched in the ROtJT register 33, and externally Output. When the NTID output garden control unit 84N finishes outputting the identification number NTID from the NTID counter 32, the output sequence 1lllltl1 unit 83
Notify the end of output.

As a result, the output sequence control unit 83 instructs the URB readout control unit 841J to read and output records from the URB 30U, and the output sequence control unit 89
Instruct cutout control for the U-side code.

The UR8 readout control unit 84U is the output sequence control unit 8
3, outputs an output control signal 91U.

This output control signal 91U is guided to gate 37U in FIG. This enables gate 37U and U
ROUT register 3 of read data from RB 30U
Output to 3 is permitted. In this state, the UR8 read control unit 84Lj controls the RALIR register 35U and UCTR.
Clear counter 56 and then RAUR register 3
5U is used to read data from URB 30LI. Also, tJRB! The output control unit 84U
Every time a predetermined byte of data is read from 30U, RAUR
Register 35 (J and CTR counter 56 contents +
1 and outputs a strobe signal 87U. CT
The contents of the R counter 56 are CM P 57U to 59U,
Guided by CMP5γL to 59L, 08UA register 54
U, 08IJB register 55U, R8U register 43U
, oSLA register 54L, 08LB register 55L,
It is compared with R8L register 43L. CMP57U, 5
8 (J and CMP57L.

The comparison result of 58L is led to the extraction control section 89.

The extraction control unit 89 receives UllI from the interrupt control unit 63.
If J record extraction control is instructed, CMP57
Monitor U and CMP5aUtr. Then, the extraction control unit 89 controls the contents of the CTR counter 56 (in this example, RAt, I
The contents of the R register 35U, namely 1. If the read address for I R830U is X, then CMP57
During the period in which 08UA≦X≦03UB is detected by tJ, 57LI, output permission is given to the gate 88. That is, the extraction control section 89 normally gives output permission to the gate 89, but the output sequence control section 8
When instructed to cut out ll1IIIl from 3, output permission/prohibition control is performed. As a result, the cutting control section 89
The strobe signal 87tJ from the tJR8 read control unit 134LI is guided to the ROUT register 33 as the strobe signal 93 only during the period when output permission is given from
It is latched in register 33. Therefore, O5'tJ
By setting A (first extraction position) and ○5UB (second extraction position) to appropriate values, it is possible to selectively extract and output only the desired attributes from the U-side code to be output. □The same applies to the L side code.In addition, 03UA (O8LA)-
In the case of 0.08UB, (O3LB)=R3U, data for one record is output as is.

When the read data from the U RB 30U becomes the final data of the corresponding record, the CMP 59U enters an overflow state and a borrow signal is output from the CMP 59U. The URB read control unit 84LJ is the CM P 59jJ
When a borrow signal is output from , it is determined that the record reading has ended, and the output sequence control section 83 is notified of this fact. The output sequence control unit 83 is the URB request control unit 8
When the end is notified from 4tJ and the FLO flag 53L is set as in this example, the LRB read control unit 8
It instructs the 4L to read and output records from the LRB 301, and instructs the extraction control section 89 to perform extraction control for the L-side code. As a result, in the same way as in the above case, 08LA≦X≦0 of the L side code
The data of the field portion satisfying 3LB is cut out and output.

When the LRB readout control unit 84 finishes controlling the readout of one record, it notifies the output sequence control unit 83 to that effect. The output sequence control section 83 determines the end of the 1-output sequence based on the output end notification from the LRB readout control section 84L, and outputs a counter strobe signal 92. This signal 92 is passed through an OR 94 to the clock end of the NTrD counter 32 as a counter strobe signal 95.
Supplied to child CK.

As a result, the contents of the NTID counter 32 (ME-specific number NTID) are incremented by 1.

Thereafter, the JOIN-EQ operation is repeated in the same way,
Each time a condition is met, a set of the corresponding identification number NTID, IJ side record, and L side code is output. Then, when the above calculation is completed, the above RESTRICT
Similar to the system operation operation, the CPU 10 reads the contents of the NTID counter 32 if necessary, and executes JOIN-E.
You can know the output record set for Q operation.

[Effects of the Invention] As detailed above, according to the present invention, various relational calculations can be performed extremely efficiently. Moreover, according to the present invention, a new identifier can be attached to a record (record set) that is output to the outside when a calculation condition is satisfied, so that it can be used for subsequent data processing.

Extremely convenient.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a marsha (relational processing unit) according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a relational database engine (RDBE) to which the marsha of FIG. 1 is applied, and FIG. 3 Figure 4 is a format diagram of merge operation specification information, Figure 4 is a format diagram of command data, and Figure 5 is a format diagram of merge operation specification information.
The figure is a block diagram showing the functional configuration of the main control section shown in FIG. 1, FIG. 6 is a block diagram showing the block configuration around the interrupt control section shown in FIG. 5, and FIG. 7 is the circuit around the clear circuit shown in FIG. 5. Figure 8 is a block diagram of the peripheral area of the output control unit shown in Figure 5, Figure 9 is a block diagram of the input/output interface shown in Figure 1, and Figure 10 is a block diagram of the RESTRICT.
A diagram showing the correspondence between a command sequence for executing system operations (REST-EQ) and the contents of various registers and flags at the time of startup and termination by each command, Part 1
Figure 1 shows the U/L at the end of execution of each command shown in Figure 10.
Figure 12 is a diagram explaining changes in the writing and reading positions to the buffer.
Figures 13 and 14 show examples of the input/output logic of the control signal generation circuit when ST-EQ) is specified.
The figure corresponds to Figures 10 and 11, and shows R when the target relation exceeds Marsha's buffer capacity.
FIG. 15 is a diagram for explaining an ESTRICT (constraint) type operation; and FIG. 15 is a diagram showing an example of input/output logic of the control signal generation circuit when a JOIN type operation (JOIN-EQ) is specified. , -10
...Marsha, 11...CPU, 20U...U buffer, 20L...L buffer, 23.28LJ,
281, 57U-59U. 571-591... Comparator (CMP), 27U...
8UU register, 21L...BUL register, 30L
J...URBba'''・30L°LRBzEy 77・
32°-N T I D''l'unta, 38...
・Main control unit, 39...MOP register, 41...C
MD register, 42...TRN register, 43tJ・
...R8U register, 431...R8L register, 4
7...■DL register, SOU...FUE flag,
50L...FLE flag, 51U...FtJWED
Flag, 51L...FLWED flag, 52U...
FUEMP flag, 52L...FLEMP flag, 5
3U...FUO flag, 53L...FLO flag,
541J...08UA register, 54L...08L
A register, 55U...03UB register, 55L.
・・03LB register, 61・・Clear circuit, 62・
...Comparison control section, 63...Interrupt control section, 64...
Output control unit, applicant: Director of the Agency of Industrial Science and Technology Tatsu Todoroki Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 1 Rei°1 wholesale IP38 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 12 Fig. 13 Figure 14 Figure 15

Claims (1)

[Claims] A first buffer that stores the first relation, a second buffer that stores the second relation, an operation code that indicates the operation type, and a buffer designation bit that designates either the first or second buffer. a first register to hold, a second register to hold the number of records forming the relation stored in the first or second buffer, and a record of the records forming the relation stored in the first or second buffer. Load processing is specified by a third register that holds record length information indicating the length, a fourth register that holds key field length information that indicates the key field length of the relation, and the operation code held in the first register. , the buffer specified by the buffer specification bit among the first or second buffer is
Means for writing the relation of the amount of data indicated by the number of records specified by the second register and the record length specified by the third register, and relational operation using the operation code held in the first register. If processing is specified, the number of records specified by the second register and the record length specified by the third register are stored in the first or second buffer specified by the buffer specification bit. means for writing the relation having the amount of data represented by , while reading data one record at a time from the first and second buffers; and a third means for temporarily storing one record's worth of data read from the first buffer. a buffer, a fourth buffer for temporarily storing data for one record read from the second buffer, a counter whose initial value can be set from the input/output bus during relational calculation processing, and a counter from the first and second buffers. a comparison circuit that compares both read records between the key fields specified in the fourth register; a first output control means that controls the updating of read addresses for the first and second buffers, and controls the output of both or one of the records temporarily stored in the third and fourth buffers to the outside; When the first output control means outputs a record, the second output control means outputs the contents of the counter to the outside as an identifier of the output record, and the counter is updated in accordance with the record output by the first output control means. A relational arithmetic processing device comprising: counter control means.