JPH0370824B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device particularly suitable for relational operations required in relational database processing.

[Technical background of the invention and its problems] One of the main processes in a relational database is a relational operation between two relations. Known relational operations include join, restriction, and projection. In this type of relational operation, the output does not necessarily require all the attributes of the original relation record, but often only a part of them. Therefore, there has been a demand for a hardware device that can cut out only specific fields in a record at high speed.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a data processing device that can selectively output only desired fields in records that are particularly handled in relational operations at high speed.

[Summary of the Invention] In the present invention, a record buffer is provided to store data for one record. The data for one record stored in this record buffer is output to the outside by the read control section. Further, in the present invention, a first cutout pointer that specifies a first cutout position of the external output target record and a second cutout pointer that specifies the second cutout position of the external output target record are provided. The contents of the first extraction pointer are compared by the first comparator with the read address presented to the record buffer from the read control unit. On the other hand, the contents of the second extraction pointer are determined by the second comparator,
It is compared with the above read address. The comparison results of the first and second comparators are led to the extraction control section. The extraction control section controls the operation of the readout control section according to the comparison results of the first and second comparators.
As a result, only the specified field in one record is selectively output to the outside.

[Embodiment of the invention] FIG. 1 shows a merger 1 according to an embodiment of the invention.
0, and FIG. 2 shows the configuration of merger 10 in FIG.
A relational database engine that applies
RDBE). RDBE in Figure 2
, 11 is a CPU that controls the entire RDBE,
12 is a sorter (sort processing device) that applies a two-way merge sort method. Sorter 12 is 12
It consists of tiered sort cells 12-0 to 12-11, and is capable of sorting up to 4K records. 13 is an IN aligner (sort preprocessing device) provided on the input side of the sorter 12 and performs presort processing such as moving key fields to be compared to the beginning of records in sort processing; 14 is a sorting unit for the IN aligner 13; It is a sort checker that monitors whether the results are correct or not.
The merger 10 is connected to the sort checker 14 and is sorted by the sorter 12.
The system is configured to perform relational operations between one or two relations at high speed. The IN aligner 13, sorter 12, sort checker 14, and merger 10 constitute an engine core 15, which is dedicated hardware that performs pipeline processing synchronized with input data by sequentially performing sort processing and relational calculation processing. do. 16 and 17 are HM adapters (hereinafter referred to as HMA) that control the interface between the RDBE and a hierarchical memory subsystem (hereinafter referred to as HM), not shown. HMA16
operates as an input port for data to the engine core 15, and HMA 17 operates as an output port for data from the engine core 15. 18 is CPU1
1 is an input/output bus, and 19 is a DMA bus. Each component of the engine core 15 including the merger 10, the CPU 11, and the HMAs 16 and 17 are connected to the input/output bus 18, and the DMA bus 19
A CPU 11 and HMAs 16 and 17 are connected to the .

As shown in FIG. 1, the merger 10 includes a calculation unit
OPP, output selection part OSP, and these calculation part OPP
and the control unit CNTP that controls the output selection unit OSP
It consists of.

In the arithmetic unit OPP, 20U is a U (Upper) buffer (hereinafter referred to as U) that stores the first relation.
20L is an L (Lower) buffer (hereinafter referred to as LB) that stores the second relation. 21U is an input register (INU register) that holds data to be written to UB20U, 21
L is an input register (INL register) that holds data to be written to LB20L, 22U is UB2
The register that holds the read data from 0U (UPR register), 22L is the register that holds the read data from LB20L (LOW register)
It is. 23 is UPR register 22U and LOW
A comparator (hereinafter referred to as CMP) that compares the contents of register 22L, 24U is UPR register 2
An output register (OTU register) transmits the contents of 2U to the output selection unit OSP side, and an output register (OTL register) 24L transmits the contents of the LOW register 22L to the output selection unit OSP side. 25
U is a write address register (WAU register) as a write pointer to UB20U, 2
5L is a write address register (WAL register) as a write pointer for LB20L. 26U is a read address register (RAU register) as a read pointer for UB20U, and 26L is a read address register (RAL register) as a read pointer for LB20L. WAU register 25U, WAL register 25L, RAU register 26U, and RAL
The register 26L has a counter function. 27
U is a backup register (BUU register) that holds the contents of RAU register 26U, and 27L is a
This is a backup register (BUL register) that holds the contents of the RAL register 26L. 28U
is WAU register 25U and RAU register 2
Comparator (CMP) that compares each content of 6U, 28L
is WAL register 25L and RAL register 26
This is a comparator (CMP) that compares each content of L.
29U is a multiplexer that selects the contents of WAU register 25U or RAU register 26U as the memory address for UB20U, and 29L is
WAL register 25L or RAL register 26L
This is a multiplexer that selects the contents of as the memory address for LB20L.

In the output selection section OSP in Figure 1, 30U is
The U record buffer (URB30) and 30L that store one record of data from UB20U are
This is an L record buffer (LRB30) that stores one record worth of data from LB20L. 3
1U stores the contents of OTU register 24U as URB30U.
Input register (INUR register) held as write data for 31L is OTL register 2
Input register (INLR register) that holds the contents of 4L as write data to LRB30L
It is. 32 is a multiplexer for selecting read data from URB30U or LRB30L; 3
3 is an output register (ROUT register) that latches selected output data from the multiplexer 32. 34U is a write address register (WAUR) as a write pointer for URB30U.
34L is a write address register (WALR register) as a write pointer to the LRB 30L. 35U is URB30
Read address register (RAUR register) as read pointer for U, 35L is LRB3
This is a read address register (RALR register) as a read pointer for 0L.
WAUR register 34U, WALR register 34
L, RAUR register 35U, and RALR register 35L have a counter function. 36U is
WAUR register 34U or RAUR register 3
The multiplexer 36L selects the contents of 5U as the memory address for URB 30U.
WALR register 34L or RALR register 3
This is a multiplexer that selects the contents of LRB 5L as a memory address for LRB 30L.

In the control unit CNTP shown in FIG. 1, 38 is a main control unit forming the center of the control unit CNTP, and 39 is an 8-bit merge operation register (MOP register) provided within the main control unit 38. M0P register 3
As shown in Figure 3, 9 contains a 5-bit merge operation specification code (MRG-OP code) that specifies the merge operation, a sort order specification bit (AS/DS bit) that specifies the sort order, and UB20.
Merge operation designation information including a buffer designation bit (U/L bit) designating U or LB20L is set. In this example, AS/DS=0 specifies ascending order, and AS/DS=1 specifies descending order. Also,
UB20U when U/L=0, LB2 when U/L=1
0L is specified.

40 is an input/output interface which is an interface to the CPU 11, and 41 is a command register (CMD register) provided in the input/output interface 40. 8-bit command data is set in the CMD register 41 according to a designation from the CPU 11. The 0th bit of this command data is a register designation bit (REG.IND bit), as shown in FIG. REG.
The IND bits are the 0th to 7th bits of command data that are used as data to specify the register (register number) in the merger 10 (REG.
IND=1) or used as the original operation specification data of the command data (REG.IND
= 0). When REG.IND=0, as shown in Figure 4, the second
The bit is a reset specification bit (RST bit) that specifies the reset of the engine core 15, the third bit is the engine start specification bit (ENG.GO bit) that specifies the startup of the engine core 15, and the fourth bit is only for the merger 10. The merger start specification bit (MRG.GO bit) specifies the start of
The seventh bit is used as an L retry designation bit (LRTRY bit) to designate clearing of the RAL register 26L and FLEMP 52L, which will be described later. Note that the operation designation of each bit described above is valid at logic "1".

Referring again to FIG. 1, 42 is a total record number register (TRN register) indicating the total number of records (TRN) of relations (streams) stored in the UB20U or LB20L, and 43U is a total record number register (TRN register).
A record size register (RSU register) indicates the record length RSU of the relation stored in the UB 20U, and a record size register (RSL register) 43L indicates the record length RSL of the relation stored in the LB 20L. 44 is RSU
A multiplexer 45 that selects the contents of the register 43U or RSL register 43L loads the selected output data from the multiplexer 44 as an initial value, and a write counter (WRC) that counts down when writing to the UB20U or LB20L.
46 is a record number counter (STC counter) that is loaded as an initial value from the contents of the TRN register 42 and counted down in response to a borrow signal from the WRC counter 45. 47
is a valid data length register (VDL register) indicating the length of the key field in the record (valid data length VDL) to be compared in the merge operation, 48
is a valid data length counter (VCT counter) that loads the contents of the VDL register 47 as an initial value and counts down when reading data from LB 20U (and LB 20L). MOP register 39, CMD register 41, TRN register 4
2. RSU register 43U, RSL register 43L,
and VDL register 47L are CPU1 in FIG.
1, it can be set up in advance.

49U is a read counter (RCU counter) that loads the contents of the RSU register 43U as an initial value and counts down when reading data from the UB20U. 49L loads the contents of the RSL register 43L as an initial value and reads data from LB20L. This is a read counter (RCL counter) that counts down at the same time. 50U is set in response to a borrow signal from RCU counter 49U,
Record end flag (FUE flag) indicating that the read data from UB20U is the last data of one record, 50L is RCL counter 49L
LB20 is set in response to a borrow signal from LB20.
This is a record end flag (FLE flag) indicating that the data read from L is the last data of one record. 51U is a write completion flag (FUWED flag) indicating that writing to UB 20U is completed, and 51L is a write completion flag (FLWED flag) indicating that writing to LB 20L is completed. 52U is an empty flag (FUEMP flag) indicating that UB20U is empty, and 52L is an empty flag (FLEMP flag) indicating that LB20L is empty.
flag). 53U is an output instruction flag (FUO) that instructs external output of data from UB20U.
flag), 53L is an output instruction flag (FLO flag) that instructs external output of data from LB20L.
It is.

54U is a register (OSUA register) as an extraction pointer that specifies the first extraction position for the record read from the URB 30U, 54L
is a register (OSLA register) as an extraction pointer that specifies the first extraction position for the read record from LRB30L, and 55U is URB3.
55L is a register (OSLB register) that serves as an extraction pointer that specifies the second extraction position for the record read from LRB 30L. be. 56 is URB30U or LRB
A counter (CTR counter) that counts up when reading data from 30L, 57U is CTR
Comparator (CMP) that compares the contents of counter 56 and OSUA register 54U, 57L is CTR
This is a comparator (CMP) that compares the contents of the counter 56 and the OSLA register 54L. 58U is
CTR counter 56 and OSUB register 55U
Comparator (CMP), 58L, which compares each content of
CTR counter 56 and OSLB register 55L
59U is a comparator (CMP) that compares each content of
A comparator (CMP) 59L compares the contents of the CTR counter 56 and the RSU register 43U.
This is a comparator (CMP) that compares the contents of the CTR counter 56 and the RSL register 43L.
OSUA register 54U, OSUB register 55U,
OSLA register 54L, OSLB register 55L
can be set up in advance by the CPU 11 shown in FIG.

Next, the configuration of the main control section 38 shown in FIG. 1 will be explained with reference to FIG. 5. In Figure 5, 60 is
A control timing generation circuit 61 determines the timing of generating various control signals according to the FUE flag 50U and FLE flag 50L, as well as the CMD register 41, etc., and 61 is the MOP register 39 and
This is a clearing circuit that clears each section according to the contents of the CMD register 41 at the timing of a start instruction from the control timing generation circuit 60. 62 is
A comparison control unit 63 is the CPU 11 shown in FIG.
This is an interrupt control unit that generates interrupts for.
Reference numeral 64 indicates an output control unit that controls the output of data to the outside, and 65 indicates an output control unit that controls the output of the UB20U at a timing according to an instruction from the control timing generation circuit 60 according to the content of the MOP register 39 and the comparison result of the comparison control unit 62. This is a control signal generation circuit that generates various control signals for read control, LB20L read control, interrupt control, output control, etc.

Next, the configuration around the interrupt control section 63 in FIG. 5 will be explained with reference to FIG. 6. In FIG. 6, 66 is an inverter to which the U/L bit from the MOP register 39 is input, 67U is an AND gate (A) to which the output of the inverter 66 and the borrow signal from the STC counter 46 are input, and 67L is an
This is an AND gate (A) to which the U/L bit from the MOP register 39 and the borrow signal from the STC counter 46 are input. The FUWED flag 51U is set according to the output signal from A67U, and the FLWED flag 51L is set according to the output signal from A67L. 68U is
CMP28U comparison results (match detection signal) and
AND gate (A) to which the output signal from FUWED flag 51U is input, 68L is the comparison result (match detection signal) of CMP28L and FLWED flag 5
This is an AND gate (A) into which the output signal from 1L is input. 69U is a gate that gates the output signal from A68U at the specified timing from the control timing generation circuit 60, and 69L is a gate that gates the output signal from A68L at the specified timing from the control timing generation circuit 60.
FUEMP flag 52U is gate 69U, FLEMP
Flag 52L is set in response to the output signal from gate 69L. A decoder 70 decodes the contents of the MOP register 39 (merge operation designation information). When the merge operation specification information specifies loading the first relation to the UB 20U, the decoder 70 sends the load signal 71U to
If loading of the second relation to LB 20L is specified, a load signal 71L is output.

72U is the load signal 71U from the decoder 70
and the AND gate (A) to which the output signal from the FUWED flag 51U is input, 72L is the decoder 7
Load signal 71L from 0 and FLWED flag 51
This is an AND gate (A) into which the output signal from L is input. 73U is the interrupt permission signal 74U from the control signal generation circuit 65 and the FUEMP flag 52
The AND gate (A) 73L receives the output signal from the control signal generating circuit 65 and the output signal from the FLEMP flag 52L. The interrupt permission signals 74U and 74L are sent to the control signal generation circuit 65 according to the contents of the MOP register 39.
generated from. For example, when a SORT type operation or a RESTRICT type operation is specified, interrupt enable signals 74U and 74L are output, and when a JOIN type operation is specified, an interrupt enable signal is output. Only 74U is specified.
Furthermore, when a PASS type operation is specified, if U/L=0 (i.e., UB20U specified), the interrupt enable signal 74U is set to U/L=1 (i.e., UB20U is specified).
LB20L specification), interrupt enable signal 74L
is output. 75 is A72U, A72L, A7
An OR gate (OR) 76 to which each output signal from 3U and A73L is input is an interrupt generation circuit that generates an interrupt in response to an output signal from OR75.

Next, the structure around the clear circuit 61 in FIG.
This will be explained with reference to FIG. In Figure 7, 7
7 is an inverter to which the U/L bit from the MOP register 39 is input, and 78U is an AND gate (A) to which the output signal from the inverter 77 and the ENG.GO bit in the command data held in the CMD register 41 are input. ), 78L is an AND gate (A) to which the U/L bit from the MOP register 39 and the ENG.GO bit are input. 79
U is the output signal from A78U and CMD register 4
OR gate (OR) into which the RST bit from 1 is input, 79L is the output signal from A78L and the above
This is an OR gate (OR) into which the RST bit is input. 80U is the output signal from OR79U and CMD
The OR gate (OR) 80L receives the URTRY bit from the register 41 and is an OR gate (OR) to which the output signal from the OR 79L and the LRTRY bit from the CMD register 41 are input.
81U converts the output signal from OR79U into WAU
A gate that gates at a specified timing from the control timing generation circuit 60 as a clear signal for the register 25U and the FUWED flag 51U;
81L converts the output signal from OR79L to WAL
This gate is gated at a specified timing from the control timing generation circuit 60 as a clear signal for the register 25L and FLWED flag 51L. 82U receives the output signal from OR80U,
RAU register 26U and FUEMP flag 52
As a clear signal for U, the gate 82L gates at the specified timing from the control timing generation circuit 60 receives the output signal from OR80L.
RAL register 26L and FLEMP flag 52L
This is a gate that is gated at a specified timing from the control timing generation circuit 60 as a clear signal for the control timing generation circuit 60.

Next, the configuration around the output control section 64 in FIG. 5 is as follows.
This will be explained with reference to FIG. In Figure 8, 8
3 depends on the status of FUO flags 53U and 53L.
Output sequence control unit that controls the output order of data from URB30U, 30L, 84U is URB3
A URB read control unit 84L controls data read from 0U, and an LRB read control unit 84L controls data read from LRB 30L. The URB readout control units 84U and 84L start record readout control operations in response to a readout start instruction from the output sequence control unit 83, and the CMP59U and 84L shown in FIG.
The read control operation is stopped according to the comparison result (coincidence detection signal) of 59L. Also, FUO flag 53
U and 53L are set according to output instruction signals 85U and 85L from control signal generation circuit 65. 8
6 is a strobe signal 87 (for the R0UT register 33) from the URB readout control units 84U and 84L.
OR gate where U and 87L are input, 88 is OR
A gate 89 gates the output signal from 86 and outputs it to the ROUT register 33, and 89 is an extraction control section. The cutting control unit 89 follows the instructions from the output sequence control unit 83 to
Or monitor the comparison results of CMP57L and 58L,
The gate 88 is controlled according to the monitoring result.

Next, the operation of the above configuration will be explained with reference to FIGS. 9 to 13, taking as an example the case of sorting that exceeds the capacity of the sorter 12 shown in FIG. 2 (this is referred to as external sort). .

First, the concept of external sorting will be explained. In the RDBE shown in FIG. 2, relations (streams, files) exceeding the capacity of the sorter 12 are sorted using an external sorting function. At this time, the relations to be sorted are not shown.
Read from HM, HMA16, IN aligner 13
and is guided to the sorter 12 via. After being sorted into buffer size units by the sorter 12, they are led to the merger 10 via the sort checker 14, where they are sorted into larger units. FIG. 9 shows an outline of the above-described external sorting procedure. That is, assuming that the original relation to be sorted is A1, the outline of the external sorting procedure is as follows. It is assumed that the buffer size of the sorter 12 (capacity of the sorter 12) and the buffer size of the UBs 20U and 20L in the merger 10 are equal.

The original relation A1 is divided into capacity units of the sorter 12, A11 to A1n (in this example, n=
4) is obtained.

A11 to A14 are respectively sorted by the sorter 12 to obtain A21 to A24.

A21 and A22 are sorted by the merger 10 to obtain A31 and A32. Similarly, A23,A
A33 and A34 are obtained from 24.

A31, A32 and A33, A34 are sorted as two sets of relations by the merger 10, and finally a relation A4 obtained by sorting the original relation A1 is obtained.

In this way, to sort relations that exceed the capacity of the sorter 12, first divide the relations to be sorted into units of the capacity of the sorter 12, and use the merger 10 to perform external sorting for each of the two sets of divided relations. You can start with this. When this operation is repeated, finally the sub-relation S1
1, S12, .
S22...Second relation S consisting of S2m
2 (in the example of FIG. 9, a relation consisting of A33 and A34) is obtained. As is clear, sorting has been completed within relations S1 and S2. And the first relation S1
and the second relation S2, merger 10
As shown in Figure 10, by merging using the external sort function of
An output (sorted) relation S3 consisting of 31, S32...S3l (l=n+m) is obtained.

Next, regarding the concrete operation of the external sort described above, in the case of n=m=3, that is, the subrelation S
11, S12, S13, and sub-relations S21, S2.
Taking as an example the case of external sorting on the second relation S2 consisting of S2 and S23, explanation will be made with reference to FIGS. 11 to 13. In addition, FIG. 11 shows a sequence of commands for executing the above-mentioned external sort, and the FUWED flag 51U, WAU register 25U, RAU register 26U, FLWED flag 51L, WAL register 25L, The correspondence relationship with each content (state) of the RAL register 26L is shown. In FIG. 11, ~ indicates the order of command execution. Moreover, FIG. 12 is a diagram explaining changes in the write position (solid line) and read position (broken line) to the UB20U and LB20L at the end of execution of each command shown in FIG. 11, and FIG. 6 is a diagram showing the input/output logic of the control signal generation circuit 65 when the EX operation) is specified. FIG.
First, setup for S11 is performed on CPU1
This is done according to instructions from 1. That is, CPU1
1 specifies the merger 10 as a device, and then command data is transferred to the merger 10 via the input/output bus 18. Command data from the CPU 11 is held in a CMD register 41 provided in an input/output interface 40 within the merger 10. In this case, the command data is the 0th
The REG.IND bit is set to logic "1" and specifies a register (register number) within merger 10. When the CPU 11 specifies a register using the above-mentioned command data, it sends the data (setup data) to be set in the corresponding register onto the input/output bus 18 along with a write signal. Thus, the data on the input/output bus 18 is set in the corresponding register in the merger 10 specified by the command data held in the CMD register 41 in response to the write signal.

In this example, CMD register 41 is REG.IND
When the bit is logical "1", the count is increased in response to a write signal from the CPU 11. Therefore, if the register numbers of the registers to be set up are consecutive, once the device is specified for the merger 10 and the command data is transferred, it is simply written along with the desired data (setup data). It is only necessary to repeatedly output the signal onto the input/output bus 18. In this way, for example, the MRG-OP code specifying load of a relation is stored in the MOP register 39.
Merge operation specification information (LOAD (U) command) including the logic "0" U/L bit specifying UB20U is set, information indicating the first field position of the record is set in the OSUA register 54U, and information is set in the OSUB register 55U. Information indicating the last field position of the record (i.e. record length)
RSU) is set. Also, RSU register 4
Record length RSU (first relation S1
The record length of each record in
The effective data length VDL indicating the key field length in the record is set in the VDL register 47, and the TRN
The total number of records TRN of S11 is set in the register 42. Note that (true value - 1) is actually adopted as RSU, VDL, and TRN.

Next, the CPU 11 again specifies the merger 10 as a device, and this time the REG.IND bit is set to logic “0”.
The command data is set in the CMD register 41 in the input/output interface 40 of the merger 10. This command data is an ENG.GO command whose third bit, the ENG.GO bit, is set to logic "1". In addition, RST bit, MRG.GO bit, URTRY bit, and
The LRTRY bit is a logic "0". Above ENG.
The GO command is for engine core 15.
This is a GO command, and the relation (stream data) from HMA 16 is sent to IN aligner 13.
It is input to the merger 10 via the sorter 12 and sort checker 14, and is subjected to a merge operation to be converted to HMA1.
Used when outputting to 7. In this case, the merger 10 will perform data processing using data newly stored in the UB 20U or LB 20L. On the other hand, the MRG.GO command is prepared as a GO command for only the merger 10. In this MRG.GO command, UB
Processing is performed on significant data already stored in 20U or LB20L.

Merger 10 is activated by the ENG.GO command set in CMD register 41. At this time, the clear circuit 61 clears (resets) the WAU register 25U, RAU register 26U, FUWED flag 51U, and FUEMP flag 52U. That is, the U/L bit of the merge operation specification information set in the MOP register 39 is logic "0", and the command data (REG.IND=0) set in the CMD register 41 is set to logic "0".
When the ENG.GO bit is logic “1”, the AND condition of A78U in the clear circuit 61 is satisfied, and A7
A logic "1" signal is output from 8U. A78
The logic “1” signal from U is led to gate 81U via OR79U, and also to OR79U, 80
It is guided to gate 82U via U. gate 81
U and 82U gate the logic "1" signal at the clear timing by the start timing generation function of the control timing generation circuit 60. A logic "1" signal from gate 81U is guided to WAU register 25U and FUWED flag 51U, and a logic "1" signal from gate 82U is guided to RAU register 26U and FUEMP flag 52U. As a result, WAU register 25U, RAU
Register 26U, FUWED flag 51U, and
FUEMP flag 52U is cleared. In this state, the merger 10 stores the information in the MOP register 39.
Data processing specified by the LOAD (U) command is performed at a speed synchronized with input to the engine core 15. This data processing will be described below.

In the merger 10, in response to the LOAD (U) command, an operation is performed under the control of the main control unit 38 to store data (S11 in this example) in the UB 20U. At this time, the corresponding data (S11) is
The data is supplied from the sorter 12 via the sort checker 14 to the merger 10 in predetermined byte units at a constant cycle. The data from the sort checker 14 is held in the INU register 21U in synchronization with the output cycle from the sort checker 14, and is stored in the INU register 21U.
guided by. In the case of the LOAD (U) command, the main control unit 38 uses the WAU register 25U to
Data is written to 20U. That is, a write control section (not shown) in the main control section 38 is an INU
The data held in the register 21U is transferred to the WAU register 2 selected by the multiplexer 29U.
Write to the address of the UB 20U specified by 5U, and write control to increment the WAU register 25U by 1 is performed repeatedly. WAU register 25U
is reset at startup as described above (see Figure 11), so S11 is UB20U.
are written sequentially starting from address 0.

When writing data to the UB20U, the main control unit 38 writes the RSU register 43U at the start of the operation.
The contents (record length RSU) of multiplexer 4
4 to WRC counter 45, and TRN
The contents of register 42 (total number of records TRN)
The STC counter 46 is set. WRC counter 45 indicates that WAU register 25U (WAL register 25L in case of writing to LB20L) is +
Each time it is 1, it is decremented by -1. As a result, the WRC counter 45 enters an underflow state when writing the final data of one record, and outputs a borrow signal. The borrow signal from WRC counter 45 is STC
The STC counter 46 is thereby decremented by -1. Therefore, the STC counter 46 enters an underflow state when writing the final data of the final record in S11, and outputs a borrow signal. The borrow signal from the STC counter 46 is commonly led to one end of A67U and 67L. A
The other end of 67U has U/ in MOP register 39.
L bit is led through inverter 66 and A6
The above U/L bit is directly led to the other end of 7L. Therefore, in this example where U/L=0, the AND condition of A67U is satisfied, and a signal of logic "1" is output from A67U to the FUWED flag 51U. This will cause FUWED flag 5
1U is set (LOAD (U) in Figure 11,
(See ENG.GO command column). The write control section in the main control section 38 stops the write control operation in response to the borrow signal from the STC counter 46. As a result, the WAU register 25U stops counting up while indicating the storage address of the final data (of the final record) in S11. In FIG. 11, the above-mentioned WAU register 25
Like the contents of U, "end" indicates that the contents of the corresponding register at the end of execution of the corresponding command will be the storage address of the final data (of the final record) of the subrelation.

The set output signal from FUWED flag 51U is routed to one end of A72U. A load signal 71U from the decoder 70 is guided to the other end of A72U. The decoder 70 is the MOP register 39
The contents of MOP register 39 are decoded,
In the case of the LOAD (U) command as in this example, a load signal 71U of logic "1" is output. Therefore, in this example, by setting the FUWED flag 51U, the AND condition of A72U is satisfied, and A7
From 2U (by executing the LOAD(U) command)
A logic "1" signal indicating completion of writing to the UB20U is output. The logic "1" signal from A72U is led to the interrupt generation circuit 76 via OR75, and thereby the interrupt generation circuit 76 is connected to the CPU.
Generates an interrupt for 11. CPU11 is
When an interrupt is received from the merger 10 (the interrupt generation circuit 76 therein), a stator register (not shown) in the merger 10 (this register consists of a FUWED flag 51U, a FLWED flag 51L, a FUEMP flag 52U, a FLEMP flag 52L, etc.)
The contents of the interrupt are read and the cause of the interrupt is determined.

When the CPU 11 determines the completion of writing of the sub-relationship S11 to the UB 20U by reading the status from the merger 10, the CPU 11 writes the next sub-relationship, that is, S2 in the second relation.
Perform setup regarding 1. The setup in this case is substantially the same as the setup related to S11 described above. In addition, the effective data length VDL
is common to each record of the first relation S1 and the second relation S2, so setup is unnecessary except in the case of S11. Therefore, the registers to be set up in S21 are the MOP register 39, the OSLA register 54L, the OSLB register 55L, the RSL register 43L, and the TRN register 42.
However, the MOP register 39 specifies the MRG-OP code that specifies external sorting and the sort order.
AS/DS bit, logic “1” specifying LB20L
Merge operation designation information (SORT-EX(L) command) including the U/L bit of is set.
Then, in the CMD register 41 in the merger 10,
As in the case of S11, the merger 10 is activated again by setting the ENG.GO command. At this time, the clear circuit 61
WAL register 25L, RAL register 26L,
FLWED flag 51 and FLEMP flag 52
L is cleared (reset). That is, the U/L bit of the merge operation designation information set in the MOP register 39 is logic "1", and the command data set in the CMD register 41 (however, REG.IND=
If the ENG.GO bit in 0) is logic “1”,
The AND condition of A78L in the clear circuit 61 is satisfied, and a signal of logic "1" is output from A78L. The logic “1” signal from A78L is OR7
While being led to the gate 81L via 9L,
It is led to gate 82L via OR79L and 80L. The gates 81L and 82L gate the logic "1" signal at the clear timing by the start timing generation function of the control timing generation circuit 60. The logic "1" signal from gate 81L is guided to WAL register 25L and FLWED flag 51L, and the logic "1" signal from gate 82L is guided to WAL register 25L and FLWED flag 51L.
The signal is directed to RAL register 26L and FLEMP flag 52L. As a result, the WAL register 25L, RAL register 26L, FLWED flag 51L, and FLEMP flag 52L are cleared. In this state, the merger 10 performs data processing specified by the SORT-EX(L) command in the MOP register 39. This data processing will be described below.

In the merger 10, in response to the SORT-EX (L) command, under the control of the main control unit 38, LB20L
An operation of storing data (in this example, S21) is performed. At this time, the corresponding data S21 is
The data is supplied from the sorter 12 via the sort checker 14 to the merger 10 in predetermined byte units at a constant cycle, and held in the INL register 21L in synchronization with this supply cycle. In the case of the SORT-EX (L) command, a write control section (not shown) in the main control section 38 of the merger 10 writes data to the UB 20U using the WAL register 25L. That is, the write control unit in the main control unit 38 writes the data held in the INU register 21L to the address of the LB 20L designated by the WAL register 25L, and repeatedly performs write control to increment the WAL register 25L by 1. WAL register 25L
is reset at startup (see Figure 11).
(See SORT-EX, ENG.GO command column) Therefore, S21 is written in order from address 0 of LB20L.

When writing data to LB20L, the main control unit 38 writes the RSL register 43L at the start of the operation.
The contents (record length RSL) of multiplexer 4
4 to WRC counter 45, and TRN
The contents of register 42 (total number of records TRN)
The STC counter 46 is set. WRC counter 45 indicates that WAL register 25L (WAU register 25U in case of writing to UB20U) is +
Each time it is 1, it is decremented by -1. As a result, the WRC counter 45 enters an underflow state when writing the final data of one record, and outputs a borrow signal. The borrow signal from WRC counter 45 is STC
The STC counter 46 is thereby decremented by -1. Therefore, the STC counter 46 enters an underflow state when writing the final data of the final record in S21, and outputs a borrow signal. The borrow signal from the STC counter 46 is commonly led to one end of A67U and 67L. A
The other end of 67U has U/ in MOP register 39.
L bit is led through inverter 66 and A6
The above U/L bit is directly led to the other end of 7L. Therefore, in this example where U/L=1, the AND condition of A67L is satisfied, and a logic "1" signal is output from A67L to the FLWED flag 51L. This causes FLWED flag 5
1L is set (SORT-EX in Figure 11).
(L), see the ENG.GO command column). Main control section 3
The write control section in 8 stops the write control operation in response to the borrow signal from the STC counter 46. As a result, the WAL register 25L is
The count-up operation is stopped at the state (end) indicating the storage address of the final data (of the final record).

In this example, read/write operations for UB20U (LB20L) are performed in a time-division manner. That is, one operation cycle in merger 10 is divided into two parts: a read cycle and a write cycle. In the case of the SORT-EX (L) command, the read control unit (not shown) in the main control unit 38
The CPU 28U compares the contents WAL of the register 25L and the contents RAL of the RAL register 26L, and compares the contents of the WAU register 25U with WAU and RAU.
CMP28 to compare the contents RAU of register 26L
We are monitoring the comparison results of U. And RAL<
If WAL, RAU<WAU, the read control section
It is determined that data can be read from LB20L, and in the read cycle, data is read from LB20L using RAL register 26L and UB20 using RAU register 26U.
Read data from U at the same time, and then
The contents of the RAU register 26U and RAL register 26L are incremented by 1. At this time, if the INL register 21L is not set, the write control section writes data to the LB 20L using the WAL register 25L as described above in the next write cycle. Then, the above operation is repeated.
The RAU register 26U and RAL register 26L are
As mentioned above, it is reset at startup (see Figure 11), so UB20U and LB20L
Data is read from address 0.

When reading data from UB20U and LB20L, when reading the first data of one record, RAU register 26U and RAL register 26L
The contents of BUU register 27U and BUL register 2
7L, RSU register 43U, RSL register 4
The contents of 3L are transferred to the RCU counter 49U and RCL counter 49L, and the contents of the VDL register 47 are transferred to the RCU counter 49U and RCL counter 49L.
The data is loaded into the VCT counter 48 at the timing specified by the control timing generation circuit 60 in the main control unit 38 to start processing one record. The RSU counter 49U, RCL counter 49L, and VCT counter 48 are decremented by 1 every time data is read from the UB 20U and LB 20L. In this example, the records fed to merger 10 are
3, preprocessing is performed so that the key field to be compared becomes the first key field. Therefore, the VCT counter 48 enters an underflow state when reading the final data of the key field, and outputs a borrow signal indicating the end of the key field. The borrow signal from the VCT counter 48 is
It is led to a comparison control section 62. In addition, the RCU counter 49U and RCL counter 49L are the U-side record whose record length is RSU, and the L-side record whose record length is RSL.
When reading the final data of the side record, an underflow state occurs and a borrow signal indicating the end of the record is output. Borrow signals from RCU counter 49U and RCL counter 49L are FUE flag 50U,
Guided by FLE flag 50L. As a result, the flags 50U and 50L are set, indicating that the final data of one record is being read.

The data read from UB20U and LB20L is sent to UPR register 22U and LOW register 22L.
is maintained. The data held in the UPR register 22U and LOW register 22L is led to the CMP 23.
In addition, UPR register 22U, LOW register 22
The data held in L is sent to the INUR register 31U via the OTU register 24U and OTL register 24L.
It is also led to INLR register 31L, and the same register 3
It is held at 1U and 31L.

The CMP 23 compares the magnitude of both data from the UPR register 22U and the LOW register 22L.
The comparison result of the CMP 23 is led to the comparison control section 62 within the main control section 38. The comparison control section 62 includes
A borrow signal indicating the end of the key field from VCT counter 48 is also led. Comparison control section 62
If the comparison result from CMP23 is U>L or U<L, at that point the U side record (in this example, 1 record in S11) and the L side record (in this example, 1 record in S12) Confirm the comparison result between the specified key fields with CMP2
3 is transmitted to the control signal generation circuit 65.
On the other hand, in the case of U=L, the comparison result cannot be determined, so the determination of the comparison result is refrained from being determined until the comparison result for the next data is given. However, if the end of the key field (key field end) is detected by the borrow signal from the VCT counter 48, U=L is determined,
The match detection result from the CMP 23 is transmitted to the control signal generation circuit 65. In addition, in the above explanation, U is UB
Indicates read data from 20U, L is LB20
The data read from L is shown.

On the other hand, the read data from the UB20U and LB20L held in the INUR register 31U and INLR register 31L are written to the URB30U and LRB30L in parallel with the comparison operation by the CMP23. The write addresses for these URB30U and LRB30L are RAUR registers 35U and 35L.
specified by. RAUR register 35U,
The RALR register 35L is cleared when one record is written, so data read from the UB 20U and LB 20L is written from address 0 of the URB 30U and LRB 30L.

Control timing generation circuit 60 in main control section 38
is FUE flag 50U and FLE flag 50L
is monitoring the status of. The control timing generation circuit 60 then outputs the FUE flag 50U and FLE
When it is detected that both flags 50L are set, that is, when reading of the final data of the record with the longer record length among the U-side record and the L-side record is detected, (URB 30U or LRB
Assuming that it is now possible to read and output one record from 30L), timing instructions for outputting various control signals are given to the control signal generation circuit 65. The control signal generation circuit 65 generates the MRG-OP code and AS/DS bit in the merge operation specification information held in the MOP register 39 and the comparison control unit 6 at the specified timing from the control timing generation circuit 60.
UB20U, LB according to the comparison result from 2.
Read address for 20L, interrupt control unit 6
3, and various control signals for controlling the output control section 64 and the like. In the preferred embodiment, control signal generation circuit 65 is a ROM. When external sorting is specified by the MRG-OP code (i.e., as in this example), the control signal generation circuit 65
In the case of SORT-EX operation) various control signals are output according to the input/output logic shown in FIG. for example,
Assuming that the subrelations S11, S21, . In the case of L, the next record is read from UB20U,
A control signal instructing the current record to be read again is output from LB20L. This control signal is, for example, a load signal to the RAU register 26U and RAL register 26L, and in this case,
A load signal to the RAL register 26L is output. When a load signal to the RAL register 26L is output, the start address of the current record loaded into the BUL register 27L (from the RAL register 26L at the start of record processing) is loaded into the RAL register 26L. As a result, the above
In the same way as reading data from LB20L, it becomes possible to read out the current record again in order starting from the first data. On the other hand, the RAU register 26U indicates the address of the next data (in this case, the start address of the next record) and remains unchanged. In this case, it becomes possible to read the next record sequentially starting from the first data in the same manner as the data reading from the UB 20U described above. Further, the control signal generation circuit 65 outputs a valid (logic "1") output instruction signal 85U that instructs the output of the record written in the URB 30U. On the other hand, if the comparison result is U>L, UB20
The current record is read again from U, the next record is read from LB20L, and a valid (logic "1") signal is output that instructs the output of the record written to LRB30L.
Outputs an output instruction signal 85L. Furthermore, the control signal generation circuit 65 generates a valid interrupt enable signal 74 regardless of the comparison result and the state of the AS/DS bit.
Output U, 74L.

Now, the control signal from the control signal generation circuit 65 instructs the reading of the next record from the UB20U and the reading of the current record from the LB20L, and the output instruction signal 85U of ethics "1" is output. do. The output instruction signal 85U of ethics "1" from the control signal generation circuit 65 is guided to the FUO flag 53U, and thereby the FUO flag 5
3U is set. Output sequence control section 83
is FUO flag 53U and FLO flag 53L
When the FUO flag 53U is set as in this example, it instructs the URB read control unit 84U to read and output records from the URB 30U. URB read control unit 84U
Assume that is output. Control signal generation circuit 65
The output support signal 85U of logic “1” from
RAUR register 35U and CTR counter 56
is cleared, and then data is read from the URB 30U using the RAUR register 35U.
The read data from URB30U is (URB30
URB3 when reading from U is specified
0U side) via multiplexer 32
is directed to the ROUT register 33. Every time a predetermined byte of data is read from the URB 30U, the URB read control unit 84U increments the contents of the RAUR register 35U and the CTR counter 56 by 1, and
Outputs an output strobe signal 87U. This output strobe signal 87U is guided to gate 88 via OR86. Gate 88 receives the output signal from OR 86 (output strobe signal 87 in this example).
U) is output to the ROUT register 33 in response to output permission from the extraction control unit 89. The control operation of the extraction control unit 89 will be explained in detail using JOIN operations as an example.
It is assumed that output permission is given to the gate 88 during the period of reading from the first data to the last data of one record written in the URB 30U, and a description thereof will be omitted. With output permission from the cutting control unit 89,
When the output strobe signal 87U, which is the output signal from the gate 88, is guided to the ROUT register 33,
(ROUT register 33 via multiplexer 32
The read data from the URB 30U (which is led to the ROUT register 33) is latched into the ROUT register 33. The data latched in the ROUT register 33 is transferred to an HM (not shown) via the HMA 17. Furthermore, during the data reading period from URB30U, the next record is read from UB20U and LB20L, and the same record is sent to URB in specified byte units.
It is also possible to write from address 0 of LRB 30U and LRB 30L. In this case, URB30U, LRB30
Read/write operations for L are performed using UB20U,
Similar to that for LB20L, it is necessary to perform this in a time-sharing manner.

The above operation is repeated and the WAL register 25
It is assumed that the CMP 28L, which compares the contents of the L and RAL registers 26L, detects a match. In this case, the CMP 28L outputs a coincidence detection signal of logic "1". This coincidence detection signal is guided to one end of A68L. A logic "1" output signal from the FLWED flag 51L is led to the other end of A68L. This is because the FLWED flag 51L is in the set state as described above. in this case,
The AND condition of A68L is satisfied, and a logic "1" signal is output from A68L. This logic "1" signal from A68L indicates that the read address indicated by the RAL register 26L matches the write address of the WAL register 25L when the writing of the sub-relation to the LB20L (S21 in this example) has been completed. This indicates that LB20L has become empty. A logic "1" signal from A68L is directed to gate 69L. Gate 69L receives the logic “1” signal from A68L,
Gate is performed at the designated timing (record end detection timing) from the control timing generation circuit 60. As a result, the logic "1" signal from A68L is output to the FLEMP flag 52L,
2L is set. A logic "1" (set) output signal from FLEMP flag 52L is routed to one end of A73L. An interrupt enable signal 74L from the control signal generation circuit 65 is led to the other end of A73L. In this case, the interrupt permission signal 74L is logic "1" (see FIG. 13) as described above, and therefore A73L outputs a logic "1" signal.
The logic "1" signal from A73L is led to the interrupt generation circuit 76 via OR75, and thereby the interrupt generation circuit 76 generates an interrupt to the CPU 11. When the CPU 11 receives an interrupt from the merger 10 (interrupt generation circuit 76 therein), it reads the contents of a status register (not shown) in the merger 10 and determines the cause of the interrupt.

When the CPU 11 determines by reading the status from the merger 10 that the LB 20L is empty, it performs setup for the next sub-relation, ie, S22 in the second relation. The setup in this case is almost the same as the setup related to S21 described above, and the MOP register 39 specifies the MRG-OP code that specifies external sorting and the sort order.
AS/DS bit, logic “1” specifying LB20L
Merge operation designation information (SORT-EX(L) command) including the U/L bit of is set.
Then, in the CMD register 41 in the merger 10,
As in S21, the merger 10 is activated again by setting the ENG.GO command. At this time, the clear circuit 61 causes the S21
As in the case of , WAL register 25L, RAL register 26L, FLWED flag 51L (and
FLEMP flag 52L) is cleared (reset) (SORT-EX (L) in Figure 11, ENG.GO
(See command column). On the other hand, WAU register 25
U, RAU register 26U, FUWED flag 51
U (and FUEMP flag 50U) is CPU11
The state at the time of interruption (that is, at the end of the operation) is retained. Therefore, the RAU register 26U indicates the start address of the next record. This state, that is, the subrelation (S11 in this example)
The state in which the start address of a certain record within is specified is indicated by "any" in FIG.

When the clear circuit 61 performs the clear operation, the merger 10 clears the information in the MOP register 39.
Performs data processing (external sort) specified by the SORT-EX (L) command. In this case, on the U side (as is clear from the contents of the RAU register 26U), the first record of the unprocessed records of the subrelation (S11 in this example) remaining in the UB20U, and on the L side (RAL register 26L is cleared). ) The subrelation newly written to LB20L (S22 in this example)
External sorting is performed starting from the first record.
When LB20L becomes empty again as a result of the external sort, the CPU 11 returns SORT-EX(L),
Using the ENG.GO command, specify S23→UB20U to instruct external sorting. As a result, S
External sorting is started from the first record of the remaining portion of No. 11 and the first record of S23. Then, when UB20U becomes empty, CPU1
1 is SORT-EX (U), ENG.GO command (first
) in Figure 1, specify S12→UB20U and instruct external sorting. In this case, the clear circuit 61 clears the logic “1” U/L bit and
Depending on the ENG.GO bit, SORT-EX (L),
Contrary to the case of the ENG.GO command, registers and flags related to UB20U, that is, WAU register 2
5U, RAU register 26U, FUWED flag 5
Clear 1U (and FUEMP flag 52U) (SORT-EX (U) in Figure 11, ENG.GO
(See command column). Therefore, in this case,
External sorting is started from the first record in S12 and the first record in the remaining portion of S23.

It is assumed that the merge sort is performed in the merger 10 in this way, and all the final relations S23 of the first relation S1 are output to the outside. In this case, since LB20L is empty, the FLEMP flag 52L is set.
From merger 10 (interrupt generation circuit 76 within)
An interrupt occurs to CPU11. When the CPU 11 receives an interrupt from the merger 10, it determines the cause of the interrupt. And CPU11 is LB20L
When it is determined that the second relation S2 has become empty and all of the second relation S2 has been output, the PASS-1 (U) and MRG.GO commands are issued to instruct the output of the data left in the UB20U (remaining part of S12). is given to Majiya 10. The MRG.GO command in this case is MRG.GO=1, REG.IND=RST=ENG.
GO=URTRY=LRTLY=0. Margeya 10 is started by the MRG.GO command,
The processing instructed by the PASS-1 (U) command, that is, reading data from the UB 20U using the RAU register 26U and outputting the read data from the UB 20U to the outside is performed. When starting with this MRG.GO command, RST=ENG.GO=
Since URTRY=LRTRY=0, the clearing operation by the clearing circuit 61 is prohibited. Therefore, the registers and flags related to UB20U, namely WAU register 25U, RAU register 26U,
FUWED flag 51U (and FUEMP flag 5
2U) is shown in the previous state, i.e. in FIG.
Holds the state at the end of execution of the SORT-EX (U) and ENG.GO commands. As is clear, the RAU register 26U indicates the first record of the record group left in the UB 20U. Therefore,
A read control section (not shown) in the main control section 38 of the merger 10 can sequentially read out the remaining portion of S12 in specified byte units. Then, when the remaining portion of S12 is discharged, that is, when the UB 20U becomes empty, the FUEMP flag 52U is set and an interrupt is issued to the merger 10.

When the CPU 11 determines that the LB20L is empty due to an interrupt from the merger 10 and that all of the remaining S12 has been discharged, the CPU 11 inputs the uninput data to the merger 10 (in this example, the last sub-relay of the first relation S1). PASS-1 instructs to output the section S13) via merger 10
(U) gives the ENG.GO command to the merger 10; The ENG.GO command in this case is ENG.GO
=1, REG.IND=RST=MRG.GO=URTRY=
LRTRY=0. The merger 10 is started by the ENG.GO command, and writes S13 to the UB 20U, which is input via the HMA 16, IN aligner 13, sorter 12, and sort checker 14.
Read and output S13 written in UB20U. These read and write operations are performed as described above.
This is basically the same as the SORT-EX(L) and ENG.GO commands. Also, when starting with the above ENG.GO command, ENG.GO = 1 (and
Since the U side is specified by the PASS-1 (U) command), only the registers and flags related to UB20U are cleared by the clear circuit 61, as in the case of the SORT-EX (L) and ENG.GO commands. Therefore, S13 input to the merger 10 is written from address 0 of the UB 20U and read from address 0 as well.

The above is the external sorting process by the merger 10.

Next, regarding relational calculation processing by the merger 10, we will take the case of RESTRICT type calculations as an example, and explain the first
This will be explained with reference to FIGS. 4 to 16. Note that FIG. 14 corresponds to FIG. 11, FIG. 15 corresponds to FIG. 12, and FIG. 16 corresponds to FIG. 13. RESTRICT operations are operations that output only records that meet the conditions from one target relation. In the RESTRICT type calculation by the merger 10, the condition data is stored in advance in the UB 20U as a first stream, and the calculation is started while storing the target relation in the LB 20L as a second stream. This point is similar to the case of the external sort (SORT type operation) described above. Then, the specified key field of the condition data is compared with that of the target relation, and when the calculation condition is satisfied,
Output selection part OSP with L side record as output target
sent to. Note that it is also possible to output the U-side record together with the L-side record.

Now, the first relation as condition data is S1, and the target relation (second relation)
Assuming that S2 is S2, the CPU 11 first sends the merger 10 a LOAD (U) command to change S1→
Specify UB20U and start merger 10 (including engine core 15) using the ENG.GO command. This allows, as with external sorting,
S1 is sequentially written in predetermined byte units starting from address 0 of UB20U. Then, by writing data of only RSU×TRN, a borrow signal is output from the STC counter 46, and when the FUWED flag 51U is set, an interrupt is generated from the merger 10 to the CPU 11. Next, the CPU 11 uses REST-EQ (L)
Specify S2→LB20L by command,
Instruct REST-EQ. This REST-EQ indicates that the target relation is output when the key field of the condition data is equal to that of the target relation. And CPU11 is ENG.GO
Engine 10 (including
Start up the core 15). The subsequent operation is substantially the same as in the case of the external sort (ie, SORT-EX command) described above. That is, in merger 10, first
The registers and flags related to LB20L are cleared, and then the write operation of S21 is started in the area starting from address 0 of LB20L. When data writing to LB20L is started, data reading from UB20U and LB20L is started.
The read data from the UB20U and LB20L is led to the CMP23, and the CMP23 and comparison control unit 62 compare and confirm the key field specified by the VDL register 47.
Guided by URB30U and LRB30L, the same URB30
U, written to LRB30L. However, UB2
When the data read from 0U and LB20L becomes the final data of the corresponding record, FUE flag 50U and FLE flag 5 are set as described in the external sort operation.
0L is set (which one is set first depends on the record length). The control timing generation circuit 60 gives timing instructions for outputting various control signals to the control signal generation circuit 65 when both flags 50U and 50L are set. As a result, the control signal generation circuit 65
MRG.GO command and AS/DS in the merge operation specification information held in the MOP register 39
Depending on the bit and the comparison result from the comparison control unit 62, it controls updating of records in the UB 20U and LB 20L, and instructs to output records written in the UB 20U and LB 20L. And F.U.E.
The flag 50U and FLE flag 50L are reset, and the next record process is performed. Note that the input/output ethics of the control signal generation circuit 65 when REST-EQ calculation is specified as in this example is as follows.
As shown in Figure 6. However, the input/output ethics shown in FIG. 16 assumes that the input relations to the merger 10 are sorted in ascending order (AS/DS=0).

In this way, REST-EQ(L), ENG.GO
The operation specified by the command is executed, and the RAL register 26L is stored, for example, as shown in FIG.
The content of matches that of WAL register 25L,
It is assumed that a coincidence detection signal is output from the CMP 28L. In this case, the FLEMP flag 52L is set and the CPU
11 is interrupted. This allows CPU1
1 determines whether the calculation in merger 10 is completed. This is because a match detection signal is output from CMP28U,
The same applies when the FUEMP flag 52U is set.

In such a state, there may be cases where it is desired to perform another calculation on the data stored in UB20U and LB20L. In this case, only MRGiya 10 will be started, so basically MRG.GO
command is used. However, with the MRG.GO command shown so far, UB2
Registers and flags related to 0U or LB20L are not cleared. In this case, UB20U,
It is not possible to perform a desired operation from the beginning of the data in LB20L. Therefore, in this example,
As shown in Figure 14, the desired merge operation command (REST-NE(L) command in this example)
In addition, URTRY and LRTRY are specified.
MRG.GO command, i.e. MRG.GO=URTRY=
LRTRY=1, REG.IND=RST=ENG.GO=0
The MRG.GO command is applied. As shown in the clear circuit 61 in FIG. 7, the URTRY bit is
Guided by one end of OR80U, the LRTRY bit is OR
It is guided to one end of 80L. Therefore, URTRY
=LRTRY=1 In this example, OR80U,80
The output level of L becomes logic "1". For this reason,
At the start timing from the control timing generation circuit 60, the RAU register 26U and FUEMP flag 52U are cleared in response to the URTRY bit, and the RAL register 26L and FLEMP flag 52L are cleared in response to the LRTRY bit. On the other hand, the WAU register 25U, WAL register 25L, FUWED flag 51U, and FLWED flag 51L retain their previous states, that is, the state at the end of execution of the REST-EQ (L) and ENG.GO commands shown in Figure 14. do. Therefore, UB
Perform the desired operation (in this example) on the data stored in 20U and LB20L from the first data.
REST-NE(L) operation) can be performed.
In addition, in the REST-NE command, the U-side data (record) when the key field of the condition data is not equal to that of the target relation and the record update for LB 20L is performed is the output target.

Next, the RESTRICT type calculation (REST-EQ calculation) for the target relation exceeding the capacity of the LB 20L will be explained with reference to FIGS. 17 and 18. In addition, Fig. 17 is similar to Fig. 11 and Fig. 1
FIG. 8 corresponds to FIG. 12. Now, assume that the first relation as condition data is S1, and the target relation (second relation) is S2. Also,
It is assumed that S2 is divided into S21 to S23 according to the capacity unit of the RAL register 26L. Note that the condition data S1 is the RAU register 2.
It is assumed that the capacity does not exceed 6U. In this case, first, from CPU 11 to merger 10,
LOAD(U), ENG.GO command is given.
As a result, the registers and flags related to CMP28U are cleared (LOAD (U) in Figure 17,
(See ENG.GO command column), S1 is UB20U
is written in predetermined byte units starting from address 0. S1
When writing is completed, the CPU 11 gives the merger 10 REST-EQ (L) and ENG.GO commands. As a result, the registers and flags related to LB20L are cleared (see Figure 17).
REST-EQ (L), see the ENG.GO command column), the operation of writing S21 into the area starting from address 0 of LB20L is started. When data writing to LB20L is started, as mentioned above, UB2
Data reading from 0U and LB20L is started, and the key field portions designated by VDL register 47 are compared. And F.U.E.
When the flag 50U and the FLE flag 50L are both set, the comparison result between records,
The MRG.GO command and the AS/DS bit control output instructions and record updates for records written to UB20U and LB20L, and processing proceeds to the next record.

In this way, REST-EQ(L), ENG.GO
The operation specified by the command is executed, and the RAL
It is assumed that the contents of the register 26L match those of the WAL register 25L and a coincidence detection signal is output from the CMP 28L. In this case, as in the case of the external sort described above, the FLEMP flag 52L is set and an interrupt is issued to the CPU 11. Thereby, the CPU 11 determines the end of the calculation between S1 and S21. CPU11 is the next S22
For REST-EQ calculation with S1 in UB20U, REST-EQ (L),
Give the ENG.GO command. However, as for S1, it is necessary to read from the first record again, so as shown in Fig. 17, the ENG.GO command with URTRY specified, that is, ENG.GO=
URTRY=1, REG.IND=RST=MRG.GO=
The MRG.GO command with LRTRY=0 is applied.
In this case, when the ENG.GO command with URTRY specification is applied, when the merger 10 is started, the clear circuit 61 shown in FIG.
RAU register 26U and
FUEMP flag 52U is cleared and logic “1”
ENG.GO bit (and U/L bit)
LB20L specification) WAL register 25L,
FLWED flag 51L, RAL register 26L,
FLEMP flag 52L is cleared. Also,
The WAU register 25U and FUWED flag 51U retain their previous states. Therefore,
Regarding S1 that has already been written to the UB20U, it becomes possible to read it from the first record. Moreover, it is also possible to correctly detect when S1 is completely read and UB20U becomes empty. On the other hand, for S22, from the first record
It is clear that the data is written to LB20L and read from the same first record.

In this way, REST-EQ(L) and
The operation specified by the ENG.GO command with the URTRY specification is executed, and as shown in FIGS. 17 and 18, the contents of the RAU register 26U match those of the WAU register 25U, and the CMP2
It is assumed that a coincidence detection signal is output from 8U.
In this case, the FUEMP flag 52U is set,
An interrupt is generated for the CPU11. This results in
The CPU 11 determines the end of the calculation between S1 and S22. CPU11 is the following S23 and UB20U
For the REST-EQ operation between S1 in the merger 10, REST-EQ(L),
Give the ENG.GO command with URTRY specification. As a result, S1 that has already been written to UB20U
The REST-EQ operation between S23 and S23, which is newly written to LB20L, is performed from the first record.

Next, relational calculation processing by the merger 10 will be explained using a JOIN type calculation as an example.
A JOIN type operation is a so-called two-stream input synthesis output type operation that compares designated key fields of two relations and creates a new relation based on the set where the conditions are met. for example,
In the JOIN-EQ operation, which is one of the JOIN-type operations,
Two records with matching specified key fields are combined and output as one record. In the JOIN operation by merger 10, after storing the first stream in UB20U by specifying LOAD (U) operation, and storing the second relation in LB20L by specifying JOIN (L) operation, JOIN operation is performed. It is done. And the specified key field of the read record from UB20U (U side record),
Read record from LB20L (L side record)
When the calculation conditions are satisfied, an instruction to output the U-side and L-side records is given from the control signal generation circuit 65. The input/output logic of the control signal generation circuit 65 in the JOIN-EQ operation is
It is shown in FIG. However, the input/output logic in FIG. 19 is based on the assumption that the relations to the merger 10 are sorted in ascending order. In addition,
In JOIN operations, the first and second relations do not exceed the capacity of UB20U and LB20L,
The sort order must also be the same. The fact that the sort order is the same means that the SORT type operations mentioned above,
The same applies to RESTRICT operations.

Now, the read records from UB20U and LB20L are done in parallel with the comparison operation by CMP23.
Written to URB30U and LRB30L. And FUE flag 50U and FLE flag 50L
When both are in the set state, that is, when the reading of the final data of the U-side record and the L-side record are both detected, the control signal generation circuit 65 outputs UB20U and LB2 as in the case of the external sort described above.
Instructs to output records written to 0L and controls record updates. In this example of JOIN-EQ calculation, assuming that U=L has been determined by the comparison control section 62, the control signal generation circuit 65
outputs output instruction signals 85U and 85L of logic "1" as shown in the input/output logic of FIG.
These logic “1” instruction signals 85U, 85L are
Guided by FUO flag 53U and FLO flag 53L,
As a result, the flags 53U and 53L are set. The output sequence control unit 83 monitors the FUO flag 53U and the FLO flag 53L.
As in this example, when the FUO flag 53U and FLO flag 53L are both set, the output sequence control unit 83 first instructs the URB readout control unit 84U to read and output records from the UB 20U, and also 89 to control the extraction of the U-side record. The URB read control unit 84U controls the RAUR register 35U and
Clear CTR counter 56 and then RAUR
Data is read from the URB 30U using the register 35U. Read data from URB 30U is guided to ROUT register 33 via multiplexer 32. URB read control unit 84
Each time U reads a predetermined byte of data from URB 30U, it increments the contents of RAUR register 35U and CTR counter 56 by 1 and outputs an output strobe signal 87U. CTR counter 56
The contents are CMP57U~59U, CMP57L~
Guided by 59L, OSUA register 54U, OSUB
Register 55U, RSU register 43U, OSLA
It is compared with register 54L, OSLB register 55L, and RSL register 43L. CMP57U, 58
The comparison results of U and CMPs 57L and 58L are led to a cutting control section 89.

The cutout control unit 89 is connected to the U from the interrupt control unit 63.
If you are instructed to control the extraction of side records,
Start CMP57U and CMP58U. Then, the extraction control unit 89 controls the contents of the CTR counter 56 (in this example, the contents of the RAUR register 35U, which match the read address for the URB 30U) indicating the position in the record of the data currently being read.
If is X, then by CMP57U, 57U
During the period in which OSUA≦X≦OSUB is detected, output permission is given to the gate 88. As a result,
Only during the period when output permission is given from the cutout control unit 89, the output strobe signal 87U from the URB readout control unit 84U is guided to the ROUT register 33, and the readout data from the URB 30U is
It is latched into the ROUT register 33. Therefore, by setting OSUA (first extraction position) and OSUB (second extraction position) to appropriate values, only desired attributes can be selectively extracted and output from the U-side records to be output. be able to. This also applies to the L-side record. Note that OSUA (OSUA) = 0, OSUB (OSLB) =
In the case of RSU, data for one record is output as is.

When the read data from the URB 30U becomes the final data of the corresponding record, the CMP 59U enters an overflow state and a borrow signal is output from the CMP 59U. The URB read control unit 84U is
When a borrow signal is output from the CMP 59U, it is determined that the record reading has ended, and the output sequence control unit 83 is notified of this fact. The output sequence control unit 83 is notified of the end by the URB readout control unit 84U, and if the FLO flag 53L is set as in this example, the output sequence control unit 83 outputs the LRB readout control unit 84L.
It instructs the LB 20L to read and output records, and also instructs the extraction control unit 89 to perform extraction control for the L-side record. As a result, in the same manner as in the case described above, the data of the field portion satisfying OSLA≦X≦OSLB in the L-side record is extracted and output.

In the above embodiment, a case was explained in which the field portion sandwiched between the first and second extraction positions of the record to be output is extracted and center extraction is performed, but it is also possible to perform side extraction in which the outer portion is extracted. be. Further, by providing a flag specifying center cutting/side cutting, it is also possible to deal with both center cutting and side cutting.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to selectively output only a desired field in a record that is particularly handled in a relational operation at high speed.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a merger according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a relational database engine (RDBE) to which the merger of FIG. 1 is applied, and FIG. 3 is a diagram of merge operation specification information. 4 is a format diagram of command data, FIG. 5 is a block diagram showing the functional configuration of the main control section shown in FIG. 1, and FIG. 6 is a block configuration diagram around the interrupt control section shown in FIG. 5. , Figure 7 is a circuit configuration diagram around the clear circuit shown in Figure 5, and Figure 8 is a diagram of the circuit around the clear circuit shown in Figure 5.
Block configuration diagram around the output control section shown in Figure 9.
The figure is a schematic diagram showing the procedure of external sorting, Figure 10 is a conceptual diagram of external sorting, and Figure 11 is a command sequence for executing external sorting, and various registers and flags at the time of startup and termination by each command. Figure 12 is a diagram showing the correspondence relationship with the contents of
Figure 1 is a diagram explaining the changes in the writing and reading positions to the U/L buffer at the end of execution of each command shown in Figure 1, and Figure 13 is a diagram showing the input/output logic of the control signal generation circuit when external sorting is specified. Figures 14 to 16 show examples, and Figures 11 to 13
Figures 17 and 18 correspond to Figures 11 and 12, and are diagrams for explaining RESTRICT operations. Figures 17 and 18 correspond to Figures 11 and 12. A diagram to explain the RESTRICT (constraint) type operation when exceeding the limit, Figure 19 is the JOIN type operation (JOIN-EQ)
FIG. 3 is a diagram illustrating an example of input/output logic of a control signal generation circuit when . 10...Majiya, 11...CPU, 20U...
...U Batsuhua, 20L...L Batsuhua, 23,2
8U, 28L, 57U~59U, 57L~59L
...Comparator (CMP), 27U...BUU register,
27L...BUL register, 38...Main control unit,
39...MOP register, 41...CMD register, 42...TRN register, 43U...RSU register, 43L...RSL register, 47...
VDL register, 50U...FUE flag, 50L
...FLE flag, 51U...FUWED flag, 5
1L...FLWED Terrag, 52U...FUEMP flag, 52L...FLEMP flag, 53U...
FUO flag, 53L...FLO flag, 54U...
...OSUA register, 54L...OSLA register,
55U...OSUB register, 55L...OSLB register, 61...Clear circuit, 62...Comparison control section, 63...Interrupt control section, 64...Output control section, 65...Control signal generation circuit, 89... Cutting control section.

Claims (1)

[Scope of Claims] 1. A first buffer 20U that stores a first relation that has been subjected to a sorting process, a second buffer 20L that stores a second relation that has been subjected to a sorting process, and a calculation type. a first register 39 that holds an operation code to indicate and a buffer specification bit that specifies either the first or second buffer; and a record that constitutes a relation stored in the first or second buffer. a second register 42 that holds record number information indicating the number of records; a third register 43U that holds record length information indicating the record length of the records constituting the relation stored in the first or second buffer;
43L, and a fourth register 47 that holds key field length information indicating the key field length of the relation.
and, when load processing or relational operation processing is specified by the operation code held in the first register, the above is applied to the buffer specified by the buffer specification bit among the first or second buffer. means 38 for writing the relation of the amount of data indicated by the number of records specified in the second register and the record length specified in the third register; and the operation code held in the first register. When relational calculation processing is specified, a means 65 for reading data one record each from the first and second buffers, and a third means 65 for temporarily storing data for one record read from the first buffer. a buffer 30U; a fourth buffer 30L for temporarily storing data for one record read from the second buffer; and a buffer 30L for temporarily storing data for one record read from the second buffer; A first comparator 2 that compares between the key fields
3, means 65 for controlling the updating of read addresses for the first and second buffers according to the comparison result of the first comparator and the operation code held in the first register; Read control units 84U, 84L that control the output of one record of data stored in the fourth buffer to the outside, and first cutout pointers 54U, 54L that specify the first cutout position of the record to be output to the outside. , second extraction pointers 55U, 55L that specify the second extraction position of the external output target record.
and a second comparator 57U that compares the read address to the third or fourth buffer presented by the read control unit with the content of the first extraction pointer.
57L, and third comparators 58U and 58L that compare the read address and the contents of the second extraction pointer.
and an extraction control section 89 that controls the operation of the readout control section according to the comparison results of the second and third comparators.