JPS61165150A - Main storage access system - Google Patents

Abstract

PURPOSE:To raise the efficiency of data processing over plural banks by executing access by a tank unit to a main storage in order of an address, in which access to a bank containing a lock bit for indicating whether a common data area can be used or not becomes final. CONSTITUTION:Access requests which have been transferred to channels CHA 31, 32 of a channel control device CTP30 through input/output control devices IOC 13, 14 from plural input/output apparatuses are set to data registers DR34, 35. In the head bit of a data D0 in the data registers DR 34, 35, a lock bit L is entered, these data blocks are sent to a request-in register RIR36 through multiplexers 38, 39 and 41, transferred to a request-get register 51 of a main storage device 50, and access is executed in order in which a bank containing each bank lock bit of a main storage 17 becomes final through multiplexers 63, 64 and 67.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory access method in a data processing device, and more specifically, to a method for accessing main memory in a data processing device, and more specifically, a method for accessing main memory in a data processing device. When sources access data in a common main storage area in conflict, the main storage is accessed while guaranteeing data consistency for accesses from each requester, i.e. from one requester. When data in the main memory that is being accessed is accessed by another request source, the data area's data area is set to "L" while the access operation is not completed.
Other request sources use a soft lock method that allows other request sources to recognize that an update is in progress due to the lock pit being 1", improving efficiency when accessing the main memory. This paper relates to a main memory access method.

[Conventional technology]

When request sources such as CPUs, CHPs, or CPUs and CHPs compete to access data in a common main storage area in the main storage device, the access operation to the main memory from one request source is If the data in the main memory being accessed is accessed by the other request source while the access is not completed, the data obtained by the other request source is not desired when the one request source is storing the data. becomes incorrect. Therefore, if there is a contention for data in common main storage, the data from each requester.

``A main memory access method is used that guarantees data consistency for access.

3 to 6 show a data processing system that accesses the main memory and a conventional main memory access method. FIG. 3 shows a data processing system that accesses the main memory. In the figure, 10 is a main storage device;
11 is a CPU, 12 is a channel processing unit (CHP),
CHP 12 includes an input/output channel (CHA) and a data transfer controller.

13 and 14 are input/output control devices (IOC), and 15 and 16 are input/output devices (■0).

In this configuration, the CPU II accesses the main storage device 10 and performs data processing. On the other hand, CHP12 has IO
When a request from I5 or 16 is received from I0C 13 or 14, it accesses main memory 10 and transfers data.

FIG. 4 shows the configuration of the main storage device 10.

In the figure, 17 is a main memory, which has a plurality of banks (BANK) for storing data in an 8-byte configuration. The figure shows four BANKo to BANK3. 18 is the priority port register (PPRo
), it has a function address register (FCADo) to which the function code FC and address AI) are sent, and a data register (DRo) to which data is set, and the CPU is set. 19 is also a priority boat register (PPP+), which internally has a function address register (FCAIh) to which a function code FC and address AD are written, and a data register (DR+,) to which a monitor is set. Request data from CHP 12 is set. Both DRo and DRl consist of 16 bytes,
The data is divided into an i-byte data area Du in the first half and an 8-byte data area DL in the latter half, and the read data is stored in BANK3 of the main memory 17 in 8-byte increments. Stored.20~
23 is a multiplexer (MPX), MPX20 and 2
1 selects one of data area Do and data area DL, and selects MP
'X22 selects one of PP'Ro'18 and PPR+'19, MPX23 selects one of FCADo and FCAD+, and each data area D of DRo and D Rl
B A N data of u and DL according to each address
Store in either K o = B A N K 3. 24 and 25 are request gent registers (RG
Ro, RGR+'), CPUI 1 and CHP1
The function code FC, address AD, and data transferred from 2 are temporarily seseted. 26 and 2
7 is a port input control unit (PICo', PTC+),
G Ro data to FCADo and D Ro, RG
Controls the transfer of R+ data to FCADl and DR1.

FIG. 5 shows the structure of data stored in the memory 17. Total 16 bytes (0 to 127 bits)
However, since it is stored in each 8-byte BANK, it consists of the first half 8-byte data Do and the second half 8-byte data D1.

Data is transferred from the input/output channel CHA of CHP12 using a 4-byte infrastructure bus, so data Do and Dl
is 4-byte data DOL', Do u and D+
L, D+ucf are transferred separately. First half data D
A lock byte is provided at the beginning of o, and a lock bit L is written as a lock signal in the first bit. When lock bit L is '0', that is, when the lock signal is released, it indicates that the data is not being updated, so each request source can use this data.Lock bit L is '1' , this indicates that the data is being updated, so each request source cannot access this data.

When storing this data in each BANK of the main memory 17,
It is stored in 8-byte increment format, but when the first half of the data Do is stored, the first lock bit L is
is set to "0".

However, since the data is stored in each 13 ANK in an 8-byte interleaved format, the data Do in the first half is 1
There is a time interval between when the second half data D1 is stored in one BANK and when the second half data D1 is stored in the next BANK. Therefore, if one request source finishes writing the first half of data Do and has not yet written the second half of data D1, and another request source makes a fetch request to the same data area, the lock bit will be changed. Since it has already become "O", it is determined that writing has finished and it is no longer in use, and reading is performed including the second half data D1, resulting in inconsistent and incorrect data being read. .

Therefore, in the conventional main memory access method, when writing data, first write the second half of the data D,
Next, by writing the first half data Do, the writing of the first half data DO is completed and the lock bit becomes “0”.
An access method is used in which it can be recognized that all data has been written when `` is reached.

FIG. 6 illustrates a time chart of this conventional main memory access method, taking as an example the case where the main memory 17 is accessed from a C8F18.

When the function code FC, descending order store instruction, address AD, and data (first half data Do, second half data D+) are transferred from the input/output channel CIA, the C8F18 transfers the request port register (RPRCH main memory device, not shown). 10 PPP + 19 cents). Data transfer from the input/output channel CHA is performed in units of 4 bytes, so the 8-byte data Do and Dl are each 4 bytes long.

It is transferred separately into LyDou, D+L, and D+u (Fig. 6).

The function code FC has accesses to the main memory 17 such as 8-byte fetch, 8-byte store,
Information identifying whether it is a 16-byte FESO, CH, 16-byte store, etc. is entered. Figures 4 to 6
In the case of the figure, C8F18 and CPUI are written in 8-byte units.
Data transfer between main memory 1 and main memory 10 is performed, and main memory 1
Since data is stored in 8-byte units in each BANK of 7, an 8-byte store request is written.

When transferring data to the main storage device 10, first, the function code FC, address AD, and the latter half of the data D1 are transferred to a request-in memory (not shown) in the CHP 12.
Register (RGR in RIRCH1 main memory 10)
25) (Fig. 6 ■).

CHP 12 (7) RI FC transferred from RCH.

Each data of AD and D+ is stored in RG in main storage device 1o.
It is temporarily set to Rl 25 (Fig. 6 ■).

RGR+25 function codes F, C and 7F
tz, 2. AD is set to FcADl by PIC+27, and data D1 is set to data register DR+OD
It is set in the u area (Fig. 6 ■).

MPX21, 22, 23 sends 8 bytes of second half data D1 to the specified BANK according to the address of FCAD+.
(Fig. 6 ■) 6 When the storage of data D1 is completed, a storage completion signal is notified to CH'P12 (Fig. 6 ■
).

Upon receiving this storage completion signal, the C8F18 transfers the first half data Do to the main storage device 10 in the same procedure as the second half data D1 described above, and stores the data B at a predetermined address in the main memory 17.
It is stored in ANK (Fig. 6 - 0).

When the storage of the first half of the data Do is completed, a storage completion signal is generated and notified to the C8F18 (FIG. 6 @~0).

By doing this, from one request source to main memory 1
Even if another request source accesses the same data area while data store processing is in progress and before the process is completed, the other request source will not be able to see that the data area is being updated. can be recognized.

However, in this main memory access method, after storing the second half data D1, processing of the next data must wait until storage of the first half data DO is completed, so there is a problem that data processing efficiency decreases.

[Problem that the invention seeks to solve]

In conventional main memory access methods, when data to be stored spans multiple BAs and NKs in main memory, the next data processing waits until the storage of the last data portion with a lock bit is completed. and especially the following BANK
If there is an access from a request source with a high priority while the data is being stored in the data storage area, the data processing efficiency is low because the data processing efficiency is low because the data must be waited until the access is completed.

[Means for solving problems]

The present invention solves the above-mentioned problems in conventional main memory access methods, and provides a main memory access method that guarantees data consistency for accesses from each request source and has good data processing efficiency. As a means for that purpose, it has a main memory device having a main memory composed of a plurality of banks, a plurality of request sources for the above f, a, and a main memory device having a main memory composed of a plurality of banks, and a plurality of request sources for the above f and a, and a request source for the above f and a from each request source. In a main memory access method for data processing systems that performs access operations to the main memory in bank units when an access request spans multiple banks, the request source continuously requests access requests that span multiple banks to the main memory. transferred to the device, and the main storage is
The main memory is accessed bank by bank in descending order of the last address to access the bank including a lock bit that indicates whether or not a common data area of the main memory can be used.

[Effect]

When multiple request sources make access requests to main memory that is composed of multiple banks and access operations are performed in bank units, and the access requests from each request source span multiple banks, the request source Continuously transfers spanning access requests to the main memory. The main storage device receives access requests transferred from the request source in descending order of the address at which access to the bank containing the lock bit is final.
Access main memory in bank units. When access to the final address is completed, data with the lock bit released is stored, and other request sources can recognize that the data is usable when accessing this access area. Furthermore, after one request source transfers an access request, it becomes possible to transfer the next access request to the main storage device.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is a time chart 1 for explaining the operation of the embodiment. Note that the configuration of the data processing system in FIG. 3, the configuration of the main memory 17 in FIG. 4, and the data configuration in FIG. 5 are common to the embodiments of the present invention. Also, these drawings and configurations are referred to as appropriate.

In FIG. 1, 30 surrounded by a chain line is CHP.

Reference numeral 50 denotes a main storage device, which corresponds to the CHPI 2 and main storage device 10 in FIG. 3, respectively.

In CHP30, 31 and 32 are input/output channels (C
HA) controls data transfer between the 10Cs 13 and 14. 33 is the request port register (RPR
), the data register 34 receives the address, data, etc. transferred from the CHA31, that is, the 10C13.
(DR34) and a data register 35 (DR35) in which addresses, data, etc. transferred from the CHA 32, that is, the TOC 14, are sent. The DRs 34 and 35 have the same data configuration, and 16-byte data consisting of a function code (FC), address (AD), first half 8-byte data Do, and second half 8-byte data D1 is set.

The configuration of data Do and Dl is as shown in FIG. In other words, data is transferred from each CHA via a 4-byte interface bus, so the first half data Do and the second half data D+ are each 4 bytes.
DOL, DQu, D+L, D(u) are set in byte units.

Data Do, that is, data Dou when the input/output channel (CHA) stores data in the common data area of the main memory.
A lock bit L is written in the first bit as a lock signal.

36 is a request in register (RIR) in which function code FC, address AD, and 8-byte first or second half data are set. 37 is a request control unit that selects one of DRs 34 and 35 by controlling multiplexers (MPX) 38 to 41;
Furthermore, for the selected data register DR, its FC
, AD and data Do, Ds and select RIR36.
Set to .

Function code FC includes 8-byte fetch, 16-byte fue-sochi, 8-byte store, 16-byte
Byte store is filled.

42 is the timing upper register (TUR), 1
It is used when transferring 6-byte data, and in the case of normal ascending store, when transferring the first 8-byte data Do, the request control unit 37 writes "PaON", and the latter 8-byte data Do is 'OFF' is entered when transferring the light data D. In the case of descending order store, when transferring the latter 8-byte data D1, 'ON' is written by the request control unit 37, and when transferring the first half 8-byte data Do, 'OFF' is written. Ru.

When storing in descending order, the first address of the second half data D1 is sent as the address AD.

Next, in the main storage device 50, 51 is a request register (RGR) that temporarily stores the FC-AD and 8-byte data transferred from the CHPI2.

52 is a priority vote register (PPR
), the data registers (DR) 53 and 5 have the same structure.
4, and sets the FC, AD and 16 bytes of data transferred from the CHP 12. The 16-byte data is set in the data upper area (Du) and data lower area (Dushi) in 8-byte units. By providing two sets of data registers, DRs 53 and 54, two channels of data can be processed in parallel. In the following description, it is assumed that DR53 has priority.

55 is the time upper register (TUR), and CHP
Sets the ON or OFF signal when transferring 16-byte data transferred from 12 TURs 38. 56
is the port input control section, and when TUR54 is ON, R
The 8-byte data set in GR51 is set in the Du area, and when it is OFF, the 8-byte data is sent to the DL area.

As a result, the second half data D1 transferred from Cl1P12 during the descending store is set to the Du area of the DR53, and the first half data Do is set to the DL area.

57 and 58 are DL selection timing circuits, exclusive OR (
EX/OR) circuits 59 and 60 generate addresses for the DL area. That is, the second half data D1 is set in the Du area, the first half data Do is set in the DL area, and
Although the address of the data D1 is set in the address AD, it is a normal address, that is, the BANK of the main memory 17.
Since the addresses when stored in are in the order Do=Dt, the address of Dl is 8 more byte addresses than that of DO. For example, when storing 16 bytes of data in byte addresses 16 to 31 of the main memory 17, the first hide address of D is 24 and the first byte address of DO is 16, as shown in the figure below.

012 22' 23242526272829303
In Figure 1, the rightmost bit is the LSB, so when the byte address of Dl is 24, the 27th and 28th bits are 1". The byte address of Do is 16, which is 8 less than this, so the 28th bit is 1". bit from “1” to “0”
”. When storing 16-byte data in descending order, the first address of data D+ will be a multiple of 8, and the 29th to 31st bits will all be “0”. Therefore, in descending order store mode, At this time, the 29th to 31st bits are not sent, but the O to 28th bits are sent, and the 28th bit is "1", indicating an 8-hide boundary. D
When the L selection timing circuit 57 (or 58) detects a 16-byte store based on the function code FC, it selects Du for the first time and stores Du in the main memory according to the AD address. The second time, select DL and output “1” to EX/OR circuit 59 (or 60)
send to The other input of the EX/OR circuit 59 (or 60) is connected to the boundary of the address AD, that is, the 28th bit. Therefore, when storing in descending order, EX -O
The R circuit 59 (or 60) converts the address of the DL area, that is, the address of Do, into the address of the DL area, that is, D
This is 8 bytes less than the address of l, and a normal address value is generated.

63 to 67 are multiplexers (MPX), MPX63
, 64 and 67 select the data in the data register DR to access the main memory 17, the MPX 66 selects the address of the data, and the MPX 65 selects the function code FC of the data register DR.

The above explanation has been made in relation to the CHP12, but the process is performed in the same manner for the CPU1l, and the process is performed in the same manner as the MPX6.

Selected by 66.67.

Next, the operation when storing the 16-byte data in FIG. 1 in descending order will be explained with reference to the time chart in FIG. 2. In addition, in the following explanation, from ClA31, C
The access operation to the main memory 17 will be explained by taking as an example a case where a 16-byte store request is made to the HP 12, 16-byte data is sent to the DR 34 of the CHPI 2, and set to the DR 53 when transferred to the main memory 50. .

(When a 1116-byte store request is made, ClA
31 is the 16-byte store function code F
C is set in the FC of the DR 34 of the RPR 33 and support for the descending order store is received. Then 4 from ClA31
Set the address AD sent via the byte interface bus to the AD of the DR34, set the first half data D'ou and DOL to the Do of the DR34, and set the second half data D1 u and DIL to the Dl of the DR34. 2
Figure ■).

(2) The request control unit 37 switches the MPXs 38 and 40 based on the FC of the DR 34, the descending order store instruction, and the AD contents, and outputs the function code F of the R34.
C, the address AD of the second half data D1 is set to F of RIR36.
Set to C and AD. Furthermore, regarding the data, first set the latter 8-byte data D], and then set TUR3B.
is set to 0N, and the contents of these RIR36 and TUR38 are transferred to the main memory bag W50. In the present invention, after transferring the second half data D+, the first half data Do is set to RIR3'6 using the same FC and AD, and TUR38 is set to O.
FF and transfer it to the main storage device 50 (Fig. 2 ■).

Therefore, the CHP 12 can immediately start the next data process by successively transferring the 16-byte data D+, Do in DR3'4 to the main storage device 50.

(3) Initially, CHP1 is stored in RGR51 of main storage device 50.
A function that specifies a 2 to 16 byte store.
The code FC, the address AD of the second half data D1, and the second half data D1 are sent, and an ON signal is set in the TUR55.

These data are input to the PPR5 by the port input control unit 56.
When transferred to CHP 7, the same FC,
The first half data DoA<RGR51 is transferred by AD, and T
UR55 is set to OFF (Figure 2, ■).

(4) The port input control unit 56 is an FC of the RGR 51.

Based on the contents of AD and TUR55, TUR55 is ON.
When , the 8-byte data of RGR51 is transferred to the Du area of DR53 in PPR52, and TUR5'5 is OFF.
When , the 8-byte data of RGR51 is DRl) 3D
Set it in the L area, and set the FC and AD as they are as the FC and AD of the DR53. As a result, DR53
The start address of Dl is set in AD, the second half data D1 is set in the Du area, and the first half data DO is set in the DL area (Fig. 2).

(When a 16-byte store is detected from the contents of the FC, the 51DL selection timing circuit 57 reads the data of the Du area and the AD address, that is, the second half data D1 and its address, from the DR53. If the EX/OR circuit 59 does not operate), MPX63
, 65, 66, and 67, the latter half of the data D1 is stored in the BANK at a predetermined address in the main memory 17 (FIG. 6).

The D L selection timing circuit 57 selects the D
The u area, that is, the first half data Do is read from the DR 53. On the other hand, regarding the address, the EX/OR circuit 59 inverts the 28th boundary bit of the address AD, that is, the byte address is 8 from the original address AD.
A smaller address for Do is generated, and the first half of the data Do is stored in the BANK at a predetermined address in the main memory 17.

(6) When the storage of each data in the Du area and Du area, that is, the second half data D1 and the first half data Do, is completed in the main memory 17, a storage completion signal is generated, and the CHP 12
(Figure 6 ■).

■).

Upon receiving this storage completion signal, the CHP 12 moves to the next data access process. Lockpill l-L is pa 0”
At this point, all 16 bytes of data have been stored in the main memory 17, so even if another request source accesses this data, the consistency of the data is guaranteed.

The main memory access method of the present invention can also be effectively used when data is transferred in descending order of addresses. For example, when performing a backward read operation on a magnetic tape device, data must be stored in main memory in descending address order. At this time, if the data is 8 bytes, it can be stored in one BANK at once, so there is no problem, but when performing a 16-byte store to improve processing efficiency, after storing the latter 8 bytes of data, It is necessary to store 8 bytes of data. In such a case, the main memory access method of the present invention maintains data consistency and efficiently transfers 16 bytes of data to the main memory BAN.
It can be stored in K.

The main memory access method for 16-byte data consisting of 8-byte units has been described above, but the present invention is not limited to 8-byte units or 16-byte data; This method is used for accessing data stored across multiple BANKs, and if the descending order of addresses is such that the release of the lock signal is the final step, the order of the addresses of intermediate unit data is changed. There is no harm in doing so. Further, the order of addresses of data to be transferred to the main memory is not limited to normal address order or descending order.

〔Effect of the invention〕

As explained above, according to the present invention, all data is continuously transferred to the main memory, and the main memory stores the data in descending order of the address at which the lock signal is released last. Therefore, data consistency can be guaranteed for access from each request source, and data processing efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of an embodiment of the present invention, Fig. 2 is a time chart illustrating the operation of the embodiment, Fig. 3 is an explanatory diagram of a system that accesses main memory and processes data; 4
FIG. 5 is an explanatory diagram of the conventional main memory access method, FIG. 5 is an explanatory diagram of the data structure stored in the main memory, and FIG. 6 is a time chart of the conventional main memory access method. In the figure, 10 is a main memory, 11 is a CPU, 12 is a channel processing unit (CHP), 13 and 14 are input/output control units (IOC), 15 and 16 are input/output devices (To), 17 is a main memory, 18 and 19 are priority port registers (PPRo, PPP+), 20 to 23 are multiplexers (MPX), and 24 and 25 are request gents.
Registers (RGRo, RGR+), 26 and 27
is the port input control unit (PICo, PIC
+), and 30 is a channel processing unit (CHP), 3
1 and 32 are input/output channels (CHA), 33 is a request boat register (RPR), 34 and 35 are data registers (DR), 36 is a request in register (RIR), 37 is a request control unit, 38-4
1 is a multiplexer (MPX), 42 is a timing
Upper register (TUR), 50 is main memory,
51 is a request gent register (RGR), 52
is the priority vote register (PPR), 5
3 and 54 are data registers (DR), and 55 is a time register.
56 is a boat input control section, 57 and 58 are DL selection timing circuits, 59 and 60
denotes an exclusive OR circuit (EX-OR), and 63 to 67 denote multiplexers (MPX), respectively.

Claims (1)

[Claims] A main memory device has a main memory consisting of multiple banks, and has multiple request sources to this main memory, and when an access request from each request source to the main memory spans multiple banks, the main memory is In a main memory access method for a data processing system in which access operations are performed bank by bank, a request source successively transfers access requests spanning multiple banks to the main memory, and the main memory is arranged in ascending order of addresses. Alternatively, a main memory access method characterized in that the main memory is accessed bank by bank in descending order.