JPS61164304A

JPS61164304A - One wave detection circuit

Info

Publication number: JPS61164304A
Application number: JP640085A
Authority: JP
Inventors: Masaaki Noda; 正明野田
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1985-01-17
Filing date: 1985-01-17
Publication date: 1986-07-25

Abstract

PURPOSE:To reduce number of integrated circuit elements by shifting the level of a base of the 1st NPN detection circuit transistor (TR) by a base-emitter voltage of the 1st PNP TR while using the 1st level shift PNP TR so as to eliminate the need for an input capacitor and a 1/2 Vcc reference power supply circuit. CONSTITUTION:When an AC signal is inputted to a terminal 10, an AC input signal is deflected around a GND level and the level of the AC input signal is shifted by an emitter-base voltage of a Q7, VBE by using a current source I2 and a level shift circuit comprising the TR Q7. The AC input signal subjected to level shift is detected by an NPN TR Q8 for a half wave. The signal subjected to half wave detection is amplified as a current by using PNP TRs Q9, Q10, an NPN TR Q11 and resistors R6-R8, smoothed by a smoothing circuit capacitor 14 and a smoothing circuit resistor 13 and a DC potential is outputted at a terminal 12.

Description

【発明の詳細な説明】産業上の利用分野本発明は、集積回路において一般に用いられる片波検波
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to single wave detection circuits commonly used in integrated circuits.

従来の技術第２図は、従来広く用いられている片波検波回路を示す
ものである。構成としては、検波回路入力コンデン？６
、検波用ＰＮＰ　トランジスタＱ２、検波電流増幅用Ｐ
ＮＰ　トランジスタＱ４．Ｑ６、及びＮＰＮトランジス
タＱ６、抵抗Ｒ２，Ｒ３，Ｒ４、平滑回路用抵抗６、平
滑回路用コンデンサＴ、検波入力端子３のＤＣ電位を与
えるＤＣバイアス回路、定電流源Ｉ、　、ＰＮＰおよび
ＮＰＮトランジスタＱ１．Ｑ３、基準電圧回路から成り
立っている。BACKGROUND OF THE INVENTION FIG. 2 shows a single-wave detection circuit that has been widely used in the past. As for the configuration, is the detector circuit input capacitor? 6
, PNP transistor for detection Q2, P for detection current amplification
NP transistor Q4. Q6, and NPN transistor Q6, resistors R2, R3, R4, smoothing circuit resistor 6, smoothing circuit capacitor T, DC bias circuit providing DC potential of detection input terminal 3, constant current source I, , PNP and NPN transistor Q1 ．． Q3, consists of a reference voltage circuit.

なお、点線枠８内の回路部分は、たとえば、シリコン基
板内に一体的に集積回路化されうる部分であり、この場
合には、１〜４は、半導体集積回路の外部端子となる。Note that the circuit portion within the dotted line frame 8 is a portion that can be integrally integrated into a silicon substrate, for example, and in this case, 1 to 4 are external terminals of the semiconductor integrated circuit.

また抵抗５、コンデンサら。Also resistor 5, capacitor etc.

７は外付素子であり、人出刃端子は３，４である。7 is an external element, and 3 and 4 are external terminals.

従来の片波検波回路について第２図の回路動作を説明す
る。ＡＣ入力信号は、コンデンサ６を介して、入力端子
３から入力する。端子３、およびＮＰＮトランジスタＱ
３のエミッタは、基準電圧１ｖｃｃにバイアスされてお
り、コンデンサ６を介して、端子３に入力されたＡＣ信
号は、ＰＮＰ　トランジスタＱ２により片波検波される
。片波検波された信号は、トランジスタＱ４．Ｑ５．Ｑ
６、及び抵抗Ｒ２，Ｒ３，Ｒ４により、電流として増幅
され、平滑回路コンデンサ７、及び抵抗６により平滑さ
れた後、端子よりＤＣ電位が出力される。The circuit operation of the conventional single wave detection circuit shown in FIG. 2 will be explained. The AC input signal is input from the input terminal 3 via the capacitor 6. Terminal 3, and NPN transistor Q
The emitter of the terminal 3 is biased to a reference voltage of 1 Vcc, and the AC signal input to the terminal 3 via the capacitor 6 is single-wave detected by the PNP transistor Q2. The single-wave detected signal is transmitted to transistor Q4. Q5. Q
6 and resistors R2, R3, and R4, and after smoothing by the smoothing circuit capacitor 7 and resistor 6, a DC potential is output from the terminal.

従来の片波検波回路では、検波入力端子をＤＣバイアス
して動作を行うために、検波入力コンデンサ６が不可欠
であり、又、−１ｖｏｃ基準電源回路が必要である。こ
のために回路を集積回路化する場合、外部素子数及び集
積回路素子数の増加を招くことになる。In the conventional single-wave detection circuit, the detection input capacitor 6 is indispensable because the detection input terminal is operated with a DC bias, and a -1 voc reference power supply circuit is also required. For this reason, when the circuit is integrated, the number of external elements and the number of integrated circuit elements increases.

発明が解決しようｋする問題点従来の片波検波回路では、検波回路入力コンデンサが不
可欠であり、また、１ｖｃｃ基準電圧回路が必要である
ため、集積回路化する場合、外部素子数及び集積回路素
子数の増加を招くことになる。Problems to be Solved by the Invention In the conventional single wave detection circuit, a detection circuit input capacitor is indispensable, and a 1Vcc reference voltage circuit is also required. This will lead to an increase in the number of

本発明は、入力コンデンサおよび一１ｖｃ０基準電源回
路が不要で、集積回路素子数を削減することができる片
波検波整流回路を提供することを目的とするものである
。An object of the present invention is to provide a single wave detection rectifier circuit that does not require an input capacitor and a -1vc0 reference power supply circuit and can reduce the number of integrated circuit elements.

問題点を解決するための手段本発明では、検波回路入力端子に、第１のＰＮＰトラン
ジスタのベースを接続し、第１のＰＮＰ　トランジスタ
のコレクタを接地し、エミッタを定電流源、及び第１の
ＮＰＮトランジスタのベースに接続し、第１のＮＰＮ　
トランジスタのエミッタを他端を接地した第１の抵抗の
一端に接続し、コレクタを、第２のＰＮＰ　トランジス
タのベースおよびコレクタ、第３のＰＮＰ　トランジス
タのベースに共通接続し、第２のＰＮＰ　トランジスタ
のエミッタを、他端を電源端子に接続した第２の抵抗の
一端に接続し、第３のＰＮＰ　）ランジ艮夕のエミッタ
を、他端を電源端子に接続した第３の抵抗の一端に接続
し、第３のＰＮＰトランジスタのコレクタを、第２のＮ
ＰＮ　トランジスタのベース、および他端を接地した第
４の抵抗の一端に接続し、第２のＮＰＮトランジスタの
コレクタを電源端子に接続し、エミッタを、検波回路出
力端子として、他端を接地した第６の抵抗、及び、他端
を接地した第１のコンデンサに接続した構成の片波検波
回路である。Means for Solving the Problems In the present invention, the base of the first PNP transistor is connected to the input terminal of the detection circuit, the collector of the first PNP transistor is grounded, and the emitter is connected to the constant current source and the first PNP transistor. connected to the base of the NPN transistor and connected to the base of the first NPN transistor.
The emitter of the transistor is connected to one end of a first resistor whose other end is grounded, and the collector is commonly connected to the base and collector of the second PNP transistor and the base of the third PNP transistor. The emitter of the third PNP lunge is connected to one end of a second resistor whose other end is connected to the power supply terminal, and the emitter of the third PNP lunge is connected to one end of a third resistor whose other end is connected to the power supply terminal. , the collector of the third PNP transistor is connected to the collector of the second N
The base of the PN transistor and the other end are connected to one end of a fourth resistor that is grounded, the collector of the second NPN transistor is connected to the power supply terminal, and the emitter is used as the detection circuit output terminal. This is a single-wave detection circuit configured by connecting a resistor No. 6 and a first capacitor whose other end is grounded.

作用上記構成の回路において、第１のＮＰＮ検波回路用トラ
ンジスタのベースを第１のレベルシフト用ＰＮＰ　トラ
ンジスタにより、第１のＰＮＰトランジスタのベース・
エミッタ間電圧分だけ、レベルシフトを行い、検波入力
端子１０に入るＡＣ信号をＧＮＤを中心に振れさせ、検
波入力コンデンサを省略しようというものである。Operation In the circuit configured as described above, the base of the first NPN detection circuit transistor is changed by the first level shifting PNP transistor.
The purpose is to shift the level by the amount of the voltage between the emitters, swing the AC signal entering the detection input terminal 10 around GND, and omit the detection input capacitor.

実施例第１図に、本発明による片波検波回路の実施例回路図を
示す。図において、９は接地端子、１０は被検波信号入
力端子、１１は電源端子、１２は出力端子、工　は定電
流源、Ｑ７”９”１０はＰＮＰ　トランジスタ、Ｑ８”
１１　　はＮＰＮ　）う／ジスタ、Ｒ６，Ｒ６，Ｒ７，
Ｒ８，１３は抵抗、１４はコンデンサである。第２図と
同様に点線枠１６で囲まれだ部分は、半導体基板上に集
積回路化されうる部分であり、それ以外の素子は、外付
部品とされるものである。Embodiment FIG. 1 shows a circuit diagram of an embodiment of a single wave detection circuit according to the present invention. In the figure, 9 is a ground terminal, 10 is a test wave signal input terminal, 11 is a power supply terminal, 12 is an output terminal, 1 is a constant current source, Q7 is a PNP transistor, 10 is a PNP transistor, and Q8 is a constant current source.
11 is NPN) U/JISTA, R6, R6, R7,
R8 and 13 are resistors, and 14 is a capacitor. Similar to FIG. 2, the portion surrounded by a dotted line frame 16 is a portion that can be integrated into a circuit on a semiconductor substrate, and the other elements are external components.

以上のように構成された本実施例の検波回路について、
以下第１図の回路図にもとづいてその動作を説明する。Regarding the detection circuit of this embodiment configured as above,
The operation will be explained below based on the circuit diagram shown in FIG.

ＡＣ信号が端子１０に入力されると、ＡＣ入力信号はＧ
ＮＤを中心に振れており、電流源Ｉ　およびトランジス
タＱ７によるレベルシフト回路により、ＡＣ入力信号は
、ｖＢＥ（Ｑ７のエミッタ・ペース間電圧）だけ、レベ
ルシフトされる。そして、レベルシフトされたＡＣ入力
信号は、ＮＰＮトランジスタＱ８により片波検波される
。片波検波された信号は、ＰＮＰ　トランジスタＱ９．
Ｑ１゜、Ｎ　Ｐ　Ｎ　トランジスタＱ１１．および抵抗
Ｒ６，Ｒ７，Ｒ８により、電流として増幅され、平滑回
路コンデンサ１４、及び平滑回路抵抗、１３により平滑
されて、端子１２にＤＣ電位が出力される。When an AC signal is input to terminal 10, the AC input signal becomes G
The AC input signal is level-shifted by vBE (the voltage between the emitter and pace of Q7) by a level shift circuit including a current source I and a transistor Q7. The level-shifted AC input signal is subjected to single-wave detection by the NPN transistor Q8. The single-wave detected signal is passed through a PNP transistor Q9.
Q1°, N P N transistor Q11. The current is amplified as a current by the resistors R6, R7, and R8, smoothed by the smoothing circuit capacitor 14 and the smoothing circuit resistor 13, and a DC potential is output to the terminal 12.

発明の効果本発明は、検波回路の入力コンデンサが不要である。又
、２　ｖＣＣ基準電圧回路も不要であるため、素子数が
削減された構成となっている。従って半導体集積回路化
するにあたって、外付素子数、集積回路素子数とも削減
されており、半導体集積回路化に、特に好適である。Effects of the Invention The present invention does not require an input capacitor for the detection circuit. Furthermore, since a 2 vCC reference voltage circuit is not required, the number of elements is reduced. Therefore, when fabricating into a semiconductor integrated circuit, both the number of external elements and the number of integrated circuit elements are reduced, making it particularly suitable for fabricating into a semiconductor integrated circuit.

[Brief explanation of the drawing]

第１図は本発明の検波回路を示す回路図、第２図は従来
の検波回路を示す回路図である。１．９・−・−・接地端子、２　、１１−・・・−電源
端子、１ｏ、３−・・−・検波回路入力端子、４，１２
・−・・−・検波回路出力端子、０１，０２．Ｑ４．Ｑ
５．Ｑ７．Ｑ９．Ｑｌ。・・・−・・ＰＮＰトランジスタ、Ｑ３．Ｑ６．Ｑ８．
Ｑｌｌ・・・、・、ＮＰＮトランジスタ、Ｉ、、Ｉ、・
・・・・・定電流源、Ｒ１，Ｒ２，Ｒ３，Ｒ４，Ｒ５，
Ｒ６，Ｒ７，Ｒ８・・・・・・抵抗、６．１３・・・・
抵抗。虜　１　図ＣｒＮＤ’９FIG. 1 is a circuit diagram showing a detection circuit of the present invention, and FIG. 2 is a circuit diagram showing a conventional detection circuit. 1.9-- Ground terminal, 2, 11-- Power terminal, 1o, 3-- Detection circuit input terminal, 4, 12
・−・・−・Detection circuit output terminal, 01, 02. Q4. Q
5. Q7. Q9. Ql. ...--PNP transistor, Q3. Q6. Q8.
Qll...,..., NPN transistor, I,, I,...
... Constant current source, R1, R2, R3, R4, R5,
R6, R7, R8...Resistance, 6.13...
resistance. Prisoner 1 Figure CrND'9

Claims

[Claims]

The base of the first PNP transistor is connected to the detection circuit input terminal, the collector of the first PNP transistor is grounded, and the emitter is connected to a constant current source and the base of the first NPN transistor. The emitter of the transistor is connected to the first resistor whose other end is grounded, and the collector is commonly connected to the base of the second PNP transistor, and the collector and the base of the third PNP transistor. The emitter of the third PNP transistor is connected to a second resistor whose other end is connected to a power supply terminal, and the emitter of the third PNP transistor is connected to a third resistor whose other end is connected to a power supply terminal.
The collector of the third PNP transistor is connected to the base of the second NPN transistor and a fourth resistor whose other end is grounded, and the collector of the second NPN transistor is connected to the power supply terminal. A single wave detection circuit characterized in that the emitter is connected as a detection circuit output terminal to a sixth resistor whose other end is grounded and to a first capacitor whose other end is grounded.