JPS58207119A - Current source circuit - Google Patents
Current source circuitInfo
- Publication number
- JPS58207119A JPS58207119A JP9061682A JP9061682A JPS58207119A JP S58207119 A JPS58207119 A JP S58207119A JP 9061682 A JP9061682 A JP 9061682A JP 9061682 A JP9061682 A JP 9061682A JP S58207119 A JPS58207119 A JP S58207119A
- Authority
- JP
- Japan
- Prior art keywords
- current
- transistor
- differential amplifier
- resistance
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/265—Current mirrors using bipolar transistors only
Abstract
Description
【発明の詳細な説明】 本発明は、集積回路に適した電流源回路に関する。[Detailed description of the invention] The present invention relates to a current source circuit suitable for integrated circuits.
電流源回路は、種々提案されているが、その中で従来、
第１図に示すようなカレントミラー回路は、基本回路と
して、知られておシダイオード接続されたトランジスタ
ｌと入力信号源２とが電源Ｖ１と接地間に直列に接続さ
れ、一方出方端子４と接地間には直列にはトランジスタ
３が直列に接続され、トランジスタ１と３のベースどう
しは、共通に接続されている。しかしながら、かかる電
流源回路では、入力電流即ちトランジスタ１のコレクタ
電流と出力電流即ちトランジスタ３のコレクタ電流との
電流比を大きく、かつ精度よく作る事は困難である。Various current source circuits have been proposed, among which the conventional
The current mirror circuit as shown in FIG. 1 is a basic circuit in which a diode-connected transistor L and an input signal source 2 are connected in series between a power supply V1 and ground, and one output terminal 4. Transistor 3 is connected in series between and ground, and the bases of transistors 1 and 3 are commonly connected. However, in such a current source circuit, it is difficult to create a large current ratio between the input current, that is, the collector current of transistor 1, and the output current, that is, the collector current of transistor 3, with high accuracy.
本発明は電流比全抵抗比のみで決めることによシ、上記
欠点全除去した電流源回路全提供するものである。The present invention provides a current source circuit which eliminates all of the above drawbacks by determining only the current ratio and total resistance ratio.
本発明によれば一端が電圧供給端子に、他端が、差動増
幅器の反転入力端子に接続され、かつ電流入力端子に導
出された、第１の抵抗、一端が前記電圧供給端子に他端
が前記差動増幅器の非反転入力端子及び第１のトランジ
スタのコレクタに接続された第２の抵抗、前記差動増幅
器の出刃端子がベースに接続され、かつエミッタが前記
電圧供給端子に接続された、前記第１のトランジスタと
極性の異なる第２のトランジスタを含んでなシ、前記第
１のトランジスタのエミッタから出力電流を得ることを
特徴とする電流源回路が得られる。According to the present invention, the first resistor has one end connected to the voltage supply terminal, the other end connected to the inverting input terminal of the differential amplifier, and led out to the current input terminal; a second resistor connected to the non-inverting input terminal of the differential amplifier and the collector of the first transistor; the blade terminal of the differential amplifier is connected to the base; and the emitter is connected to the voltage supply terminal. , there is obtained a current source circuit characterized in that the current source circuit does not include a second transistor having a polarity different from that of the first transistor, and obtains an output current from the emitter of the first transistor.
本発明の電流源回路は、大力端子と出力端子に流れる電
流比は第１の抵抗と第２の抵抗との定抗比で定まシ、そ
の電流比は大きくとることが出来る。In the current source circuit of the present invention, the current ratio flowing between the large power terminal and the output terminal is determined by the constant resistance ratio between the first resistor and the second resistor, and the current ratio can be set to a large value.
次に本発明をその実施例に従い図面音用いて詳細に説明
する。第２図は、本発明の一実施例を示す回路図である
。入力信号源６は、トランジスタ７のベースに接続され
、電源■２と接地間に抵抗５とともに直列に挿入されて
いる。又トランジスタ７．８．９で構成される。差動増
幅器の出力は、トランジスタ１１のベースに接続され、
コレクタはトランジスタ１３のベースに接続される。又
そのコレクタ出力はトランジスタ９０ペースに接続され
、エミッタは出力端子に接続されている。このように構
成することによシ大力電流と出力電流の比は抵抗５と抵
抗１２の抵抗比によシ定まる。Next, the present invention will be explained in detail according to embodiments thereof with reference to the drawings. FIG. 2 is a circuit diagram showing one embodiment of the present invention. The input signal source 6 is connected to the base of the transistor 7, and is inserted in series with the resistor 5 between the power supply 2 and ground. It also consists of transistors 7, 8, and 9. The output of the differential amplifier is connected to the base of transistor 11,
The collector is connected to the base of transistor 13. Also, its collector output is connected to the transistor 90 pace, and its emitter is connected to the output terminal. With this configuration, the ratio between the output current and the output current is determined by the resistance ratio between the resistor 5 and the resistor 12.
即ちトランジスタ１１．１３抵抗１２による帰還回路と
差動増幅器の動作によシ、抵抗５の電圧降下と抵抗１２
のそれは等しい。いま抵抗５の値をＲ５，抵抗１２の値
？Ｒ１２，入力電流ｉＩｘｇ出力電流を工０とすればＲ
５・ＩＩＮ＝Ｒ１２・工０となる。That is, due to the operation of the feedback circuit and differential amplifier using transistors 11 and 13 and resistor 12, the voltage drop across resistor 5 and resistor 12
that of is equal. Now, is the value of resistor 5 R5 and the value of resistor 12? R12, input current iIxgIf output current is 0, then R
5・IIN=R12・Work 0.
従って、Ｉｏ＝（几５／Ｒ１２）ＩＩＮとなシＲ５とＲ
１２の比のみで出刃電流が定まる。Therefore, Io=(几5/R12)IIN, R5 and R
The blade current is determined only by the ratio of 12.
本発明は以上説明したよ゛うに、抵抗と差動増幅器を用
いることによシ入出力電流比を抵抗比のみで、定めるこ
とが出来る。集積回路に於いては、抵抗の相対比を精゛
度良く作る事は容易で６ｋ、しかも、かなシの相対比（
数１０〜数１００或いは１／数ｌθ〜１／数１００ ）
でも安定して笑現し得る。又本実施例を前述のカレント
ミラー回路で実現しようとするとＰＮＰ）ランジスタが
必要となるが、ＮＰＮトランジスタに対し高電流でのｈ
ｐｇ の低下が大きく入出力電流比の誤差となる。As explained above, according to the present invention, by using a resistor and a differential amplifier, the input/output current ratio can be determined only by the resistance ratio. In integrated circuits, it is easy to precisely create the relative ratio of resistors, 6k, and the relative ratio of resistors (
number 10 to number 100 or 1/number lθ to 1/number 100)
But it is possible to smile stably. Furthermore, if this embodiment is to be implemented using the current mirror circuit described above, a PNP) transistor will be required;
A large drop in pg causes an error in the input/output current ratio.
第１図は従来例を示すオ回路図であシ、第２図は本発明
の一実施例を示す回路図である。
１．３，７，８，９，１１．１３・・・・・・トランジ
スタ、５，１０．１２・・・・・・抵抗、２．６・・・
・・・入力信号源。
代理人 弁理士 内 原 晋
＃ｌ 図
手２ 因FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1.3, 7, 8, 9, 11.13...transistor, 5,10.12...resistance, 2.6...
...Input signal source. Agent Patent Attorney Susumu Uchihara #l Figure 2 Cause
Claims (1)
器の反転入力端子に接続され、かつ電流入力端子に導出
された第１の抵抗と、第１のトランジスタと、一端が前
記電圧供給端子に他端が前記差動増幅器の非反転入力端
子及び第１のトランジスタのコレクタに接続された第２
の抵抗と、前記差動増幅器の出力端子がベースに接続き
れ、さらにコレクタが前記第１のトランジスタのベース
に接続され、かつエミッタが前記電圧供給端子に接続さ
れた前記第１のトランジスタと極性の異なる菓２のトラ
ンジスタとを含み、前記第１のトランジスタのエミッタ
から出力電流を得ること全特徴とする電流源回路。a differential amplifier; a first resistor having one end connected to the voltage supply terminal and the other end connected to the inverting input terminal of the differential amplifier and led to the current input terminal; a first transistor; one end connected to the voltage supply terminal; a second transistor, the other end of which is connected to the supply terminal and the non-inverting input terminal of the differential amplifier and the collector of the first transistor;
and the first transistor, the output terminal of the differential amplifier being connected to the base, the collector being connected to the base of the first transistor, and the emitter being connected to the voltage supply terminal. 2. A current source circuit comprising two different transistors, and obtaining an output current from the emitter of the first transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9061682A JPS58207119A (en) | 1982-05-28 | 1982-05-28 | Current source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9061682A JPS58207119A (en) | 1982-05-28 | 1982-05-28 | Current source circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58207119A true JPS58207119A (en) | 1983-12-02 |
Family
ID=14003416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9061682A Pending JPS58207119A (en) | 1982-05-28 | 1982-05-28 | Current source circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58207119A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4546307A (en) * | 1984-01-03 | 1985-10-08 | National Semiconductor Corporation | NPN Transistor current mirror circuit |
| FR2599198A1 (en) * | 1986-05-20 | 1987-11-27 | Sgs Microelettronica Spa | HIGH CAPACITY MIRROR CIRCUIT |
-
1982
- 1982-05-28 JP JP9061682A patent/JPS58207119A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4546307A (en) * | 1984-01-03 | 1985-10-08 | National Semiconductor Corporation | NPN Transistor current mirror circuit |
| FR2599198A1 (en) * | 1986-05-20 | 1987-11-27 | Sgs Microelettronica Spa | HIGH CAPACITY MIRROR CIRCUIT |
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