JPS61162892A - Memory circuit - Google Patents

Abstract

PURPOSE:To heighten reading speed by making the length of the gate of a transistor for balancing bit line short. CONSTITUTION:The gate length L of a P channel type transistor Q103 for balancing bit line is made shorter than other P channel type transistors. When the gate length L is made shorter, subthreshold current I0 increases. In the case where the gate length L is made short until I0 (leak current of high resistance load) and IR become nearly the same, memory cell data are broken by subthreshold current I0 of the transistor Q103 when the word line Xj is high level. Accordingly, subthreshold current I0 is selected to 1/20 of leak current IR of high resistance load. Supposing that the gate length L in this case is LB, subthreshold current I0 of the P channel type transistor Q103 for balancing bit line is 1/20 of IR. Accordingly, absolute value of threshold value voltage of the transistor Q103 becomes smaller than other transistors, and balancing operation of bit line is made easy correspondingly.

Description

[Detailed description of the invention] This invention relates to a memory circuit with improved output time.

[Conventional technology]

An example of a conventional memory circuit is shown in FIGS. 1 and 2.

This will be explained using FIG. 8, 9g, 9 (j, Φ), and FIG. 10, (a), ■). FIG. 8 is a block diagram showing the configuration of the memory circuit, FIGS. 9(a) and 9(b) are circuit diagrams of the address buffer and ψ1 signal generating section, respectively.
10 (ω, (b) is a signal waveform diagram. First, Figure 8, Figure 9 (a), (b), Figure 1, Figure 2.
The figure will be briefly explained. Address buffer 101t-! 7
Dress input signal Al (i=o, 1.2.-.,
From n).

Two address buffer signals Ai', Ai' and an address change detection signal i are created for AI in synchronization with Ai and Al1 in reverse phase with person 1. However, the amount of address change detection signal ψ is determined by the amount of address input signal At It is a signal that detects rising or falling and becomes low level for a certain period of time. Also, chip select input signal δ.

Write enable input signal WE, data input signal DIN
are respectively input to the buffer 102, and a chip select buffer signal C8', a write enable buffer signal WE', and a data input buffer signal DIN'' are generated.
', At' (i=o, 1.2...., n
) Only the j-th word line Xj and the Y-th Y select line Yk, which are uniquely determined by the combination of , are selected, and only one desired memory cell 109 from the memory cell group is selected. DIN control unit 107. The Do/O controller 108 controls writing and reading, respectively. Further, the Φb times signal generator 103 is an AND logic circuit that receives the address change detection signal φ1 (i=0.1.2..., n) and outputs the bit line balance signal φB.

As shown in FIG. 1, the memory cell matrix section 106 has a structure in which memory cells 109 are arranged at each intersection of a plurality of word lines and a plurality of bit lines.

ing. Here, as shown in the memory cell 1091-1.82, four ON-channel type insulated gate field effect transistors (MIS transistors) (hereinafter referred to as transistors) Q1os to Qxos and two high resistance loads R101+ It is assumed that the memory cell is composed of R102. Here, Qloa and Q107 are transformer 7 agate.

Next, a description will be given of the bit line balancing transistor Q10KIC provided between the bits @BL and BLO in the memory cell matrix section 106 shown in FIG. (The one in the box shows the P channel type, and the other one shows the iN channel type.) Therefore, it can be seen that the P8 unbalanced signal φB is in the ON state only during the period when the P8 unbalanced signal φB is at the low level. The role of this bit line balancing transistor Qlos is to equalize the potential of the bit lines BL and BL when switching the address O,
The purpose is to allow read operations to be performed at high speed.

That is, the bit line balance signal φ3 is generated in response to a change in the address input signal A1, and the bit line B
Because L and BL are at equal potential.

When word line Xj rises, the data of the memory cell immediately appears on the bit line. In addition, the state of bit line balance operation &-! , 810 as shown in Figures (a) and (b).

[Problems solved by the invention = 5] However, this conventional example tch has the following drawbacks.

As shown in FIG. 10 (blK), after the cutting operation, the @1'' side potential of the bit line is lower than the 111 side potential of the write bus line.
The level becomes lower by the threshold voltage of the Y-select ON-channel transistor Q104 (or Qloi).

Because of the backgate potential dependence of the threshold voltage, when the source is at a potential much higher than the ground potential GND, the threshold voltage also becomes a larger value than when the source is grounded. For example, when Vcc=5V, the write bus line '''1
The potential on the m side is 5V, and the potential on the bit line σ11 is about 3VlC. -10,000, P-channel transistor Q at the end of the bit line
IOI (or Qtoz) (D t K capability is the ON channel type transistor Q104 (or Qlos
), the bit line @Om side potential is almost equal to the write bus line's o1 side potential,
Approximately QV&C.

Therefore, the bit line balancing operation after the completion of writing is performed for the bit line pair of approximately 3V and approximately 0V. However, the P-channel bit line balancing transistor Ql
For os iC, the source potential is about 2V lower than the back gate potential of this transistor, Vu.
Similar to transistor Q104 (or Qtos), because the threshold voltage depends on the back gate voltage, the absolute value of the threshold voltage is larger than when the source is at Mu potential. For example, when the source is 5VO, the threshold voltage is If SV is 0, then when the source becomes 3vVc, the threshold voltage changes to about -1.4■.

In this case, the gate-to-north voltage of the transistor Q1os is -3V, that is, (threshold voltage) -1.6V, and the electric power is considerably lower than when the source is at VCC potential. As a result, it becomes difficult to perform the bit line balancing operation sufficiently, and even after the bit line backup signal φB returns to high level, the bit line potential remains unbalanced. Such potential imbalances prevent memory cell data from appearing on the bit lines, resulting in slow read times.

As described above, the nine memory circuits 1c are configured as in this conventional example.
However, there was a drawback that the read time after the write operation was delayed.

Accordingly, an object of the present invention is to provide a memory circuit which eliminates the above drawbacks and improves the read time after a write operation.

[Ninth way to solve the problem]

In the memory circuit according to the present invention, the memory cell is composed of a 717 flip-flop and a pair of transfer gates provided between the 7 flip-flop and a pair of bit lines, and the bit line balance is turned on or off by a clock signal VcL. In a memory circuit in which a MIS transistor for bit line balancing is provided between the pair of bit lines, the gate length of the MIS transistor for bit line balancing is set to be the same as the MIS transistor for bit line balancing mounted on the same memory circuit. 3 transistor and all other MIS transistors of the same conductivity type.

The gate length of the 7-star run is short and short, and is set within a range that satisfies the following conditions.

Conditions When Nidorance 7 Argate is turned on and current is injected from the bit line into the memory cell, for the minimum current value that can destroy the data held in the memory cell O,
Bit line balance MID when the gate-source voltage is QV) Reduce the drain current value of the transistor O to 1/10 or less.

[Effect]

If the gate length of the bit line balancing transistor is shortened within a range that satisfies this condition, the absolute threshold voltage of the bit line balancing transistor will increase.

Other transistors of the same conductivity type can be made smaller. As a result, the bit line balance operation after writing is performed sufficiently, and the effect of speeding up the vl start time can be obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

The first embodiment of the present invention is based on the first embodiment in the above conventional example.
P-channel transistor Q for bit line balance shown in the figure
*This is a memory circuit in which the gate length of ox is set to be shorter than that of other OF channel type transistors, and to a value described later.

In FIGS. 4(a) and 4(b), the threshold voltage V? Gate length dependence of subthreshold current engineering. However, when the subthreshold current factor is 0,
is the drain current when the gate-to-north voltage is 0V.

10,000, high resistance load 1 of the memory cell 109 shown in FIG.
Let the leakage current of ot (or RIG!) be 1.

As can be seen from Fig. 4(b), if the gate length Lt is shortened, a subthreshold heavy current circuit is obtained. increases.

If the gate length of the bit line balancing transistor Q1as is shortened until the % 0 and the % are about the same, then when the word line Xj is at a high level, the subthreshold current of the transistor QIOI will be reduced. It is thought that the memory cell data is destroyed by this process, and the mechanism of this data destruction will be briefly explained below.

First, FIG. 3 shows a circuit of a memory cell 109 and a P-channel transistor Qlon for bit line balancing. When word line Xj is at high level, memory cell 109 ON channel type transformer 7 argate Qsos and Qloy
tc is on. Now, if the potential of internal node B of memory cell 109 is VCCt ground potential, then N-channel transistor QIOI + Qt
oe 'C are in the off state and on state, respectively. That is, the potential of the 5th node AOVcc is 1 for the high resistance load R1ot, and the ground potential of the node BO is for the N-channel transistor Qt.
It is maintained by the OS.

Here, if the subthreshold current of the bit line balance P-channel transistor Qlox is changed.

If the leakage current KIi of high resistance load R101 is equal to
The current path I shown in FIG. 3 is formed. Furthermore, if 0 becomes larger than 11 and the node voltage drops to the threshold voltage of the N-channel transistor Ql, the transistor Qlos changes from the on state to the off state 11I.
As a result, the potential of one node B rises from the ground potential to 4Vc, and as a result, the data in the memory cell 109 is destroyed. Therefore, if s IQ and IQ are approximately the same, it can be considered that the memory cell data will be destroyed. So, engineering. Construction work 1
It is necessary to keep it to one-tenth or less.

For the above reasons, in this embodiment, the subthread code IEfiI is used. Let's choose an IK of 20 minutes for a leak current tool with a high resistance load, and let the gate length in this case be written as Ll.

Therefore, the gate length and the threshold voltage VTl in the IC are determined. The value of vi is considerably smaller than the threshold voltage of other P-channel transistors1.For example, the threshold voltage and subthreshold l-ruby current of a general P-channel transistor are -o, sv,
0.05X10A and high resistance load R1o
l (also F'1Rxox) O leakage current I, lXl
Set to 0 A. Then, the subthreshold current of the OP channel type transistor QIOI for bit line balancing. is 1 凰 (1/1020, i.e. 5×10 A
Therefore, the corresponding threshold voltage V? l is approximately 10,6
It becomes v. That is, the absolute value of the 14-value voltage of the bit line balancing transistor Q10m is about 0.2 V smaller than that of the other transistors, and the bit line balancing operation becomes easier to perform.

Book! The signal waveform diagram of the example is WXs diagram (a), (b) VC
As shown in FIG. 10 (8), φ) of the conventional example, the effect of this embodiment is greater in the bit line balance operation after writing, and the bit line balance operation that was caused by the defect O of the conventional example is greater. Sufficient balance is achieved without causing subsequent potential imbalance, and there is no delay in read time.

In the second embodiment of the present invention, in the first embodiment,
In the example in which the memory cell 109 has a CMI8 configuration shown in Figure 86 and is a 9 memory circuit, the memory cell has a CMIS configuration, so the data in the memory cell is held by an on-state transistor. has been done. Therefore.

If an attempt is made to destroy the memory cell data by turning on Qsox and Qaoz and injecting current from the bit line into the memory cell, the current value will be:
l! A considerably larger value than in Example 1, e.g. 1X10
Approximately one person is required. Therefore, if the subthreshold lightning leakage current of the bit line balancing transistor Qlon is determined according to the same method as in the first embodiment, the process will be 0.
to 1×10 AO, i.e. 5×10 people. Figure 4(a).

(b) The threshold voltage VTI corresponding to F and this I is approximately -αIV.

Therefore, in this embodiment, the absolute value of the threshold voltage of the bit line balancing transistor Q10m can be made considerably small.
A memory circuit can be realized in which the bit line balancing operation is sufficiently performed and the object of the present invention is fully achieved. The signal waveform diagrams of this embodiment are shown in Fig. 7 (al, (b)), and compared to Fig. 10 (ml, φ) of the conventional example, the bit line balance operation after the write operation is sufficiently performed. It can be seen that the readout time after the % loading operation is also sufficiently fast.
The effects of the present invention will be apparent.

In the above explanation, a P-channel type is used as the bit line balancing transistor, but it goes without saying that the present invention can be applied in the same way even if an N-channel type is used. Various applications are also possible.

〔Effect of the invention〕

As mentioned above, the present gA can be achieved by simply shortening the gate length of the bit line balancing transistor.

Since the bit line balancing operation can be performed sufficiently, a memory circuit with a high read time can be realized.

[Brief explanation of the drawing]

1 and 2 are the circuit diagrams of the mesori cell matrix section of the embodiment and the conventional example, and the circuit diagram of the memory cell section of the present invention.
Figures (a) and (1)) are a graph of threshold voltage vs. gate longevity, a graph of suppressed threshold current vs. gate length, respectively.
5(a) and 5(b) are signal waveform diagrams showing the first embodiment of the present invention, FIG. 6 is a circuit diagram of the second memory cell portion of the present invention, and FIG. 7(a) ), Φ) are signal waveform diagrams showing the 20th embodiment of the present invention. Block diagram showing the 20th embodiment and the conventional example, FIG. 9(a), (
b) i respectively 1. of the present invention. FIG. 10(a) is an address buffer circuit diagram and a circuit diagram of a φ-signal generating section of the second embodiment and the conventional example. ('b) is a signal waveform diagram showing a conventional example. 101... Address Babu 7, 102...
...Input buffer, 103...ψB signal generation section, 104...X address decoder% 105.
...Y address decoder, 106...Memory cell matrix section, 107...DIN control section, 108...D OtJ? control unit, 10
9...Memory cell, 801...Memory cell% BL. BI,... Bit line h Q, 1oz...
...P-channel type MM3 transistor for bit line balance t Qtos, Q10? ...Transfer gate (N-channel fiMIs transistor). Dln system fq cape f times viewing place f 斥1ryup Lv! v4-den 1 self (1>) pair (0L) g-! r interval < b) ) 工 J-gu saki 藺 (ku) moment (b 7th grade

Claims (1)

[Claims] A memory cell is composed of a flip-flop and a pair of transfer gates provided between the flip-flop and a pair of bit lines, and a bit line balancing MIS transistor that is turned on or off by a clock signal. In the memory circuit provided between the pair of bit lines,
The gate length of the bit line balancing MIS transistor is made shorter than the gate length of all other MIS transistors of the same conductivity type as the bit line balancing MIS transistor mounted on the same memory circuit, and the following conditions are met. A memory circuit characterized by being set within a range that satisfies the following. Conditions: When the transfer gate is turned on and current is injected from the bit line to the memory cell, the minimum current value that can destroy the data held in the memory cell is
To reduce the drain current value of a bit line balancing MIS transistor to 1/10 or less when the gate-source voltage is 0V.