JPH07105152B2 - Non-volatile memory circuit device - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a non-volatile memory circuit device using a non-volatile transistor as a memory cell.

(Prior Art) In a recent nonvolatile memory circuit device, if the power supply voltage is directly supplied to the drain of the memory cell at the time of reading data, the memory cell may be destroyed or erroneous writing may occur. Therefore, in this type of memory circuit, it is necessary to keep the drain voltage of the memory cell low when reading data, and also in that case, it is necessary to ensure reliability during reading.

FIG. 8 is a circuit diagram showing a configuration of a conventional nonvolatile memory circuit device. Note that the write circuit and the like are omitted for the sake of clarity. Positive power supply potential V _CC and node A
An intermediate potential output circuit 30 that outputs a potential lower than the potential V _CC is provided between and. Further, one end of a plurality of column selecting transistors 31 is commonly connected to the node A, and a bit line 32 is connected to the other end of each of the transistors 31. A plurality of word lines 33 are provided so as to intersect these bit lines 32, and a memory cell 34 composed of a non-volatile transistor is arranged at a position where each bit line and the word line intersect. The drain of each memory cell is connected to the corresponding bit line 32, the gate is connected to the corresponding word line 33, and the sources of all the memory cells are connected to the ground potential V _SS . Further, the node A is connected to a sense amplifier 35 composed of a voltage comparator composed of an analog circuit. The sense amplifier 35 includes the above-mentioned intermediate potential output circuit 30.
A potential which is slightly lower than the output potential of the reference potential Vref is supplied as the reference potential Vref, and the sense amplifier 35 compares the potential of the node A with the reference potential Vref to obtain the data Do.
Output ut.

In the memory circuit having such a configuration, the intermediate potential output circuit 30 keeps the potential of the node A lower than the power supply potential V _CC . Therefore, this low potential is applied to the drain of the memory cell selected at the time of reading data, and the destruction of the memory cell and the occurrence of erroneous writing as described above are prevented.

However, the provision of the intermediate potential output circuit 30 limits the potential amplitude of the node A, and it is necessary to use the sense amplifier 35 of a voltage comparator type having a complicated structure by an analog circuit. Such a sense amplifier has a problem that it has a low power supply margin, is difficult to drive at a low voltage, and consumes a large amount of current.

Further, when the memory cell 34 selected at the time of reading data is turned on, a DC through current flows between the power supply potential V _CC and the ground potential V _SS , so that the consumption current is further increased.
Further, the intermediate potential output circuit 30 requires a large current capacity, which causes a problem that the circuit configuration becomes complicated.

(Problems to be Solved by the Invention) As described above, in the conventional nonvolatile memory circuit device, since the potential itself to be detected by the sense amplifier is lowered to prevent destruction of memory cells and erroneous writing, a low voltage There are drawbacks such as being unable to drive with, and consuming a large amount of current.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-volatile memory circuit device that can be driven at a low voltage and consumes less current without lowering reliability during reading. To do.

[Structure of the Invention] (Means for Solving the Problems) In the nonvolatile memory circuit device of the present invention, a memory cell array provided with a plurality of memory cells each including a nonvolatile transistor is connected to a drain of the memory cell. A plurality of column lines, a plurality of column selection transistors each having one end of a current path connected to each of the plurality of column lines, and the other end commonly connected to a first node; 1
A first polarity precharging transistor having a current path formed between the memory cell and a second polarity discharging transistor having a current path formed between the source of the memory cell and the second potential. A potential supply means for selectively supplying a potential lower than the first potential to the gates of the plurality of column selection transistors in response to an address input, and the pre-during precharge connected to the first node. Whether the first state is maintained by being supplied with the first potential through the charging transistor and the second potential is supplied from the memory cell selected at the time of reading through the discharging transistor. Outputs a potential according to the second state or the first state depending on whether or not
It is composed of a latch type sense amplifier composed of a CMOS logic gate circuit.

(Operation) In the nonvolatile memory circuit device according to the present invention, the drain potential of the memory cell is kept low by applying a potential lower than the power supply potential to the gate of the column selection transistor. The potential supply circuit that supplies the gate potential to the column selection transistor only needs to charge the gate capacitance of the column selection transistor, the current capacity of this potential supply circuit can be reduced, and the configuration is simplified.

Further, according to the present invention, the first node to which the sense amplifier is connected is precharged to the power supply potential by the precharge transistor, and the source of each memory cell is discharged by the discharge transistor when the memory cell is selected. No DC through current is generated, and the current consumption can be reduced. Moreover, since the first node to which the sense amplifier is connected is precharged to the first potential which is the power supply potential, the potential amplitude of the first node becomes sufficiently large and the first node is connected to this first node. The sense amplifier can be configured using a logic gate circuit. Therefore, it is possible to improve the power supply margin and reduce the current consumption in the sense amplifier.

(Examples) Hereinafter, the present invention will be described by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory circuit device according to the present invention. Also in this case, the write circuit and the like are omitted for the sake of clarity. A precharging transistor 1 composed of a P-channel MOS transistor is inserted between the positive power supply potential V _CC and the node A which is a data detection node. This transistor 1
A precharge signal Pr is supplied to the gate of the. One end of a plurality of column selecting transistors 2 each composed of an N channel MOS transistor is commonly connected to the node A. A bit line 3 is connected to the other end of each of the column selecting transistors 2. A plurality of word lines 4 are provided so as to intersect these bit lines 3. The plurality of word lines 4 are selectively driven by the output of the row decoder 5 to which the row address is supplied. A memory cell 6 composed of a non-volatile transistor having a floating gate structure is provided at a position where each bit line 3 and each word line 4 intersect with each other.
Are arranged. The drain of each memory cell is connected to the corresponding bit line 3 and the gate is connected to the corresponding word line 4. The sources of all the memory cells 6 are connected to the drain of a discharge transistor 7 which is an N-channel MOS transistor.
The source of the discharging transistor 7 is connected to the ground potential V _SS .

_{Reference numeral} 8 denotes an intermediate potential generation circuit that generates a constant potential V _DD that is lower than the power supply potential V _{CC and} higher than the ground potential V _SS . The potential V _DD generated here is supplied to the column decoder 9 to which the column address is supplied. The column decoder 9 selectively outputs the potential V _DD to the gate of the column selecting transistor 2 based on the column address.

A sense amplifier 10 is connected to the node A. This sense amplifier 10 comprises two CMOS NOR gate circuits 11 and 1
The NOR gate circuit 11 is provided with the potential of the node A, and the other NOR gate circuit 12 is provided with the comparison potential generating circuit 13 for outputting the potential of the node A. The respective comparison potentials Vref are supplied.

The comparison potential generation circuit 13 is composed of a transistor equivalent to the column selection transistor 2 and has a gate supplied with a potential equal to the constant potential V _DD at the time of selecting a memory cell, and the precharge transistor. The transistor 15 is composed of a transistor equivalent to 1 and the gate is supplied with the precharge signal Pr, and a nonvolatile transistor similar to the memory cell 6 so that the current between the source and the drain is about half that of the memory cell 6. And the dummy cell 16 which is set between the dummy cell 16 and the ground potential V _SS and which is composed of a transistor equivalent to the discharge transistor 1 and whose gate is supplied with the precharge signal Pr.
It consists of and.

Next, the data read operation in the memory circuit having such a configuration will be described with reference to the timing chart of FIG. First, when the read control signal Rd is at "H" level, the precharge signal Pr becomes "L" level, and the precharge transistor 1 is turned on. As a result, the node A is precharged to the power supply potential V _CC (precharge period Tp). At this time, the discharge transistor 7 is turned off and the power supply potential V
_No DC through current flows between _CC and the ground potential V _SS . On the other hand, also in the comparison potential generation circuit 13, the transistor 15 is turned on and the transistor 17 is turned off, so that the node B connected to the sense amplifier 10 is precharged to the power supply potential V _CC . In this case, nodes A and B are both at V _CC level,
That is, since it becomes "H" level, the output data Dout of the sense amplifier 10 becomes "L" level.

Next, the column and row address ADD is supplied to the column decoder 9 and the row decoder 5, and the precharge signal Pr changes from "L" level to "H" level. When the precharge signal Pr changes to "H" level, the transistor 7 is turned on, and the period for reading data is started (discharge period Td). First, the source of each memory cell 6 is set to the ground potential by turning on the transistor 7. Further, one of the column selecting transistors 2 is selected by the column decoder 9 according to the column address, and the constant potential V _DD from the intermediate potential generating circuit 8 is applied to the gate of the selected transistor 2. This turns on the column selection transistor 2, but its gate potential is the power supply potential V _CC.
Since this value is lower than
A potential lower than the power supply potential V _CC is output to the bit line 3 connected to. On the other hand, either 1 depending on the row address
The word line 4 of the book is selected by the row decoder 5. As a result, the "H" level drive signal is applied to the gate of the memory cell 6 connected to the selected word line 4.
As a result, the memory cell arranged at the intersection of the bit line outputting the potential lower than the power supply potential V _CC and the selected word line is selected. Now, if the selected memory cell is programmed with a low threshold voltage,
This memory cell is turned on, and the bit line 3 and node A are discharged to the ground potential V _SS . If the selected memory cell is programmed with a high threshold voltage, this memory cell is turned off and the bit line 3
And node A is not discharged.

On the other hand, in the comparison potential generation circuit 13, the precharge signal Pr
Changes to the "H" level to turn on the transistor 17 and when any one of the column selecting transistors 2 is selected, the intermediate potential V _DD is simultaneously supplied to the gate of the transistor 14. This allows Node B
Is discharged from V _CC . Now, when the threshold voltage of the selected memory cell 6 is low and the potential of the node A is discharged, the current between the source and drain of the dummy cell 16 of the comparison potential generation circuit 13 is about half that of the memory cell 6. Since it is set to
The potential of the node A approaches V _SS faster than the potential of the node B, and the output data Dout of the sense amplifier 10 is inverted from the “L” level to the “H” level. When the threshold voltage of the selected memory cell 6 is high, the potential of the node A is not discharged and the potential of the node B is discharged.
The output data Dout of the sense amplifier 10 remains unchanged at the original “L” level. In this way, data is read from the selected memory cell.

Here, since a potential lower than the power supply potential V _CC is applied to each bit line 3, it is possible to prevent the destruction and erroneous writing of the memory cell as in the conventional case.

In the data reading period, the transistor 1 precharges the first node A to the power supply potential, and then,
The source of each memory cell 6 is discharged to the ground potential by the transistor 7, and no DC through current is generated between the power supply potential and the ground potential. Therefore, current consumption can be reduced.

Furthermore, in the intermediate potential generation circuit 8 that generates a potential lower than the power supply potential, since it is sufficient to drive the gate of the column selection transistor 2, the current capacity can be small, and the current consumption can be reduced and the configuration can be simplified. Can be planned.

Moreover, the potential of the node A is the power supply potential V _CC and the ground potential V _SS.
Since the sense amplifier 10 has a simple configuration using a logic gate circuit including NOR gate circuits 11 and 12 as shown in the figure, the current consumption can be reduced. Moreover, if the NOR gate circuits 11 and 12 having the CMOS structure are used, the current consumption is further reduced. As described above, the flip-flop type logic circuit has advantages such as stable circuit operation in a wide voltage range, low power consumption, and low voltage driving.

FIG. 2 is a circuit diagram showing the configuration of another embodiment of the non-volatile memory circuit device of the present invention. In this embodiment circuit, between the node A which is the common connection end of the plurality of column selecting transistors 2 and the other end of the precharge transistor 1 whose one end is connected to the first potential, the gate is at the intermediate potential V. A level down transistor 18 to which _DD is supplied is inserted to selectively supply the bit line 3 via the column selection transistor 2 with a potential lower than the power supply potential V _CC which is the first potential. It was done. Along with this, in the comparison potential generation circuit 13, a transistor 19 is inserted between the dummy cell 16 and the transistor 14 so that the gate is supplied with the power supply potential V _CC and is equivalent to the column selection transistor 2. It Then, the NOR gate circuit 11 in the sense amplifier 10
Is supplied with the potential of the connection node C between the precharging transistor 1 and the level-down transistor 18.

The data read operation in the apparatus of the embodiment shown in FIG. 2 is the same as that shown in the timing chart of FIG. Also,
According to the apparatus of the embodiment shown in FIG. 2, the degree of integration is further excellent. That is, in the device of the embodiment shown in FIG.
V _DD is supplied to the column decoder 9. Therefore, in the column decoder 9, the column selection transistor 2
It is necessary to install a buffer (not shown) composed of a CMOS circuit or the like in order to supply a potential lower than the power-source potential V _CC which is the first potential to each gate of, and the pattern area tends to increase. . In the embodiment of FIG. 2 described above, since only one level-down transistor 18 needs to be provided for a plurality of column selecting transistors, the pattern area is increased as compared with the case where many buffers are provided as described above. Is small.

Further, since the capacity and resistance of the column decoder increase as the capacity increases, the number of circuits serving as delay elements such as the above-mentioned buffer is reduced, and the operational reliability is improved.

4 and 5 and 6 are circuit diagrams showing a concrete configuration of the intermediate potential generating circuit 8 used in each of the above-described embodiments.

In the circuit of FIG. 4, P is _placed between the power supply potential V _CC and the ground potential V _SS.
A switch transistor 20 composed of a channel MOS transistor and two resistors 21 and 22 are connected in series, and the switch transistor 20 is set to an “L” level when reading data, for example, a reverse phase signal of the read control signal Rd. ▼
The continuity is controlled by. In this circuit,
During the period other than the data read period, the transistor 20 is turned off and no current is consumed. On the other hand, during the data reading period, the transistor 20 is turned on, and the potential V _DD lower than V _CC divided by the two resistors 21 and 22 is output.

In the circuit shown in FIG. 5, P is _placed between the power supply potential V _CC and the ground potential V _SS.
A switching transistor 23 composed of a channel MOS transistor and a plurality of P-channel MOS transistors 24 are connected in series, and the switching transistor 23 is connected to the signal ▲ ▼.
The continuity is controlled by. Even in this circuit,
During the period other than the data reading period, the transistor 23 is turned off and no current is consumed. Also, during the data read period, the transistor 23 is turned on, and V _CC divided by the switching transistor 23 and the plurality of transistors 24 is used.
Lower potential V _DD is output.

In the circuit of FIG. 6, between the power supply potential V _CC and the ground potential V _SS , a switching transistor 25 composed of a P-channel MOS transistor, a depletion type N-channel MOS transistor 26, and an intrinsic type (threshold value is approximately 0 V). An N-channel MOS transistor 27 is connected in series, and the output node D is configured by commonly connecting the gates and one ends of the transistors 26 and 27 to each other, and the switching transistor 25 is controlled to be conductive by the signal ▲ ▼. It is the one. Also in this circuit, the transistor 25 is turned off except during the data reading period, and no current is consumed. In the data read period, the transistor 25
Is turned on, and the voltage V _DD at which the drain voltage of the switching transistor 25 is lower than V _CC divided by the ON resistance of the transistors 26 and 27 is output to the node D. According to this configuration, since the gates of the transistors 26 and 27 and the node D are short-circuited, a constant intermediate potential is always output even if the power supply potential V _CC fluctuates to some extent.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, the sources of the memory cells may be commonly connected to the discharge transistor 7 and the discharge transistor 7 may be shared by all the memory cells, or, as shown in the circuit diagram of FIG. An independent discharge transistor 7 may be provided for each 6. Further, the intermediate potential generating circuit 8, the sense amplifier 10 and the like are not limited to the illustrated configurations, and various circuit configurations can be used.

[Effects of the Invention] As described in detail above, according to the present invention, a non-volatile memory circuit device that realizes circuit simplification without lowering reliability during reading, and that is driven with low power consumption and low voltage is provided. Can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory circuit device according to the present invention, FIG. 2 is a circuit diagram showing a configuration of another embodiment of the nonvolatile memory circuit device according to the present invention, and FIG. Timing charts for explaining the operation of the circuits of FIGS. 1 and 2, FIGS. 4 to 7 are circuit diagrams showing a partial configuration in the circuits of FIGS. 1 and 2, and FIG. FIG. 6 is a circuit diagram showing a configuration of a conventional nonvolatile memory circuit device. 1 ... Precharge transistor, 2 ... Column selection transistor, 3 ... Bit line, 4 ... Word line, 5 ...
Row decoder, 6,16 ... Memory cell, 7 ... Discharge transistor, 8 ... Intermediate potential generation circuit, 9 ... Column decoder, 10 ... Sense amplifier, 11, 12 ... NOR gate,
13 ... Comparison potential generation circuit, 14, 17 ... N-channel MOS transistor, 15 ... P-channel MOS transistor. 18 ……
Level-down transistor.

Claims (4)

[Claims] 1. A memory cell array provided with a plurality of memory cells composed of non-volatile transistors, a plurality of column lines to which the drains of the memory cells are connected, and one end of a current path is provided with the plurality of column lines. A plurality of column selecting transistors which are respectively connected to each other and whose other end is commonly connected to a first node, and a first polarity precharge in which a current path is formed between a first potential and the first node. Transistor, a discharge transistor of a second polarity in which a current path is formed between the source of the memory cell and a second potential, and the gates of the plurality of column selecting transistors in response to an address input. A potential supply means for selectively supplying a potential lower than a potential of 1, and the above-mentioned precharge transistor which is connected to the first node and is connected to the first node during precharge. The first state is maintained by being supplied with the first potential, and the second state is determined depending on whether or not the second potential is supplied from the memory cell selected at the time of reading via the discharge transistor. A CMOS that outputs a potential according to the first state
A non-volatile memory circuit device comprising a latch type sense amplifier including a logic gate circuit. 2. The non-volatile memory circuit device according to claim 1, wherein the latch type sense amplifier is composed of a NOR type flip-flop and compares the potential of the first node with a comparison potential. 3. A memory cell array provided with a plurality of memory cells each comprising a non-volatile transistor, a plurality of column lines to which the drains of the memory cells are connected, and one end of each current passage has each of the plurality of column lines. A plurality of column selection transistors, which are connected to each other and whose other end is commonly connected to the first node, and a first polarity precharge in which a current path is formed between the first potential and the second node. A transistor, a second polarity discharge transistor having a current path formed between the source of the memory cell and a second potential, and a current path formed between the first node and the second node. And a second polarity level-down transistor whose gate is supplied with a potential lower than the first potential at the time of reading from the memory cell, and is connected to the second node. The first state is maintained by being supplied with the first potential through the precharge transistor during charge, and the second potential is supplied from the selected memory cell during read through the discharge transistor. CMOS that outputs a potential according to the second state or the first state depending on whether or not it is supplied
A non-volatile memory circuit device comprising a latch type sense amplifier including a logic gate circuit. 4. The non-volatile memory circuit device according to claim 2, wherein the latch type sense amplifier is composed of a NOR type flip-flop and compares the potential of the second node with a comparison potential.