JPH0676580A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the driving load on the output signal line of a switching control circuit for writing and reading operations by deciding the state of a couple of external input complementary signals generated on the basis of write data and controlling the active/inactive state of a differential amplifier circuit. CONSTITUTION:When data are inputted from a data input terminal D at the time of writing, the output signal WET of the writing/reading operation switching control circuit goes down to L and the complementary signals GWS corresponding to the data are generated. The write state is decided on the basis of the complementary state between the signals GWB and a decision circuit WRC outputs decision outputs SBRB and SBR to turn OFF a load circuit LD1 common to differential amplifiers BLSA1-BLSAn connected to respective bit line couples BL1-BLn and also make a differential amplifier BSA for the circuit LD1 inactive. Consequently, the driving load of the output signal of the reading operation switching control circuit is reduced to enable high-speed writing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device in which activation of the differential amplifier circuit is controlled by a pair of complementary signals generated based on write data.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional semiconductor memory device. In the figure, 1 is a cell array, 3 is a column decoder having a column address coupled to the cell array 1 through an I / O control circuit 12, and 7 Is a row decoder having a row address combined with the cell array 1, 14 is a chip enable control circuit (CS), 15 is a circuit (WE) for controlling switching between write and read operations, and 16 is a combination with the I / O control circuit 12. Input / output circuit (I / O BUF). Data is input / output to / from the input / output circuit 16, and control signals are sent to the chip enable control circuit 14 and the control circuit 1.
5 and are supplied.

FIG. 5 is a circuit diagram of an input / output circuit connected to a bit line pair of a semiconductor memory device of the prior art and a decode circuit for selecting them, in which BL1, BL2 and BLn are bit line pairs. , BLSA1, BLSA
2 and BLSAn are provided respectively corresponding to each bit line pair, and the output signal line pair and the load circuit are made common, and LD1 is the differential amplifier circuit B.
A load circuit common to LSA1, BLSA2 and BLSAn, and RB1 is the differential amplifier circuit BLSA1, BLSA.
2 and BLSAn have a common output signal line pair SR1, S
R2 and SRn are the differential amplifier circuit BLSA, respectively.
1, the first selection signal line of BLSA2 and BLSAn,
DTR1, DTR2 and DTRn are provided corresponding to each bit line pair respectively, and are transfer gate circuits for transmitting write data to the corresponding bit line pair, WB1 is a write data line pair, and SW1, SW2 and SWn are Each of the transfer gate circuits DT
BL on the second selection signal line of R1, DTR2 and DTRn
D1, BLD2, and BLDn are bit line pair selection decoding circuits provided corresponding to each bit line pair, and GWB is a global write data line pair.
TR is a transfer gate circuit for connecting the write data line pair WB1 and GWB, BSA is a differential amplifier circuit, and SBW is the decode circuits BLD1 and BLD2.
And BLDn and transfer gate circuit BTR
Is a third selection signal line of the differential amplifier circuit BSA.
Is a fourth selection signal line, WES is an output signal line of a circuit that controls switching between writing and reading operations of the semiconductor memory device, and BD is a memory divided into a plurality of circuits including all the circuits described above in the semiconductor memory device. A decoding circuit for selecting a cell block.

Next, the operation of the conventional semiconductor memory device shown in FIG. 5 will be described. A decode circuit BD for selecting a memory cell block receives a decode signal of an address signal input to the semiconductor memory device and receives a bit line pair BLD1,
BLD2 and BLDn and select signal line SBW of transfer gate circuit BTR are generated, and the decode signal of the address signal and the writing of the semiconductor memory device are performed,
Output signal line WE of circuit for controlling switching of read operation
The logic of S is taken to generate the selection signal SBR. Also,
Bit line pair selection decoding circuits BLD1, BLD2 and BLD provided corresponding to each bit line pair.
n is provided corresponding to each bit line pair for receiving the decode signal of the address signal and the selection signal SBW input to the semiconductor memory device, and a transfer gate circuit DT for transmitting write data to the corresponding bit line pair.
R1, DTR2 and DTRn selection signals SW1, SW
2 and SWn as well as the decoding of the address signal, the selection signal SBW, and the writing of the semiconductor memory device,
Output signal line WE of circuit for controlling switching of read operation
The logic of S is taken and provided corresponding to each bit line pair, and the differential amplifier circuit selection signals (SR1, SR2, SRn) common to the output line pair and the load circuit are generated.

Now, when the semiconductor memory device including the circuit of FIG. 5 is in a write operation state, the decoding circuit BD causes the memory cell block of FIG. 5 and the bit line pair BL included therein.
Bit line pair BL1 which is one of 1, BL2 and BLn
Is selected, the selection signals SBW and SW1 change to "High".
It becomes the potential "h" and the transfer gate circuits BTR and DT
When R1 is in the "ON" state, the data line pair GWB, the write data line WB1 and the bit line pair BL1 are electrically connected, and the write data input to the semiconductor memory device is transmitted to the write data line WB1 through the data line pair GWB.
It is transmitted to the bit line pair BL1. Further, since the semiconductor memory device is in the writing state, the output signal line WES is
The potential becomes “High”, the selection signal lines SBR and SR1 become “Low” potential, and the differential amplifier circuits BLSA1 and BSA
Is deselected and power consumption is reduced.

[0006]

The above-mentioned conventional input / output circuits connected to the bit line pairs of the semiconductor memory device and the decoding circuit for selecting them are provided corresponding to each bit selection pair. A differential amplifier circuit having a common output signal line pair and a load circuit, and a signal line that is provided corresponding to each bit line pair and selects a transfer gate circuit for transmitting write data to the corresponding bit line pair. Are selected signal lines SR1, S as shown in FIG.
R2 and SRn and selection signal lines SW1, SW2 and S
Bit line pair selection decoding circuits BLD1, BLD2, and BLDn provided corresponding to each bit line pair in order to reduce power consumption by separating into Wn and deselecting the differential amplifier circuit during the write operation. Is a decoding circuit for generating selection signal lines SW1, SW2 and SWn therein and selection signal lines SW1, SW2 and S
It must have two circuits, a decode circuit to generate Wn. Therefore, the problem that the occupied area in the semiconductor memory device of the bit line pair selection decoding circuit provided corresponding to each bit line pair increases and the output signal of the circuit that controls the switching of the write and read operations There is a problem that the driving load of the line increases.

[0007]

A semiconductor memory device of the present invention is provided with a plurality of memory cells arranged in an array in both row and column directions and correspondingly provided for each column of these memory cells. A memory cell array including a plurality of bit line pairs respectively connected to the memory cells of the columns and a plurality of word lines respectively provided for each row of the memory cells and connected to the memory cells of the corresponding row; A plurality of first differential amplifier circuits that are supplied corresponding to some of the bit line pairs, and write data that are provided respectively corresponding to some of the plurality of bit line pairs when activated. From one of the plurality of pairs of transfer gate circuits for transmitting the true signal and the complementary signal displayed by the corresponding bit line pair, and the selected first differential amplifier circuit. It receives the resulting output, second amplifying
And a control circuit for deactivating the second differential amplifier circuit in response to the true signal and the complementary signal displayed by the write data.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device of the present invention, in which 1 is a cell array, 2 is an I / O (input / output) control circuit, and 3 is an I / O control circuit 2 and is connected to the cell array 1. A column decoder having a selected column address, 7 a row decoder having a row address coupled to the cell array 1, 4 a chip enable control circuit (CS), 5 a circuit for controlling switching between write and read operations (W
E) and 6 are input / output circuits (I / O BUF) connected to the I / O control circuit 2. Data is input / output to / from the input / output circuit 6, and a control signal is supplied to the chip enable control circuit 4 and the control circuit 5. The chip enable control circuit 4 outputs the signal CST to the column decoder 3 and the input / output circuit 6, and the control circuit 5 outputs the signal WET to the input / output circuit 6.

FIG. 2 is a circuit diagram of an input / output circuit connected to a bit line pair of the semiconductor memory device of the first embodiment of the present invention and a decode circuit for selecting them, and BL1, BL1 in the figure.
BL2 and BLn are bit line pairs, and BLSA1 and BLSA
2, BLSAn are provided corresponding to each bit line pair, and the output signal line pair and the load circuit are common to each other, and LD1 is the differential amplifier circuit BLSA1, BSA.
A load circuit common to LSA2 and BLSAn, which is composed of a P channel type insulated gate field effect transistor,
Is the differential amplifier circuits BLSA1, BLSA2 and BL
Output signal line pairs common to SAn, DTR1, DTR2, and DTRn are provided corresponding to each bit line pair, and are transfer gate circuits for transmitting write data to the corresponding bit line pairs, and WB1 is write data. Line pairs SS1, SS2 and SSn are the differential amplifier circuits BLSA1, BLSA2 and BLSA, respectively.
n and transfer gate circuits DTR1, DTR2
BLD1, BLD2, and BLDn in the selection signal lines of DTRn and DTRn are bit line pair selection decoding circuits provided corresponding to each bit line pair, GWB is a global write data line pair, and BTR is the write data. A transfer gate circuit for connecting the line WB1 and the data line pair GWB, BSA is a differential amplifier circuit, and S
BW The decoding circuits BLD1, BLD2 and BLD
n is the third selection signal of the transfer gate circuit BTR, SBR is the fourth selection signal of the differential amplifier circuit BSA, and WRC is the semiconductor memory device in the writing state or the reading state depending on the state of the write data line pair GWB. BD is a decoding circuit for selecting a plurality of divided memory cell blocks including the preceding circuit in the semiconductor memory device.

FIG. 6 is a logic circuit diagram of an input / output circuit which is a part of an input / output circuit of a general semiconductor memory device. DIN is an external input terminal, and GWB is a write data input from the external input terminal. It is a global write data line pair that outputs a pair of complementary signals generated based on the above.

Next, the operation of the semiconductor memory device of the first embodiment of the present invention will be described.

Decode circuit BD for selecting a memory cell block receives decode signals of the address signal input to the semiconductor memory device and decode circuits BLD1 and BLD.
D2 and BLDn and transfer gate circuit B
The TR select signal line SBW is generated. The bit line pair selection decode circuits BLD1, BLD2, and BLDn provided corresponding to each bit line pair receive the decode signal of the address signal and the selection signal SBW input to the semiconductor memory device, and each bit line pair. And transfer gate circuits DTR1 and DT for transmitting write data to corresponding bit line pairs.
Differential amplifier circuits BLSA1, BLSA2, BLSA provided corresponding to R2 and DTRn and bit line pairs, respectively, and sharing the output signal line pair and the load circuit.
It generates n select signals SS1, SS2 and SSn.

Now, when the semiconductor memory device including the circuits of FIGS. 2 and 6 is in a write operation state, the decoding circuit BD is one of the memory cell block of FIG. 4 and bit line pairs BL1, BL2 and BLn included therein. Bit line pair is selected and external write data input is input terminal DI
When it is given to N, it is in the write operation state, so the output signal W of the circuit for controlling the switching of the write and read operations.
ET has a "Low" potential, a complementary signal is output to the data line pair GWB according to the data input to the input terminal DIN, and the selection signals SBW and SS1 have a "High" potential, so that the transfer gate circuits BTR and DTR have an "O" level.
It becomes the N "state and the data line pair GWB and the write data line W.
B1 and the bit line pair BL1 are electrically connected to each other, and the write data input to the semiconductor memory device is transmitted to the write data line WB1 through the data line pair GWB and is transmitted to the bit line pair BL1. Since the data line pair GWB is in the written state, one of the data line pairs GWB has a “High” potential or a “Low” potential, and the other one has a “Low” potential or a “High” potential.
One output signal SBRB becomes the "High" potential, the other output signal SBR becomes the "Low" potential, the differential amplifier circuit BSA is deselected, the power consumption is reduced, and each bit line pair is provided correspondingly. , The signal line SBRB that controls the common load circuit LD1 of the differential amplifier circuit that shares the output signal line pair and the load circuit becomes the "High" potential, and the load circuit LD1 is set to the "OFF" state to correspond to each bit line pair. Differential amplifier circuits BLSA1 and BLS, which are provided in common and share the output signal line pair with the load circuit.
A2 and BLSAn are unselected, and power consumption is reduced.

On the other hand, during the data read operation, the signal WET
Since (FIG. 6) becomes high level, the write data line pair G
Both WB become high level. The output of the discrimination circuit WRC becomes high level, the differential circuit BSA is activated, and the NAND gate in the circuit WRC generates low level output, so that the P-channel insulated gate field effect transistor in the load circuit LD1 is generated. Turns on. Since the write data line pair GWB and WB1 are both at the high level, the transfer gate BTR is turned off.

On the other hand, a word line (not shown) is selected by the read address, and the store data of the memory cell connected to the selected word line is the bit line pair BL1, BL.
2 ,. ． ． It appears as a potential difference between BLn. It is assumed that the decoder BLD1 sets its output SS1 to the active high level according to the read address. An active high level also appears at the gate of the transfer gate DTR1,
The write data line pair WB1 is at a high level, but the bit line pair BL1 is not shown in the load circuit (load circuit LD1
Connected to Vcc via the same configuration), the high level of the write data line pair WB1 changes to the bit line pair BL1.
It has virtually no effect on the potential difference based on the store data appearing above. The potential difference is amplified by the differential amplifier BLSA1, appears in the common load LD1, and further amplified by the differential amplifier BSA to obtain read data.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG.

The semiconductor memory device of the second embodiment of the present invention has an input / output circuit connected to a bit line pair and a decode circuit for selecting them, and BL1 and BL2 in the figure.
And BLn are provided corresponding to each bit line pair, and the output signal line pair and the load circuit are common to the differential amplifier circuit, and LD1 is the above-mentioned BLSA1, BLSA2, BLS.
The load circuit common to An is composed of an N-channel type insulated gate field effect transistor. The difference between this embodiment and the above-described first embodiment is that the insulated gate field effect transistor constituting the load circuit LD1 is changed from a P channel type insulated gate field effect transistor to an N channel type insulated gate field effect transistor, and its control is performed. Since the function and effect of each circuit and signal line are the same as those of the first embodiment shown in FIG. 2 except that the signal SBRB is changed to the opposite phase signal SBR, the description thereof will be omitted.

[0019]

As described above, according to the present invention, the semiconductor memory device writes data according to the state of the global write data line GWB which outputs a pair of complementary signals generated based on the write data input from the external input terminal. It has a judgment circuit for judging whether it is a state or a reading state,
By controlling activation / deactivation of the differential amplifier circuit by the output signal, there is an effect that the driving load of the output signal of the circuit for controlling the switching of the read operation can be reduced and the circuit operation can be speeded up.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram of an input / output circuit connected to a bit line pair and a decode circuit for selecting them in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an input / output circuit connected to a bit line pair of a semiconductor memory device of a second embodiment of the present invention and a decode circuit for selecting them.

FIG. 4 is a schematic configuration diagram of a conventional semiconductor memory device.

FIG. 5 is a circuit diagram of an input / output circuit connected to a bit line pair of a conventional semiconductor memory device and a decode circuit for selecting them.

FIG. 6 is a partial input logic circuit of an input / output circuit of a general semiconductor memory device.

[Explanation of symbols]

1 memory cell array 2, 12 I / O control circuit 3 column decoder 4, 14, CS chip enable control circuit 5, 15, WE write / read operation switching control circuit 6, 16 I / OBUF BLD1, BLD2, BLDn bit line pair selection Decoding circuit BL1, BL2, BLn Bit line pair BLSA1, BLSA2, BLSAn, BSA Differential amplifier circuit BD Decoding circuit DTR1, DTR2. DTRn Transfer gate circuit LD1 Load circuit SS1, SS2, SSn, SBR, SBW, SR1, S
R2, SRn, SW1, SW2, SWn selection signal line WRC judgment circuit WES output signal line WB1 write data line

Claims (4)

[Claims] 1. A plurality of memory cells arranged in an array in both row and column directions, and a plurality of bit lines provided corresponding to each column of the memory cells and connected to the memory cells of the corresponding columns, respectively. A memory cell array including a plurality of word lines provided corresponding to each pair of rows and the memory cells and connected to the memory cells of the corresponding row, and a plurality of bit line pairs corresponding to some of the bit line pairs. A plurality of first differential amplifier circuits, which are provided corresponding to some of the plurality of bit line pairs, respectively, and correspond to a true signal and a complementary signal displayed by write data when activated. A plurality of pairs of transfer gate circuits for transmitting to the bit line pair, and a second differential for receiving and amplifying an output obtained from one of the selected first differential amplifier circuits A semiconductor memory device comprising: an amplifier circuit; and a control circuit which deactivates the second differential amplifier circuit in response to a true signal and a complementary signal displayed by the write data. 2. The semiconductor memory device according to claim 1, wherein the first differential amplifier circuit has a common load circuit. 3. The common load circuit comprises an insulated gate field effect transistor which is in an “OFF” state when the second differential amplifier circuit is deactivated. Semiconductor memory device. 4. The semiconductor memory device according to claim 2, wherein one of the first differential amplifier circuit and one of the plurality of pairs of transfer gates are simultaneously activated by one set of address signals.