JPS61161797A - Multilayer printed circuit board - Google Patents

Multilayer printed circuit board

Info

Publication number
JPS61161797A
JPS61161797A JP274885A JP274885A JPS61161797A JP S61161797 A JPS61161797 A JP S61161797A JP 274885 A JP274885 A JP 274885A JP 274885 A JP274885 A JP 274885A JP S61161797 A JPS61161797 A JP S61161797A
Authority
JP
Japan
Prior art keywords
pattern
multilayer printed
layer
printed board
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP274885A
Other languages
Japanese (ja)
Inventor
金子 浩美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP274885A priority Critical patent/JPS61161797A/en
Publication of JPS61161797A publication Critical patent/JPS61161797A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は多層プリント板に関し、特に雑音特性の改善さ
れた電子回路の多層プリント板の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer printed board, and more particularly to a structure of a multilayer printed board for electronic circuits with improved noise characteristics.

〔従来の技術〕[Conventional technology]

従来、電子回路用の多層プリント板はプリント板の内部
のパターン層を電源パターン、グランドパターンとし、
表面側のパターン層を信号パターンとして使用している
Conventionally, multilayer printed boards for electronic circuits use the internal pattern layer of the printed board as a power supply pattern and a ground pattern.
The pattern layer on the front side is used as a signal pattern.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の多層プリント板は信号ラインがプリント
板の表面に存在するため、信号ラインから外部へ雑音成
分がanたり、外部からの雑音成分を伶つて電子回路の
雑音を増大させるという欠点があった。
The above-mentioned conventional multilayer printed circuit board has signal lines on the surface of the printed circuit board, so it has the disadvantage that noise components are transmitted from the signal lines to the outside, and noise components from the outside are mixed up, increasing the noise of the electronic circuit. Ta.

本発明の多層プリント板は上記問題点に対処してなされ
たもので、信号ラインから外部への雑音成分が漏れるの
を防ぎ、又外部から雑音成分が混入するのを防止するこ
とが可能な多層プリント板を得ることを目的とする。
The multilayer printed board of the present invention has been made to address the above problems, and is a multilayer printed board that can prevent noise components from leaking from the signal line to the outside, and can also prevent noise components from entering from the outside. The purpose is to obtain printed boards.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の多層プリント板は、三層以上の多層プリント板
において、表面の各層を全面グランドパターンと全面電
源パターンとすることにより構成さnる。
The multilayer printed board of the present invention is a multilayer printed board with three or more layers, and is constructed by forming each surface layer into a ground pattern and a power pattern on the entire surface.

〔実施例〕〔Example〕

次に、本発明の実施例について、図面を参照して説明す
る。第1図は本発明の一実施例である4層プリント板の
斜視図であり、第2図は第1図の断面図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view of a four-layer printed board according to an embodiment of the present invention, and FIG. 2 is a sectional view of FIG. 1.

第1図及び第2図において、パターン1層1の全面を電
源のパターンとし、下側の表面層であるパターン41−
4の全面をグランドパターンとし、内層であるパターン
2層2、及びパターン3層3を信号ラインに使用する。
In FIGS. 1 and 2, the entire surface of pattern 1 layer 1 is used as a power supply pattern, and the lower surface layer is pattern 41-
The entire surface of 4 is used as a ground pattern, and the inner layers, pattern 2 layer 2 and pattern 3 layer 3, are used for signal lines.

このように電源パターンのパターン1層1とグランドパ
ターンのパターン41−4で信号ラインをはさみ込むこ
とにより信号ラインから外部へ雑音成分が漏nるのを防
ぎ、又外部より信号ラインに雑音成分が混入するのを防
ぐことができる。
By sandwiching the signal line between the power supply pattern layer 1 and the ground pattern 41-4, it is possible to prevent noise components from leaking from the signal line to the outside, and to prevent noise components from entering the signal line from the outside. Contamination can be prevented.

なお上記実施例では4層プリント板につき説明したが、
こn以外の多層プリント板に於ても、表面の各パターン
層全面を電源パターンとグランドパターンとすることに
より同様の効果が得られる。
Note that in the above embodiment, a four-layer printed board was explained.
Similar effects can be obtained in multilayer printed boards other than this one by using the entire surface of each pattern layer as a power supply pattern and a ground pattern.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によ几ば、多層プリント板
の表面の各パターン層を電源とグランドにすることによ
り、雑音成分が外部へ漏れるのを防ぎ、又外部より雑音
成分が混入するのを防止することができ、雑音につよい
電子回路を構成することが出来る。
As explained above, according to the present invention, each pattern layer on the surface of a multilayer printed board is used as a power supply and a ground, thereby preventing noise components from leaking to the outside and preventing noise components from entering from the outside. Therefore, it is possible to configure an electronic circuit that is resistant to noise.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の4層プリント板の斜視図、
8J2図は第1図に示した実施例の断面図である。 1・・・・・・パターン1層、2・・・・・・ノ(ター
ン層、3・・−・・・パターン3層、4・・・・・・パ
ターン4111m、5・・・・・・絶縁層、6・・・・
・・4層プリント板。
FIG. 1 is a perspective view of a four-layer printed board according to an embodiment of the present invention;
FIG. 8J2 is a sectional view of the embodiment shown in FIG. 1. 1...Pattern 1 layer, 2......No (turn layer, 3...Pattern 3 layer, 4...Pattern 4111m, 5......・Insulating layer, 6...
...4-layer printed board.

Claims (1)

【特許請求の範囲】[Claims] 三層以上の多層プリント板において、表面の各層を全面
グランドパターンと全面電源パターンとしたことを特徴
とする多層プリント板。
A multilayer printed board having three or more layers, characterized in that each layer on the surface has a ground pattern and a power pattern on the entire surface.
JP274885A 1985-01-11 1985-01-11 Multilayer printed circuit board Pending JPS61161797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP274885A JPS61161797A (en) 1985-01-11 1985-01-11 Multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP274885A JPS61161797A (en) 1985-01-11 1985-01-11 Multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS61161797A true JPS61161797A (en) 1986-07-22

Family

ID=11537966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP274885A Pending JPS61161797A (en) 1985-01-11 1985-01-11 Multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS61161797A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63119292A (en) * 1986-11-07 1988-05-23 日本電気株式会社 Multilayer interconnection board
JPS63155791A (en) * 1986-12-19 1988-06-28 日本電気株式会社 High density multilayer interconnection board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63119292A (en) * 1986-11-07 1988-05-23 日本電気株式会社 Multilayer interconnection board
JPS63155791A (en) * 1986-12-19 1988-06-28 日本電気株式会社 High density multilayer interconnection board

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