JPS61161717A - Formation of gate electrode pattern - Google Patents
Formation of gate electrode patternInfo
- Publication number
- JPS61161717A JPS61161717A JP311185A JP311185A JPS61161717A JP S61161717 A JPS61161717 A JP S61161717A JP 311185 A JP311185 A JP 311185A JP 311185 A JP311185 A JP 311185A JP S61161717 A JPS61161717 A JP S61161717A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- electrode pattern
- ions
- electrode material
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000007772 electrode material Substances 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 229910052742 iron Inorganic materials 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 11
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 4
- 239000003039 volatile agent Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 2
- -1 iron ions Chemical class 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 claims 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims 1
- 229910001431 copper ion Inorganic materials 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- 229910021341 titanium silicide Inorganic materials 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 9
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 101100536577 Caenorhabditis elegans cct-4 gene Proteins 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101000653567 Homo sapiens T-complex protein 1 subunit delta Proteins 0.000 description 1
- 241000047703 Nonion Species 0.000 description 1
- 102100029958 T-complex protein 1 subunit delta Human genes 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はＭＯ８半導体集積回路装置における微細なＭ
ＯＳ ）ランジスタのゲート電極パターンの形成方法の
改良に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention is directed to
OS) This invention relates to an improvement in a method for forming a gate electrode pattern of a transistor.
半導体集積回路装置（ＩＣ）は市場の要求によって近年
ますます高集積化が進み、回路パターンも１μｍからサ
ブミクロン領域へ指向している。これに伴って、ＭＯＳ
）ランジスタ（ＭＯ８Ｔ）のゲート電極パターンも微
細化が要求され、それに従って寸法精度も高精度なもの
が必要となってきている。Semiconductor integrated circuit devices (ICs) have become increasingly highly integrated in recent years due to market demands, and circuit patterns are moving from 1 μm to submicron regions. Along with this, MOS
) The gate electrode pattern of a transistor (MO8T) is also required to be miniaturized, and accordingly, high dimensional accuracy is also required.
第２図Ａ−Ｅは従来のゲート電極パターンの形成方法を
説明するために１その主要段階における状態を示す断面
図で、まず、基板（１）の上にゲート電極材料膜（２）
を形成する（第２図Ａ）。次に１その上に感光性レジス
ト膜（３）をスピンコードによって１μｍの厚さに塗布
する（第２図Ｂ）。つづいて、所望のゲート電極パター
ンに対応するパターンを有するホトマスクを介して感光
性レジスト膜（３）に所要の選択露光をし、現像処理を
施して所望のレジストパターン（３ａ）を得る（第２図
Ｃ）。次に１このレジストパターン（３ａ）′ｔ−マス
クとして四塩化炭素（ＣＣ１４）などのプラズマを用い
た反応性イオンエツチング（Ｒａａｃｔｌｖｅ Ｉｏｎ
Ｅｔｃｈｉｎｇ ＠ ＲＩＥ）によって、ゲート電極
材料膜（２）の露出部をエツチング除去しく第２図Ｄ）
、更に、残存したレジストパターｙ（３ａ）ｔ−酸素プ
ラズマなどで除去することによってゲート電極パターン
（２ａ）が完成する（Ｗ。2A to 2E are cross-sectional views showing the main stages of the conventional method for forming a gate electrode pattern. First, a gate electrode material film (2) is deposited on a substrate (1).
(Figure 2A). Next, a photosensitive resist film (3) is applied thereon to a thickness of 1 μm using a spin code (FIG. 2B). Subsequently, the photosensitive resist film (3) is selectively exposed to light through a photomask having a pattern corresponding to the desired gate electrode pattern, and developed to obtain the desired resist pattern (3a). Figure C). Next, this resist pattern (3a)' is subjected to reactive ion etching using plasma such as carbon tetrachloride (CC14) as a t-mask.
The exposed portion of the gate electrode material film (2) is removed by etching (Fig. 2D).
Then, the remaining resist pattern y(3a) is removed by oxygen plasma or the like to complete the gate electrode pattern (2a) (W).
２図Ｅ）。Figure 2 E).
従来の方法では以上のように、有機レジストパターン（
３＆）を１スクとしてゲート電属材料膜（２）をエツチ
ングしているが、有機レジストパターン（３ａ）もＲＩ
ＥＫよって多少エツチングを受けるという問題点がある
。すなわち、ｃ ｃｔ４プラズマのＲＩＥに対してゲー
ト電極材料膜とレジスト膜との被エツチング選択比は比
較的小さい。これはレジストパターンをマスクとしてゲ
ート電極材料ａｔ−エツチングしたとき、レジストは上
記選択比に応じた膜減りをすることを意味している。第
３図Ａ。In the conventional method, as described above, the organic resist pattern (
The gate metal material film (2) is etched using 3&) as one screen, but the organic resist pattern (3a) is also etched using RI.
There is a problem that it is etched to some extent by EK. That is, the etching selection ratio between the gate electrode material film and the resist film is relatively small in RIE using CCT4 plasma. This means that when the gate electrode material is etched using the resist pattern as a mask, the thickness of the resist is reduced in accordance with the above-mentioned selection ratio. Figure 3A.
Ｂはこの様子を示す拡大断面図で、レジストパターン（
３ａ）はある程度テーバをもっており（第３図Ａ）、従
って、ＲＩＥを施すと図に（３ｂ）で示すように、レジ
スト膜減シのため、バターｙ＃Ｈにも図示減少Ｗを生じ
、下地ゲート電極パターン（２ａ）のパターン幅の制御
性を悪くシ、シかも、レジストパターン（３ａ）のテー
バの場所的変化が下地ゲート電極パターン（２ａ）のパ
ターン幅のばらつきを生じ、特にサブミクロンのパター
ン幅ではこの影響は無視できなくなるという問題点があ
った。B is an enlarged cross-sectional view showing this state, and the resist pattern (
3a) has a certain degree of taber (Fig. 3A), therefore, when RIE is applied, as shown in Fig. 3b, due to the resist film reduction, butter y#H also undergoes an indicated reduction W, and the underlying The controllability of the pattern width of the gate electrode pattern (2a) may be poor, and the positional variation of the taber of the resist pattern (3a) may cause variations in the pattern width of the underlying gate electrode pattern (2a). There was a problem that this effect could no longer be ignored depending on the pattern width.
この発明は以上のような問題点を解消するためになされ
たもので、サブミクロンのゲート電極パターンでも制御
性よく形成することのできる方法を提供することを目的
とする。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method that can form even submicron gate electrode patterns with good controllability.
この発明に係るゲート電極パターンの形成方法では、ゲ
ート電極材料膜に所望のパターンに応じて所定のイオン
を注入しておき、その上で所定ガス雰囲気でのドライエ
ツチングを施すことによって、所望のゲート電極パター
ンを得るものである。In the method for forming a gate electrode pattern according to the present invention, a desired gate electrode pattern is formed by implanting predetermined ions into a gate electrode material film according to a desired pattern, and then performing dry etching in a predetermined gas atmosphere. This is used to obtain an electrode pattern.
この発明ではゲート電極材料膜に、所望のパターンに応
じて、ちる種のイオンを注入しておき、その上で所定ガ
ス雰囲気でのドライエツチングを施すことによって、上
記イオンを雰囲気ガスと反応させて不揮発性化合物を生
ぜしめ、これをマスクとしてイオノ非注入部分をエツチ
ング除去させる。従って、従来方法のようなレジストマ
スクに起因するパターンシフトの問題は排除される。In this invention, ions of various types are implanted into the gate electrode material film according to a desired pattern, and then dry etching is performed in a predetermined gas atmosphere to cause the ions to react with the atmospheric gas. A non-volatile compound is generated, and this is used as a mask to remove the non-ion implanted areas by etching. Therefore, the problem of pattern shift caused by the resist mask as in the conventional method is eliminated.
〔実施例〕
第１図Ａ −Ｃはこの発明の一実施例を説明するために
、その主要段階における状態を示す断面図 ゛で、まず
、基板（１）の上にポリシリコンからなるゲート１！極
材料膜（２）を形成する（稟１図Ａ）。次に、集束イオ
ンビーム（以下ＦＩＢといつ。）工によってゲートとな
るべき部分へ鉄（Ｆｅ）、銅（Ｃｕ）のようなイオンを
例えば５０ ｋｅＶの加速電圧で１０ｇＬ／ｃｍ２注入
してイオン注入［域（５）を形成しく第１図Ｂ）、その
後に、四塩化炭素＜ＣＣｔ４＞等の雰囲気でドライエツ
チング金施すと、注入されたＰ”ｅ、 Ｃｕはエツチン
グガスと反応してＦｅＣＺ２＋ ＣｕＣＺ２のような不
揮発性化合物を生成し、イオン注入領域（５）における
この生成物がマスクの役割を果して、イオン注入されて
いない部分のゲート電価材料膜（２）はエツチング除去
され、所望のゲート電極パターン（２ａ）が得られる（
＠１図Ｃ）。[Embodiment] FIGS. 1A to 1C are cross-sectional views showing the main stages of an embodiment of the present invention. First, a gate 1 made of polysilicon is placed on a substrate (1). ! A polar material film (2) is formed (Figure 1A). Next, ions such as iron (Fe) or copper (Cu) are injected at 10 gL/cm2 into the part that will become the gate using a focused ion beam (hereinafter referred to as FIB) at an acceleration voltage of 50 keV. [To form region (5) (Fig. 1B), dry etching is then performed in an atmosphere of carbon tetrachloride <CCt4>, etc., and the implanted P"e and Cu react with the etching gas to form FeCZ2+ CuCZ2. This product in the ion-implanted region (5) acts as a mask, and the gate voltage material film (2) in the non-ion-implanted area is etched away to form the desired gate. Electrode pattern (2a) is obtained (
@1 Figure C).
この方法におけるエツチングマスクの役割を果すイオン
注入領域（５）の耐ドライエツチング性が極めてよく、
従来方法におけるレジストマスクのような膜減りが殆ん
どないことと、イオンのゲート１極材料膜（２）中での
横方向の広がシが殆んどないこととによって、ゲート電
極パターン（２ａ）は極めて精度よく形成でき、設計寸
法からのずれは、わずか０．１μｍであった。The ion implantation region (5), which plays the role of an etching mask in this method, has extremely good dry etching resistance.
The gate electrode pattern ( 2a) could be formed with extremely high precision, and the deviation from the design dimension was only 0.1 μm.
上記実施例ではゲート電極材料にポリシリコンを用いた
が、それ以外の材料、例えば、モリブデンもしくはタン
グステンまたはそりブデン、タングステンもしくはチタ
ンのクリサイドを用いても木質的差異はない。Although polysilicon was used as the gate electrode material in the above embodiment, there is no difference in wood quality even if other materials such as molybdenum, tungsten, tribdenum, tungsten, or titanium crystal are used.
以上説明したように、この発明では、ゲート電極材料膜
にＦＩＢＫよって直接所定のイオンを所望パターンに注
入しておき、その上で所定ガス雰囲気でのドライエツチ
ングを施すこと罠よって、上記イオンをその雰囲気ガス
と反応させて不揮発性化合物を生ぜしめ、これをマスク
として上記ゲート電極材料膜のイオン非注入部分をエツ
チング除去するので、ホトマスクの転写工程を必要とし
ないのは勿論、エツチングマスクが極めてＭ度よく形成
でき、しかも耐ドライエツチング性にすぐれているので
正確なゲート電極パターンが得られる。As explained above, in the present invention, predetermined ions are directly implanted into the gate electrode material film in a desired pattern using FIBK, and then dry etching is performed in a predetermined gas atmosphere. A non-volatile compound is generated by reacting with atmospheric gas, and this is used as a mask to remove the non-ion-implanted portions of the gate electrode material film by etching.Therefore, there is no need for a photomask transfer process, and the etching mask is extremely thin. Since it can be formed easily and has excellent dry etching resistance, an accurate gate electrode pattern can be obtained.
第１図Ａ−Ｃはこの発明の一実施例を説明するためＫそ
の主要段階における状ａ′ｆ−示す断面図、第２図Ａ〜
Ｅは従来のゲート電極パターンの形成方法を説明するた
めにその主要段階における状態を示す断面図、第３図Ａ
、Ｂはこの従来方法の欠点の発生状況を示す拡大断面図
である。
図において、（ｌ）は基板、（２Ｊはゲート電極材料膜
、（２ａ）はゲート電極パターン、（５）はイオン注入
領域、工は集束イオンビームである。
なお、各図中同一符号は同一または相当部分を示す。1A to 1C are cross-sectional views showing an embodiment of the present invention at its main stages, and FIGS.
E is a cross-sectional view showing the state at the main stages to explain the conventional method of forming a gate electrode pattern; FIG. 3A
, B are enlarged cross-sectional views showing the occurrence of defects in this conventional method. In the figure, (l) is the substrate, (2J is the gate electrode material film, (2a) is the gate electrode pattern, (5) is the ion implantation region, and is the focused ion beam. Note that the same symbols in each figure are the same. or a significant portion.
Claims (7)
オンを集束イオンビームによつて所望パターンに注入し
、その後に所定ガス雰囲気でのドライエッチングを施し
、上記注入イオンを上記雰囲気ガスと反応させて不揮発
性化合物を生ぜしめ、上記所望パターンのイオン注入領
域に生じた上記不揮発性化合物の層をマスクとして、上
記ゲート電極材料膜のイオン非注入部分をエッチング除
去することを特徴とするゲート電極パターンの形成方法
。(1) Predetermined ions are implanted into the gate electrode material film formed on the substrate in a desired pattern using a focused ion beam, and then dry etching is performed in a predetermined gas atmosphere, and the implanted ions are mixed with the above atmospheric gas. A gate characterized in that a non-volatile compound is produced by a reaction, and a non-ion-implanted portion of the gate electrode material film is etched away using the layer of the non-volatile compound produced in the ion-implanted region of the desired pattern as a mask. How to form an electrode pattern.
気ガスに四塩化炭素を用いることを特徴とする特許請求
の範囲第１項記載のゲート電極パターンの形成方法。(2) The method for forming a gate electrode pattern according to claim 1, characterized in that iron ions are used as ions and carbon tetrachloride is used as a dry etching atmosphere gas.
気ガスに四塩化炭素を用いることを特徴とする特許請求
の範囲第１項記載のゲート電極パターンの形成方法。(3) The method for forming a gate electrode pattern according to claim 1, characterized in that copper ions are used as the ions and carbon tetrachloride is used as the dry etching atmosphere gas.
徴とする特許請求の範囲第１項ないし第３項のいずれか
に記載のゲート電極パターンの形成方法。(4) The method for forming a gate electrode pattern according to any one of claims 1 to 3, characterized in that polysilicon is used as the gate electrode material.
徴とする特許請求の範囲第１項ないし第３項のいずれか
に記載のゲート電極パターンの形成方法。(5) The method for forming a gate electrode pattern according to any one of claims 1 to 3, characterized in that tungsten is used as the gate electrode material.
とする特許請求の範囲第１項ないし第３項のいずれかに
記載のゲート電極パターンの形成方法。(6) The method for forming a gate electrode pattern according to any one of claims 1 to 3, characterized in that molybdenum is used as the gate electrode material.
リブデン・シリサイドおよびチタン・シリサイドなる１
群の物質中から任意に選んだ１員を用いることを特徴と
する特許請求の範囲第１項ないし第３項のいずれかに記
載のゲート電極パターンの形成方法。(7) Tungsten silicide, molybdenum silicide, and titanium silicide are used as gate electrode materials.
4. The method of forming a gate electrode pattern according to claim 1, wherein a member arbitrarily selected from a group of materials is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP311185A JPS61161717A (en) | 1985-01-10 | 1985-01-10 | Formation of gate electrode pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP311185A JPS61161717A (en) | 1985-01-10 | 1985-01-10 | Formation of gate electrode pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61161717A true JPS61161717A (en) | 1986-07-22 |
Family
ID=11548238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP311185A Pending JPS61161717A (en) | 1985-01-10 | 1985-01-10 | Formation of gate electrode pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61161717A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03173782A (en) * | 1989-11-30 | 1991-07-29 | Eagle Ind Co Ltd | Method for working material body |
| JP2008311617A (en) * | 2007-05-15 | 2008-12-25 | Canon Inc | Nano structure, and manufacturing method of nano structure |
-
1985
- 1985-01-10 JP JP311185A patent/JPS61161717A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03173782A (en) * | 1989-11-30 | 1991-07-29 | Eagle Ind Co Ltd | Method for working material body |
| JP2008311617A (en) * | 2007-05-15 | 2008-12-25 | Canon Inc | Nano structure, and manufacturing method of nano structure |
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