JPS61161609U - - Google Patents
Info
- Publication number
- JPS61161609U JPS61161609U JP4322885U JP4322885U JPS61161609U JP S61161609 U JPS61161609 U JP S61161609U JP 4322885 U JP4322885 U JP 4322885U JP 4322885 U JP4322885 U JP 4322885U JP S61161609 U JPS61161609 U JP S61161609U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- binary
- circuit
- memory
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003909 pattern recognition Methods 0.000 claims description 4
- 238000003384 imaging method Methods 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Length Measuring Devices By Optical Means (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Image Processing (AREA)
- Closed-Circuit Television Systems (AREA)
Description
第２図は従来のパターン認識装置の一例を示す
構成図、第１図は本考案によるパターン認識装置
の一実施例を示す構成図、第３図は本考案の主要
部である除去回路の構成図。５…演算回路、６…
２値化回路、７…同期信号発生器、１０…除去回
路、１０ａ…クロツク発生器、１０ｂ…メモリ、
１０ｃ…第１の論理回路、１０ｄ…シフトレジス
タ、１０ｅ…第２の論理回路。
Fig. 2 is a block diagram showing an example of a conventional pattern recognition device, Fig. 1 is a block diagram showing an embodiment of the pattern recognition device according to the present invention, and Fig. 3 is the configuration of a removal circuit which is the main part of the present invention. figure. 5... Arithmetic circuit, 6...
Binarization circuit, 7... Synchronization signal generator, 10... Removal circuit, 10a... Clock generator, 10b... Memory,
10c...first logic circuit, 10d...shift register, 10e...second logic circuit.
Claims (1)
処理し、得られる２値化信号を入力信号として認
識処理するパターン認識装置において該撮像装置
に同期して該２値化信号を記憶するメモリのアド
レス信号を発生するクロツク発生器と、該２値化
信号の垂直方向の信号を記憶するメモリと該メモ
リから出力される２値化信号と該２値化回路で２
値化処理された２値化信号とを論理処理する第１
の論理回路と該２値化信号を入力としかつ該クロ
ツク発生器のクロツク信号をクロツクとして動作
するシフトレジスタと、該シフトレジスタの出力
信号を論理処理する第２の論理回路で構成し該２
値化回路から出力される信号の垂直および水平信
号成分を所定の信号時間だけ除去する除去回路を
備付けたことを特徴とするパターン認識装置。 A memory for storing the binarized signal in synchronization with the imaging device in a pattern recognition device that performs binarization processing in a binarization circuit using video information of the imaging device and recognizes and processes the obtained binarized signal as an input signal. A clock generator that generates an address signal, a memory that stores a vertical signal of the binary signal, a binary signal output from the memory, and a binary signal outputted from the binary circuit.
A first step that performs logical processing on the binarized signal that has been digitized.
a shift register that receives the binary signal as an input and operates using the clock signal of the clock generator as a clock; and a second logic circuit that logically processes the output signal of the shift register.
A pattern recognition device comprising a removal circuit that removes vertical and horizontal signal components of a signal output from a value conversion circuit for a predetermined signal time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4322885U JPS61161609U (en) | 1985-03-27 | 1985-03-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4322885U JPS61161609U (en) | 1985-03-27 | 1985-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61161609U true JPS61161609U (en) | 1986-10-07 |
Family
ID=30554705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4322885U Pending JPS61161609U (en) | 1985-03-27 | 1985-03-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61161609U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990009004A1 (en) * | 1989-01-31 | 1990-08-09 | Yoshiro Yamada | Image processing method and apparatus |
| JP2006078381A (en) * | 2004-09-10 | 2006-03-23 | Keyence Corp | Display method of display of image processing apparatus |
-
1985
- 1985-03-27 JP JP4322885U patent/JPS61161609U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990009004A1 (en) * | 1989-01-31 | 1990-08-09 | Yoshiro Yamada | Image processing method and apparatus |
| JP2006078381A (en) * | 2004-09-10 | 2006-03-23 | Keyence Corp | Display method of display of image processing apparatus |
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