JPS6116101B2 - - Google Patents
Info
- Publication number
- JPS6116101B2 JPS6116101B2 JP55090375A JP9037580A JPS6116101B2 JP S6116101 B2 JPS6116101 B2 JP S6116101B2 JP 55090375 A JP55090375 A JP 55090375A JP 9037580 A JP9037580 A JP 9037580A JP S6116101 B2 JPS6116101 B2 JP S6116101B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memory access
- signal
- central processing
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Stand-By Power Supply Arrangements (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9037580A JPS5715299A (en) | 1980-07-02 | 1980-07-02 | Memory access control system of doubled memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9037580A JPS5715299A (en) | 1980-07-02 | 1980-07-02 | Memory access control system of doubled memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5715299A JPS5715299A (en) | 1982-01-26 |
JPS6116101B2 true JPS6116101B2 (enrdf_load_stackoverflow) | 1986-04-28 |
Family
ID=13996814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9037580A Granted JPS5715299A (en) | 1980-07-02 | 1980-07-02 | Memory access control system of doubled memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5715299A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5487927A (en) * | 1992-01-24 | 1996-01-30 | Revlon Consumer Products Corporation | Decorating method and products |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB100768A (en) * | 1916-04-03 | 1916-07-06 | John Maxfield | Improvements in and relating to Tuning Pins for Pianos. |
JPS4912626U (enrdf_load_stackoverflow) * | 1972-05-10 | 1974-02-02 | ||
DE2432956C3 (de) * | 1974-07-09 | 1979-07-19 | Heinz-Dieter Dipl.-Ing. 1000 Berlin Adomeit | Gurtaufwickelklemmautomat |
-
1980
- 1980-07-02 JP JP9037580A patent/JPS5715299A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5715299A (en) | 1982-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5345566A (en) | Method and apparatus for controlling dual bus system | |
EP0077153B1 (en) | Digital data processor with fault-tolerant bus protocol | |
US4358823A (en) | Double redundant processor | |
US4453215A (en) | Central processing apparatus for fault-tolerant computing | |
US4597084A (en) | Computer memory apparatus | |
US7681073B2 (en) | Arbitration system for redundant controllers, with output interlock and automatic switching capabilities | |
US5005174A (en) | Dual zone, fault tolerant computer system with error checking in I/O writes | |
US4907228A (en) | Dual-rail processor with error checking at single rail interfaces | |
EP0186006B1 (en) | Multiprocessor system | |
US4916704A (en) | Interface of non-fault tolerant components to fault tolerant system | |
US6687851B1 (en) | Method and system for upgrading fault-tolerant systems | |
EP0306244B1 (en) | Fault tolerant computer system with fault isolation | |
US5491787A (en) | Fault tolerant digital computer system having two processors which periodically alternate as master and slave | |
US4747041A (en) | Automatic power control system which automatically activates and deactivates power to selected peripheral devices based upon system requirement | |
US5068780A (en) | Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones | |
EP0116344B1 (en) | Power backed-up dual memory system | |
US5163138A (en) | Protocol for read write transfers via switching logic by transmitting and retransmitting an address | |
US5634037A (en) | Multiprocessor system having a shared memory with exclusive access for a requesting processor which is maintained until normal completion of a process and for retrying the process when not normally completed | |
US20040073836A1 (en) | Predecessor and successor type multiplex system | |
JPS6116101B2 (enrdf_load_stackoverflow) | ||
JP3415636B2 (ja) | プロセッサ装置 | |
JPH11212904A (ja) | データ転送システム | |
JPH07114521A (ja) | マルチマイクロコンピュータシステム | |
JPH0822441A (ja) | 情報処理装置およびその通信エラー検出方法 | |
WO2001080010A2 (en) | Method and system for upgrading fault-tolerant systems |