JPS6116101B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control method for a duplex memory, and in particular, to a memory access control method for a duplex memory, and in particular, to a memory access control system for a duplex memory, and in particular to a memory access control method for controlling data access control, which includes a plurality of central processing units and a duplex memory device commonly accessed by the plurality of central processing units. In a processing system, processing normally proceeds while synchronizing the central processing units that have received memory access requests in the memory devices of both systems, and in the event of a power failure in one system, only the other normal system operates. This invention relates to a memory access control method that guarantees operation when power is turned on/off and when a power failure occurs.

In multiprocessor systems with multiple central processing units (CPUs), memory may be duplicated to improve system reliability. In such cases, when one memory fails and the other memory is switched to. Generally, the switching operation is performed by interrupting access from the central processing unit. However, in a data processing system operated as an online system, interruption of access is not desirable, and it is necessary to be able to power on and off one of the dual systems even during access from the central processing unit. It is said that Furthermore, since power failures also occur asynchronously with access, the memory system must be able to operate with one lung even if the power is cut off due to a failure.

The present invention guarantees the continuity of processing in a memory system by making it possible to turn on and off power to one system without stopping access from the central processing unit to the duplex common memory. It is an object of the present invention to improve the maintainability and possibility of the system, and for this purpose, the present invention provides a data processing system that includes a plurality of central processing units and a duplex memory device that is commonly accessed by the plurality of central processing units. In the processing system, each of the memory devices includes a circuit that sends a power abnormality signal to other memory devices indicating that the power supply of the own system is disconnected or abnormal, and a memory access request that selects memory access requests from the plurality of central processing units. A selection circuit and the memory access request selection circuit send the identification information of the central processing unit selected by the memory access request selection circuit to the other system, and the identification information of the central processing unit of the own system and the other system and the power abnormality signal from the other system. It is equipped with a memory access selection synchronization control circuit that controls memory access to the own system's memory, and the above-mentioned central processing from the other system is performed when there is an abnormality in the power supply of the other system and for a predetermined period after the power supply of the other system is brought into a normal state. The present invention is characterized in that memory access can be performed regardless of device identification information, and after the predetermined period has elapsed, memory access is performed based on the central processing unit identification information of both systems.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a data processing system according to an embodiment to which the present invention is applied. In the figure, 1 to 4 are central processing units (CPUs), 5 and 6 are memory controllers, and 7 and 8 are memories. - Arrays 9 and 10 are power supply units. In FIG. 1, a memory controller 5, a memory array 7, and a power supply unit 9 constitute one memory device A system, and a memory controller 6, a memory array 8, a power supply unit 10
constitutes the other memory device B system. Also,
The memory controllers 5 and 6 include contention control units 11 and 12 that control reception of access requests from multiple central processing units, registers that hold memory status and error information, etc., a data check circuit, and a protection function unit. Circuit section 1 having etc.
3 and 14, memory control units 17 and 18 that control access to the memory array, and synchronization control units 15 and 16 that perform synchronization control between both systems. The present invention provides memory controllers 5, 6
It is characterized by its configuration, and its operation will be explained below. FIG. 2 is a connection diagram of power supply status signals, in which 5, 6, 9, and 10 are the same as in FIG. 1, 20 and 21 are delay circuits, 22 and 23 are flip-flops, and 24 to 27 are AND circuit, 2
8 and 29 are NAND circuits, 30 to 33 are inverters, CUT signal is the first notice signal from the power supply unit, INH is the second notice signal, PWFX is a signal indicating an abnormality in the power supply of the own system, and PWFY indicates an error in the power supply of another system. signal,
CK is a clock signal, and A is a signal indicating that the memory controller is not in sequence (processing a CPU service request). Figure 3 is a time chart of power on/off. First, +5V of A system is turned on, and +5V from power supply unit 9
When the CUT signal indicating the guarantee of 5V is sent to the memory controller 5, the memory controller 5 starts operating as a common memory. After that, B
The system is powered on, but power supply unit 1
After +5V is guaranteed by the CUT signal from 0, it starts operating as a common memory, and as described later, after the selection synchronization operations of both systems are matched,
The duplex memory enters synchronous operation.

On the other hand, when the power is cut off, for example, when the A system power is cut off, the first
A warning signal (CUT signal) “off” is sent to the memory controller 5. In addition, even in the event of a power failure, the alarm detection circuit (not shown)
CUT signal “off” is sent. The memory controller 5 generates a second notice signal (INM signal) "OFF" which is a delayed version of the CUT signal "OFF".
This delay time is within the output hold-up time of the power supply unit. Then, the memory controller 5 completes all sequences within the delay time, receives the CUT signal "off", normally completes the sequence being executed, and then receives the INH signal "off". Therefore, noise is prevented from being generated on the interface by suppressing the input to the central processing unit and the interface driver circuit (for example, the driver circuit consisting of NAND circuits 28 and 29) with other systems. In other words, when the power supply drops from 5V to 0V due to an abnormality in the power supply unit 9 or 10, the NAND circuit (driver circuit) 28 or 29 generates noise to prevent the signal PWFX of the normal memory controller from turning on. Driver circuit) 28 or 29
*INF signal is input to. Thereafter, the mode is switched to a mode that allows single-lung operation using only the B system. As mentioned above, the power abnormality warning signal (CUT) is delayed by a delay circuit for a certain period of time and becomes the INHX signal, but this is to ensure that the sequence that is currently operating at the time a power abnormality occurs is normally terminated. After completion, it is necessary to cause the other system to have a power failure and disconnect the system with the power failure. Therefore, the memory controller
After receiving the CUT signal, if the sequence is not in progress or the sequence at that point has ended,
The CUT signal is set in the flip-flop by the clock signal, and PWFY (other system power failure) is detected.

Next, FIG. 4 is a block diagram showing the connection relationship of the memory access selection synchronization control circuit in the memory controller, and in the figure, 5 and 6 are the first
40 and 41 are the same as in FIG.
An access selection synchronization control circuit, 42 and 43 are rise detection circuits that detect the rise of a service request from the central processing unit, 44 and 45 are buffers that hold detected service request signals, and 46 and 47 are buffers that hold requests (REQ) from the buffers. ) signal and sends identification information of the selected central processing unit (CPC0.1 signal) and a signal indicating that a service request has been detected (HIT signal) to memory access selection synchronization control circuits 40 and 41 , 48 and 49 are read/write control circuits that control access to the memory array in response to START signals from the memory access selection synchronization control circuits 40 and 41. Memory access selection synchronization control circuit 4
0 and 41 exchange signals with each other, and when the other system is powered on while only one system is operating,
Synchronous operation is started after matching the access request source selections of both systems.

Buffers 44 and 45 have CPU0 to CPU
The REQ signal for the service request corresponding to CPU 3 is set, but depending on the access timing of CPU0 to CPU3, up to four REQ signals are turned on at the same time.

The CPU selection circuits 46 and 47 select the REQ signal with the highest priority from among the four turned-on REQ signals at most, according to the priorities (not shown) instructed by the memory access selection synchronization control circuits 40 and 41. Selected and selected REQ
The CUT number corresponding to the signal is displayed in 2 bits of the CPU0 and 1 signals, and the HIT signal indicating that a service request has been received is turned on.

When only one REQ signal is set in the buffers 44 and 45, the CPU number corresponding to that REQ signal is displayed on the CPC0 and 1 signals and the HIT signal is turned on, regardless of the priority.

FIG. 5 is a block diagram of the memory access selection synchronization control circuits 40 and 41, in which 50 is a comparison circuit, 51 and 52 are quaternary counters A, respectively.
B, 53 is a NOR circuit, 54 and 55 are AND circuits,
56 and 57 are OR circuits, HITX, Y and
CPC0.1X, Y are the same as in Figure 4,
is the signal from the own system, Y is the signal from the other system, START is the 4th signal
The signal is the same as in the figure and indicates the start of memory access. CLOCK is the clock signal. PWFX is the same as in Fig. 2 and is the signal indicating a self-system power supply abnormality. PWFY is the same as in Fig. 2. *CUAV is a signal indicating that one service request has been completed. The operation of FIG. 5 is as follows. In case of power failure in other system,
Since PWFY is "1", the output of the OR circuit 56 becomes "1", and therefore, the START signal is generated only by the own system HIT signal (HITX), and memory access is performed. Next, since the service requests of the own system and the other system may not match immediately after the power of the other system is turned on, the memory access is performed after waiting for a certain period of time. That is, when the HITX signal is turned on, the output of the AND circuit 54 becomes "1", and the quaternary counter B52 continues to increment the clock until a match is found in the comparison circuit 50, and carries out a carry after four clocks. Generate a signal. Then, the carry signal causes the output of the OR circuit 56 to become "1", and the START signal is generated using only the own system HIT signal (HITX), and memory access is performed. Of course, if the access request source code information of both systems match in the comparator circuit 50 before the quaternary counter B52 generates a carry, the OR circuit 57 immediately generates a START signal based on the output of the comparator circuit 50. Ru.

On the other hand, when the power supply of another system is abnormal, PWFY is "1", so the output of the OR circuit 53 remains "0".
The other quaternary counter A51 is in a stopped state. Then, since PWFY becomes "0" after the other system power is turned on, the OR circuit 53 outputs "1" every time the *CUAV signal (service request end signal) is generated, and each time, the OR circuit 53 outputs "1" Count up A51. In this way, when the processing for the fourth service request is completed, the quaternary counter A51 issues a carry signal, sets the output of the OR gate 53 to "0", and the subsequent quaternary counter A
51 count up operation is stopped. At the same time, since the output of the AND circuit 54 is set to "0", the quaternary counter B52 is also stopped from now on. Therefore, after the other system is powered on, the OR circuit 57 will not generate a START signal for the fifth or subsequent service request unless the access request source codes of both systems match in the comparison circuit 50.

To further explain, since the rising edge detection circuits 42 and 43 perform rising edge detection by clock synchronization, depending on the timing of service requests from CPUs 0 to 3, the REQ signal may be set in the buffer 44 of the A-system memory controller. However, the buffer of B series memory controller is 45.
may be set on the next clock. Also, when multiple CPUs issue service requests at the same time, the buffer 44,
45 may be set with REQ signals corresponding to different CPUs. In this case, it goes without saying that the next clock will match the clock. Like this A
In order to synchronize and service the same CPU in system B, memory access selection synchronization control circuits 40 and 41 exchange HIT, CPC0, and 1 signals with each other, and HITX, CPC0, and
The comparison circuit 50 compares the 1X signal with the HITY, CPC0, and 1Y signals of other systems, and if they match, turns on the START signal and instructs to access the memory. If they do not match, they will match after one clock as described above, so the START signal is then turned on.

If there is a power failure in the other system, the comparison circuit 50 cannot find a match, but the OR circuit 56 is turned on by the power failure signal PWFY of the other system, so if the access request signal HITX of the own system is turned on, the AND circuit 55 is turned on. Then, the START signal turns on and memory access is performed.

After powering on the other system, the other system power error signal PWFY
Since the comparison circuit 50 is off, memory access is started when a match is found in the comparison circuit 50. However, immediately after turning on the power of another system, the buffer 44 or 45 of the own system is
All REQ signals corresponding to CPU0 to CPU3 may be set, but not all REQ signals may be set to the buffers of the system immediately after power is turned on. Normally, during duplex operation, the comparator circuit 50 will find a match after one clock, but in this case no match will be found no matter how many clocks you wait. The number of unmatched service requests immediately after power is turned on for other systems is equal to the number of CPUs at most, and is four times in the example of FIG. 4.

For this reason, even if the comparison circuit 50 cannot find a match for the four service requests immediately after power is turned on in other systems, accesses are accepted only in the own system.

That is, the quaternary counter A51 is stopped from incrementing by the PWFY signal when there is an abnormality in the power supply of another system, and the counter value is set to "0".

Immediately after the power of the other system is turned on, the PWFY signal is turned off, so the NOR circuit 53 is turned off by the service request end signal *CUAV, and the counter A51 increments. When this *CUAV signal turns on four times, counter A5
1 increments from "0" to "4" and outputs a carry signal. As a result, the NOR circuit 53 is turned on and its own increment is prohibited, and the AND circuit 54 is turned off and the increment of the counter B52 is also prohibited.

Therefore, the AND circuit 54 does not operate on the own system until the four service requests are processed immediately after the other system's power is turned on.
By turning on the HITX signal and incrementing the counter B52 under the condition that the comparison circuit 50 cannot find a match, the counter B52 outputs a carry signal after 4 clocks even when the comparison circuit 50 cannot find a match. , generates a START signal and processes the service request.

In this way, the memory access selection synchronization control circuit shown in Figure 5: (1) When only the own system is powered on normally,
Immediately due to a memory access request from the own system.
(2) Immediately after the other system is powered on, the comparison circuit 5
If a match cannot be obtained by comparison with 0, a START signal is generated based on the memory access request signal of the own system. (4) After the other system's power is turned on, the comparator circuit 50 can compare and match the fifth and subsequent service requests. The START signal is not emitted unless it is.

Fig. 6 is a diagram showing the relationship between Fig. 1, Fig. 2, and Fig. 4, and in the figure, the same numbers as in Fig. 1, Fig. 2, and Fig. 4 represent the same thing. There is.

Further, 60 in FIG. 6 indicates a part including numbers 20, 22, 24, 26, and 28 in FIG.
3, 25, 27, and 29 are shown.

As explained above, according to the present invention, the duplex memory devices exchange power supply abnormality signals with each other, and when the power supply of the other system is abnormal and for a predetermined period after the power supply of the other system is brought into a normal state, Memory access can be performed regardless of the memory access request source information from the system, and after a predetermined period of time, memory access is performed only when the memory access request source information of both systems matches. It is possible to power on and off one system without stopping access from the central processing unit to the device, and the continuity of memory system processing is not lost due to power failure, improving system maintainability and availability. can be increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a data processing system according to an embodiment to which the present invention is applied, Fig. 2 is a connection diagram of power state signals, Fig. 3 is a time chart of power on/off, and Fig. 4 is a memory controller. FIG. 5 is a block diagram showing the connection relationship of the memory access selection synchronization control circuit in the memory access selection synchronization control circuit, and FIG. 6 shows the relationship between FIGS. FIG. In the figure,
1 to 4 are central processing units, 5 and 6 are memory controllers, 7 and 8 are memory arrays, 9 and 10 are power supply units, 40 and 41 are memory access selection synchronization control circuits, and PWFX is a self-system power supply abnormality detection circuit. PWFY is a signal indicating an abnormality in the power supply of another system, START
is a signal instructing the start of memory access.

Claims (1)

[Claims] 1. In a data processing system comprising a plurality of central processing units and a duplicated memory device that is commonly accessed by the plurality of central processing units,
a circuit that sends a power abnormality signal to each of the memory devices indicating disconnection or abnormality of the power supply of the own system to the other memory devices; and a memory access request selection circuit that selects memory access requests from the plurality of central processing units; The identification information of the central processing unit selected by the memory access request selection circuit is sent to the other system, and the identification information of the central processing unit selected by the memory access request selection circuit is sent to the other system. Equipped with a memory access selection synchronization control circuit that controls memory access to the memory, the central processing unit identification information from the other system is used when the other system's power supply is abnormal and for a predetermined period after the other system's power supply is brought into a normal state. A memory access control method for a dual memory, characterized in that memory access can be performed regardless of the above, and after the elapse of the predetermined period, memory access is performed based on the central processing unit identification information of both systems.