JPS61161012A - Ccd shift register - Google Patents

Abstract

PURPOSE:To attain high circuit integration and to quicken the operating speed with less parasitic capacitance of each gate by providing a transfer gate above/ under a semiconductor thin film. CONSTITUTION:Transfer gates 11, 12 are provided on/under the semiconductor thin film 14. An electric charge is stored under phi1, phi2 gates at t=t1. Then an electric charge is transferred from the phi2 gate to a phi3 gate at t=t2. Since a channel stop region 17, however, exists between the phi1 and phi3 gates, the electric charge of the phi1 gate is not transferred directly to the phi3 gate. The electric charge of the phi1 gate is transferred to the phi2 gate by zeroing the applied voltage of the phi1 gate at t=t3. The signal electric charge is transferred by repeating the operation above. Thus, the circuit integration is increased. Since the parasitic capacitance of each gate is less, the operating speed is quickened.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a CCD shift register.

(Conventional configuration and its problems) Conventionally, CCD (Charge Couple D
(evice) shift registers have been given great importance. A conventional CCD shift register will be described below with reference to one drawing.

FIG. 1 shows a schematic cross-sectional view of a conventional CCD shift register. 1 is a Si substrate, and 2 is a transfer gate.

In the CCD shift register configured as above, by applying an appropriate pulse voltage to each transfer gate,
Signal charges can be transferred.

However, the above configuration has the disadvantage that when the CCD shift register is miniaturized, the amount of charge handled per one bit is reduced. Also,
There is a desire to make the CCD shift register more compact.

Furthermore, there is a demand for high-speed operation, and for this purpose it is necessary to reduce the capacitance of the transfer gate.

However, it has been difficult to meet these demands with conventional configurations.

(Object of the Invention) In view of the above-mentioned drawbacks, the present invention provides a CCD shift register that can have a high degree of integration and a high operating speed.

(Structure of the Invention) To achieve this object, the CCD shift register of the present invention includes transfer means having transfer gates above and below a thin film semiconductor.

(Description of Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a sectional view of the CCD shift register in the first embodiment of the present invention. In FIG. 2, 10 is a substrate;
11 is an upper transfer gate made of polysilicon or the like; 12 is a lower transfer gate made of polysilicon or the like; 13, 15 .
16 is an insulator, 14 is a semiconductor thin film, and 17 is a channel stop region. For the semiconductor thin film 16, polysilicon or single crystal silicon obtained by recrystallizing polysilicon by laser annealing is used.

The operation of the CCD shift register configured as described above will be explained below.

Various drive pulses for the transfer means can be considered, examples of which are shown in FIG. Based on the drive pulse shown in FIG.
The operation of charge transfer will be explained with reference to the schematic diagram in the figure.

In FIG. 4(a) (t=1:□), φ1. Charge is accumulated under the φ2 gate.

In FIG. 4(b) (t = tz), by applying a voltage to the gate φ, charge is transferred from the φ2 gate to the φ3 gate. However, since there is a channel stop region between the φ1 and φ3 gates, the charges on the φ and gates are not directly transferred to the φ□ gate.

In FIG. 4C (t=ti), by setting the voltage applied to the φ1 gate to O, the charge on the φ□ gate is transferred to the φ2 gate.

By repeating the above operations, signal charges can be transferred.

As described above, according to this embodiment, by providing the transfer gates above and below the semiconductor thin film, the degree of integration of the CCD shift register is increased, and the parasitic capacitance of each gate is reduced, so high-speed operation is possible. .

In this embodiment, a four-layer CCD shift register is used, but a three-layer CCD shift register may be used.

(Effects of the Invention) As described above, by providing the transfer gates above and below the semiconductor thin film, the CCD shift register of the present invention has a higher degree of integration and can increase the operating speed, and its practical effects are as follows. There is something big.

[Brief explanation of drawings]

1WI is a schematic sectional view of a conventional CCD shift register, FIG. 2 is a sectional view of a CCD shift register in an embodiment of the present invention, FIG. 3 is a pulse timing diagram of a transfer means in one embodiment, and FIG. FIG. 2 is a schematic diagram for explaining charge transfer. 10...Substrate, 11.12...Transfer gate, 13,
15°16...Insulator, 14...Semiconductor thin film, 17
...Channel stop area. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 Figure 3 t+ 1213

Claims (3)

[Claims] (1) An insulating substrate, a plurality of first transfer gates formed on the insulating substrate, a semiconductor thin film formed on the insulating substrate and the first transfer gate, and a plurality of first transfer gates formed on the semiconductor thin film. A CCD shift register comprising a second transfer gate. (2) A CCD shift register according to claim (1), wherein the semiconductor thin film is polysilicon. (3) The CCD shift register according to claim (1), wherein the semiconductor thin film is silicon obtained by recrystallizing polysilicon by laser annealing.