JPS61160134A - Exponent underflow detecting circuit - Google Patents

Abstract

PURPOSE:To detect an exponent underflow rapidly and to report an interruption quickly by forecasting plural carries to be generated in an exponent part. CONSTITUTION:The mantissa part of an operation result is applied to a line 10 and its exponent part is applied to a line 11. A subtracted value detected by a subtracted value detecting circuit 12 and the exponent part of the line 11 are applied to an exponent subtracting circuit 14 and a value indicated by the subtracted number is subtracted from the exponent part, so that the compensated exponent part is outputted to a line 16. Plural exponent subtracted result forecasting circuits 13 are formed to forecast and output plural subtracted results corresponding to respective cases of the subtracted numbers to be generated from the applied exponent part. An exponent underflow generating circuit 15 inputs the subtracted value detected by the circuit 12 and respective forecasting values of the circuits 13, selects a forecasting value corresponding to the subtracted value, and when the selected value does not indicate a carry meaning the success of subtraction, outputs an exponent underflow signal to a line 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device, and more particularly to an exponent underflow detection circuit for floating point arithmetic.

[Background of the invention]

In data processing devices, one of the factors for determining a branch instruction is to refer to a condition code based on the result of a floating-point operation, and to determine whether the branch is successful or unsuccessful based on the state of the condition code. Generally, when the code detects an exponent underflow in a floating-point operation, it is forced to take the state II OIt or 1''. Therefore, in order to quickly determine a branch instruction, the floating-point operation must be executed when an exponent underflow occurs. Conditions need to be detected as early as possible.

Conventionally, there is a method disclosed in Japanese Patent Application No. 54-43918 as a method for quickly detecting exponent underflow in floating point arithmetic. This is 2.0 for each position in the index. Underflow is detected by finding a combination of zero bits that causes an underflow, and then calculating the logical product of this and the output of the exponent decoder. The problem with this conventional method is that exponent underflow can be detected quickly when there are fewer consecutive zero digits than the upper part of the mantissa, but when the number of zero digits increases.

The number of required gate stages increases, and the effect of high-speed detection is significantly reduced. In order to avoid this, if you try to speed up only when the number of zero digits is small, you can proceed with execution of the instruction assuming that an exponential underflow interrupt will not occur, and if an interrupt occurs later, To deal with this, the problem arises that the execution control logic becomes complicated.

[Purpose of the invention]

The purpose of the present invention is to detect exponential underflow at high speed,
An object of the present invention is to provide an exponential underflow detection circuit that can report interrupts early.

[Summary of the invention]

Exponent underflow in floating point arithmetic.

Detected when the number of consecutive zero digits from the high-order part of the mantissa is subtracted from the exponent and there is no carry indicating a successful subtraction. The present invention detects exponent underflow at high speed by predicting multiple carries that may occur from the exponent part.

[Embodiments of the invention]

FIG. 1 shows an overall block diagram of an exponential underflow detection circuit according to the present invention. In Figure 1, line 10 is given the mantissa part of the operation result (actually the value obtained by decoding the zero digit of the mantissa part), and line 11 is given the exponent part (the exponent part of the operand and operand). 6 subtraction number detection circuit 12 where the larger one) is suspected
Now, we check the arithmetic number of consecutive zeros from the upper part of the mantissa obtained from line 10, and detect the number to be subtracted from the exponent (subtraction number). The subtraction number detected by the subtraction number detection circuit 12 and the exponent part of the line 11 are given to the exponent subtraction circuit 14,
By subtracting the value indicated by the subtraction number from the exponent part, the corrected exponent part is output on the line 16. On the other hand, line 1
The exponent part of 1 also serves as an input to the exponent subtraction result prediction circuit 13. There are a plurality of sets of exponent subtraction result prediction circuits 13, which predict and output a plurality of subtraction results corresponding to each possible subtraction number based on the photographed exponent part. That is, a carry corresponding to each possible subtraction number is output. The exponent underflow generation circuit 15 is connected to the subtraction number detection circuit 12.
Input the detected subtraction number and each predicted value of the exponential subtraction result prediction circuit 13, select the predicted value corresponding to the subtraction number, and if the predicted value does not indicate a carry indicating successful subtraction,
An exponential underflow signal is output on line 17.

FIG. 2 shows a specific example of the subtraction number detection circuit 12.

In Figure 2, Z11-N-Z42-N is the value obtained by decoding the zero digit of the mantissa, and Zll-N is the value of the zero digit of the mantissa.
Only the digit is O, and the 0th and 1st digits of Z12-N are 0. Z13
-N indicates that the 0th to 2nd digits are 0, and the same applies hereinafter. N1-N-N14-N is the output, N1-
N is the subtraction number 1 (the value to be subtracted from the exponent part is 1), N1
-N indicates the number of subtractions of 2, and in the following, similarly, N14-N indicates the number of subtractions of 14.

Figure 3 shows a specific example of the exponent subtraction result prediction circuit, where the exponent part is 7.
In Figure 3, which is made up of bits, E1 to E7 are each bit of the exponent part, and P or N indicates the logic of the corresponding bit.
Indicates l''' or 0'''. Cl-N-C14-N is the predicted output, CI-N indicates the carry corresponding to the subtraction number 1, C2-N indicates the carry corresponding to the subtraction number 2, and similarly, 014-N indicates the subtraction number 14. Indicates the carry corresponding to .

FIG. 4 shows a specific example of the exponential underflow generating circuit 15. The exponential underflow generation circuit 15 selects the output Cl -N-Cl4-N of the exponential subtraction result prediction circuit 15 corresponding to the output N1-N-N14-N of the subtraction number detection circuit 12 using AND gates 101-114. However, if there is no carry in the selected one, the circuit outputs an exponential underflow EXPUDF-P to the line 17 through the AND gate 115. Note that MASK-N indicates a program mask that permits exponential underflow interrupts.

〔Effect of the invention〕

According to the present invention, the number of gate stages is considerably reduced compared to the conventional method, and an exponential underflow interrupt can be detected early. Therefore, a condition code can be set early, and therefore, a 2-branch instruction can be determined early. There is. Furthermore, as is clear from the embodiments, there is an advantage that the number of gate stages does not increase even if the number of consecutive zero digits from the upper part of the mantissa is long.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of an embodiment of the present invention. FIG. 2 is a detailed diagram of the subtraction number detection circuit, FIG. 3 is a detailed diagram of the exponent subtraction result prediction circuit, and FIG. 4 is a detailed diagram of the exponent underflow detection circuit. IO...-mantissa input line, 11... Exponent input line, 12... Subtraction number detection circuit, 13... Exponent subtraction result prediction circuit, 15... Exponent underflow generation circuit, I7... - Exponential underflow output line. Condolence 1 image middle ゛correct 1ne*i meal 4Ml, -? >centre·
-7゜-Figure 2 Figure 3

Claims (1)

[Claims] (1) A subtraction number detection circuit that detects a value to be subtracted from the exponent part (subtraction number) by checking the number of consecutive zero digits from the upper part of the mantissa part in a circuit for detecting exponent underflow in floating point arithmetic; An exponent subtraction result prediction circuit that inputs an exponent part and predicts multiple subtraction results depending on the number of subtractions that may occur, and selects the output of the subtraction number detection circuit based on the value detected by the subtraction number detection circuit. An exponential underflow detection circuit comprising: an exponential underflow generation circuit that generates an exponential underflow.