JPH0469734A - Underflow exception generation predicting circuit for floating point addition/subtraction - Google Patents

Abstract

PURPOSE:To suppress the decrease of the processing speed of a processor to the minimum by comparing a constant value generated by a constant generating means with the value of the maximum exponential part selected on the way of calculation of the addition/subtraction of a floating point of a first and a second operands, and outputting a signal for predicting the underflow exception generation in accordance with the result of this comparison. CONSTITUTION:This circuit is constituted of a constant circuit 101 for generating a constant by inputting a prescribed signal, a code extending circuit 102 for inputting an exponential part intermediate result 210, and a comparator 103. In such a state, a constant value generated by the constant circuit 101 and the value of the maximum exponential part selected on the way of calculation of the floating point addition/ subtraction of the first and the second operands are compared by this comparing circuit 103, and in accordance with the result of this comparison, a signal for predicting the underflow exception generation is outputted. Accordingly, as for most of cases in the case a floating point operation which does not generate an outflow exception is executed, it is judged that an exception is not generated in an early stage of the operation. In such a manner, the instruction execution control can be executed with high efficiency.

Description

[Detailed Description of the Invention] [1I r+'J] (Industrial Application Field) The present invention relates to an information processing device that performs floating point addition and subtraction, and more specifically, the present invention relates to an information processing device that performs floating point addition and subtraction. The present invention relates to an underflow exception occurrence prediction circuit that can predict the occurrence of an underflow exception at the beginning of an operation.

(Prior Art) Many microprocessors commercialized for information processing execute instructions in a pipeline in order to perform processing at high speed. That is, the execution of each instruction is divided into several stages, and each stage is executed in several cycles. Then, before executing or terminating the first fi instruction,
Start execution of next instruction. By doing this,
It aims to shorten the operating cycle and increase the throughput of instruction execution.

Since the execution content of each instruction differs depending on the type of instruction, the number of execution cycles of an instruction varies depending on the type of instruction. For example, the floating point arithmetic instruction j1 usually requires a larger number of execution cycles than other instructions.

In recent years, with the increase in the degree of integration of LSIs, a large number of processors equipped with 17 dynamic point arithmetic instructions are being commercialized. ? When executing a ``i+ floating-point operation, it may be necessary to handle exceptions that occur 1 (-) depending on the type of operand and the type of operand. There are several types of these examples.
Performing this processing in hardware may require a heavy load in terms of operating speed and circuit scale. Therefore, due to implementation trade-offs, many processors handle certain types of exceptions using software.

In Zunawa's software, only the circuit that issues an l-wrap when a certain type of exception occurs is implemented, and the example I is issued in the middle of an operation. When the trap is issued, the trap routine h is executed. This trap routine causes software to execute the floating point arithmetic instruction that caused the exception. The trap routine also handles exceptions and calculates the result of the operation.

In a processor that performs bi-line execution of instructions, several instructions are executed in parallel. Example of a floating-point operation instruction that needs to be processed by a wrap routine When the instruction to be executed is completed, the instructions to be executed after all the lf floating point operation 'L instructions are invalidated, and the processing is shifted to the trap routine. When execution of the lf floating point arithmetic instruction is completed within the trap routine, processing returns from the trap routine.

The instruction to be executed after the return N'r is the instruction following the floating point operation p instruction.

When setting up such a processor, it is important to have the trap routine control the processing so that the instructions after the one that generated the trap are in the same state as if they had not been executed at all. .

For example, consider the instruction sequence shown in FIG. 7(a). In the figure,
FADD is an instruction to perform mezzo dynamic point addition. F M
OV is a transfer instruction between registers.

The F A D D instruction sets the value of register r] and register 1.
Performs floating point addition of the values of and stores the result in register 2.
Store in. The first FMOV instruction transfers the value of register 3 to register (). The FMOV instruction No. 2 1-1 transfers the value of 1 register 0 to register 1.

Assume that the instruction execution bi-line is configured as follows: instruction fetch (F), decode and register read (D), operation (E), and register write = 7>(W). Further, it is assumed that the register reading hardware and the calculation result are configured so as to be bypassed, and the l-digital dynamic point adder/subtractor has a pipeline configuration capable of outputting the calculation result every cycle.

In this case, assuming that there are no exceptions that cause traps, instruction actual fi control as shown in FIG. 7(1)) is possible. In other words, an instruction is fetched in one cycle (11).
F) and 2 cycles] -1 and this D: 11-C, 34
Implement operation p (E) in 56 cycles. Furthermore, the result is written to the 7 cycle ll'ff register (W).

However, if an exception occurs that causes a trap, such control may be inconvenient. for example,
6 cycles [FA I on 1] D or send a trap 4 (
If you do so, a system error will occur. That is,
Whenever starting Traplutin, the first FM
The execution of the OV instruction ()2) is in a state where it has finished.
FADD instruction in trap routine? The value of the register [) used when executing -i is different from the value that should originally be used.

Therefore, if there is a possibility that the FADD command may issue a trap, it is necessary to perform control as shown in FIG. 7(C). Zunawaji, the first FMOV command is F A I
) Until it is determined that the D command does not generate a trap.
C1 Specifically, is it necessary to make the write operation to register 0 wait from 6 to Noicle 1-1? Also, as a result,
The FMOV command No. 2 and 1 is also made to wait as shown in the figure.

In this way, when exception handling is performed using a trap routine, the performance of the process from block to node will be degraded.

There are several types of exceptions that can occur during addition and subtraction of if dynamic point numbers. Some exceptions occur during the first stage of execution, while others occur near the end of execution. As is clear from the above explanation, when the former exception handling is performed by a trap routine, the performance is not affected and the impact is small. However, if the latter exception is handled by a trap routine, the performance will be significantly lowered by 1.

An example of the latter type of exception is the underflow exception. This exception occurs when the exponent part of the calculation result becomes a value smaller than the expression range of the format.

This underlow exception will be explained using the IEEE754 standard as an example. This standard stipulates that the calculation results are, in principle, converted into 11-values and output. The processing when the exponent part of the calculation result is smaller than the expression range of the city-standardized number differs depending on the operation mode specified by the user. There is an operation mode in which the old calculation process is continued using the result of the default process, and an operation mode in which the old calculation process is interrupted.

In the latter mode of operation, an underflow exception flag is set and the user is notified when the calculation process is interrupted.

When the former operation mode is selected, the calculation result is expressed as a denormalized number. First, in order to represent the exponent part with the minimum value of the expression range, the mantissa part is shifted to the right by the necessary amount. Then, this intermediate result is rounded according to the specified rounding factor. When a loss of precision occurs during this rounding process, an underflow exception flag is set.

As is clear from this explanation, strictly speaking, the underflow exception in the current IEEE745 is different from "the case where the exponent part of the operation result becomes a value smaller than the expression range of the format". Please note that the underflow exception in this specification refers to the latter (
Write down =1.

In order to perform this double default processing in hardware, a priority encoder for determining the number of shifts of the mantissa and a valen shifter for shifting the mantissa are required. And for these circuits,
Loads such as an increase in circuit scale and a decrease in operating speed occur. Therefore, this exception is often implemented to be handled by a trap routine.

The above-mentioned waiting control for subsequent instructions is necessary when an exception actually occurs, but when an exception does not occur, the control is completely useless. Therefore, if it can be determined early in the execution of an operation that this exception will not occur, it is possible to perform control that predicts the occurrence of an exception.

In other words, if it is determined that an exception will not occur, the seventh
The control shown in FIG. 7(b) is performed, and in other cases, it is predicted that an exception will occur and the control shown in FIG. 7(c) is performed. This greatly contributes to suppressing the performance degradation of the processor.

In this way, in a processor that uses a trap routine to handle underflow exceptions in floating-point additions and subtractions, in order to prevent performance degradation, the processor checks for the occurrence of an underflow exception early in the execution of an operation, and detects the occurrence of an underflow exception when it cannot be determined whether an underflow exception has occurred. An underflow exception generator δI11 circuit that outputs an underflow exception generator 4I] signal is required.

(Problems to be Solved by the Invention) As explained above, in conventional processors that handle underflows in floating-point addition and subtraction using trap routines, the processing speed of the processor is reduced to control the waiting of subsequent instructions. The disadvantage is that the performance of

The present invention has been made to address these shortcomings of conventional devices, and its purpose is to check for the occurrence of an underflow exception early in the execution of a floating-point addition/subtraction, in order to minimize the deterioration in performance; To provide an underflow exception occurrence prediction circuit that outputs an exception occurrence prediction signal only when it cannot be determined whether an underflow exception has occurred.

[Configuration of the Invention (Means for Solving the Problems) The features of the present invention are as follows.
In the normalization process performed on the maximum operand exponent part selected when executing floating-point addition/subtraction of the second operand, the maximum number that may be subtracted from the exponent part is determined whether to perform true addition or not. a signal indicating whether the arithmetic operation is single-precision arithmetic or double-precision arithmetic; Second
a constant generating means that generates a constant in response to a signal indicating whether the difference between the exponent parts of the operands is 2 or more; and a constant value generated by the constant generating means and the first. Second
Comparison means for comparing the value of the maximum exponent part selected during calculation of floating point addition/subtraction of the operand, and detecting the occurrence of an underflow exception according to the comparison result.
This circuit is located in an underflow exception prediction circuit for floating-point addition/subtraction that outputs a signal for II.

(Operation) In this circuit, first, in the first stage of constant generation, the maximum value that may be subtracted in the normalization process that is performed on the value of the maximum exponent part selected during addition and subtraction of floating point numbers is set as a constant. It occurs as follows. This constant value determines the state of the floating-point addition/subtraction, i.e., whether it is a single-precision operation, a double-precision operation, a true addition, a true subtraction, and the difference between the exponents of both operands to be operated on. The values are set depending on whether or not the value is 2 or more. These constant values are then compared in the comparison means with the value of the maximum exponent part selected during the floating point addition/subtraction calculation. This comparison result indicates whether or not the exponent part of the calculation result falls within the exponent part expression range of the normalized number, so if it is determined that the comparison result exceeds this expression range, the floating point addition/subtraction 3? It is possible to predict the occurrence of an underflow exception. Therefore, in this circuit, it is possible to predict the occurrence of an underflow exception based on the output of the comparison means.

(Embodiment)] 2. Fig. 1 is a block diagram showing an underflow exception occurrence prediction circuit according to an embodiment of the present invention, and Fig. 2 is a block diagram showing an underflow exception occurrence prediction circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing a decimal point addition/subtraction device.

Prior to explaining the underflow exception generator-1 circuit shown in Figure 1, the configuration of a general floating-point addition/subtraction device and the order of operation of floating-point addition/subtraction will be explained with reference to Figure 2. , to facilitate understanding of embodiments of the present invention.

A portion 200 surrounded by a dotted line in FIG. 2 shows the configuration of a general floating point addition/subtraction device.

As shown, this device includes an exponent calculation circuit 216, a swap circuit 217, a digit adjustment circuit 218, a mantissa addition/subtraction circuit 219, a normalization/rounding circuit 220, and an exponent adjustment circuit 221.

It should be noted that in this device, the circuit that calculates the sign part by 51 is not relevant to the explanation of the occurrence of the underflow exception of the present invention, so it is omitted in Fig. 2. The underflow exception occurrence prediction circuit 222, which is one embodiment, includes an exponent calculation circuit 216 as shown in the figure.
It is connected to a floating point adder/subtracter so that the output at

In this device, the exponent part 81 arithmetic circuit 216 includes a first
The exponent signal 202 of the operand and the exponent signal 205 of the second operand are input to the swap circuit 2]7.
The operand mantissa signal 203 and the second operand mantissa signal 206 are input manually. Further, as a calculation result, the exponent part signal 208 is sent from the exponent part adjustment circuit 22] to the normalized/
A mantissa signal 209 is output from the rounding circuit 220. The number 71 part is determined by the calculation result of the mantissa part, or
Since this is not related to the content of the present invention, its explanation will be omitted.

Calculation of the exponent and mantissa parts in floating-point addition and subtraction can be roughly divided into the following four processing stages.

Processing 1: (Exponent part intermediate result calculation and mantissa part digit alignment) 1st. Second operand exponent part 202. 2 f', 1
5 with the exponent part addition result 216], the larger one is output as the exponent part intermediate result 210. Furthermore, the mantissa part is digit-aligned using the calculation result of the exponent part.

In other words, the operand mantissa part 213 with the smaller exponent part is shifted to the right by the difference 215 between the two operand exponent parts in the digit alignment circuit 2]8, and the digit-aligned mantissa part 213 is shifted to the right by the difference 215 between the two operand exponent parts.
14 is generated. The other operand mantissa is signal 2]
2 and output as is.

Process 2: (Calculation of mantissa intermediate result) Calculate the intermediate result of the mantissa. Fixed-point addition and subtraction between the digit-aligned mantissa value 214 and the other operand mantissa value 212 is performed in an addition/subtraction circuit 219 to calculate a mantissa intermediate result 211.

Whether addition or subtraction is to be performed is determined using the type of instruction and the sign part of the operand. Note that in order to distinguish the addition and subtraction here from the addition and subtraction of instructions, this specification calls them true addition and true subtraction.

Process 3: (Normalization) The mantissa is normalized and the exponent is adjusted accordingly. iE normalization is to adjust the binary 1'' of the mantissa intermediate result 211 to a predetermined digit position.Therefore, it is performed by shifting the mantissa intermediate result 211.The result 211 is shifted to the right. If the result 211 is shifted to the left, it is necessary to add the shifted number to the intermediate result 210 of the exponent part.If the result 211 is shifted to the left, it is necessary to subtract the shifted number from the intermediate result 210 of the exponent part 1. .

Process 4: (Rounding/re-1F normalization) Refer to the lower few bits of the normalized mantissa intermediate result,
Increment the intermediate result if necessary according to the rounding mode. When incrementing I, an overflow may occur from the most binary bit of the 1F normalized mantissa intermediate result. In this case, it may be necessary to renormalize the mantissa. That is, the mantissa is shifted one digit to the right, and the value of the exponent is incremented by one. Is it like ``2''? Addition or subtraction of floating point numbers is performed.

The underflow exception occurrence prediction circuit of the present invention receives as input the result of selecting the maximum exponent part performed in process 1 of the processing flow, and predicts the occurrence of an underflow by comparing this manual value with a predetermined constant. It is based on that. As can be seen from the processing flow described above, this human input signal is generated immediately after the start of calculation. Therefore, by using this signal to predict the occurrence of an underflow exception, if it is determined that an underflow exception will almost never occur, the instruction execution control shown in FIG. 7(b) is performed; otherwise, It is determined that an underflow example has occurred, and control for waiting for subsequent instructions as shown in FIG. 7(C) is performed. By doing so, even if an underflow exception does not occur, it is possible to perform processing quickly without unnecessarily slowing down the processing speed of the processor by always performing waiting control.

Furthermore, as is clear from FIG. 2, the maximum value that can be subtracted from this human power value 210 is the subtracted value due to the mantissa normalization in process 3, which is the left shift number. . Therefore, if the value obtained by subtracting this value from the result of addition of the exponent part falls below the expression range of the exponent part, it can be predicted that there is a possibility that an underflow exception will occur. In other cases, it can be determined not to generate an underflow exception. The present invention basically configures a circuit that predicts the occurrence of an underflow exception based on this boiling method. Furthermore, compared to the exponent expression range, the range in which the value of the intermediate exponent result varies due to normalization is very small. Furthermore, the range of responses due to normalization is determined by the information on whether it is single-precision arithmetic or double-precision arithmetic, the information on whether it is true addition or true subtraction, and the difference between the exponents of both operands of 2 or more. It is determined based on the information whether it is white or white. By doing this, in the large 2F case where an underflow exception does not occur, it can be determined at an early stage that an exception will not occur.

Next, embodiments of the present invention based on two basic concepts will be described.
This will be explained below. Note that this embodiment is configured for a floating-point addition/subtraction device conforming to the IEEE754 standard. This device is capable of performing both single precision and double precision operations. Also, only normalized numbers can be used as operands. If a denormalized number operand is entered manually, it is handled in software by a trap routine. Since the occurrence of this trap can be determined by referring to the operand value immediately after the start of the operation, this specification does not affect performance and has little effect.

The format of tit precision data in the IEEE754 standard is shown in FIG. 3(a), and the format of double precision data is shown in FIG. 3(b). In both figures, S is the sign part,
e indicates an exponent part, f indicates a mantissa part, and the numbers shown indicate the number of bits in each part.

Note that the exponent part is expressed in digits. Further, the mantissa part is expressed by an absolute value and a sign.

FIG. 4 shows the correspondence between data formats and expressed numbers. FIG. 4(a) is an i, 11-precision correspondence table, and FIG. 4(b) is a double-precision correspondence table.

With this format, the exponent value ranges from 0 to 255 in single precision and from 0 to 2°47 in double precision.

The exponent expression range for single precision normalized numbers is 1 to 254, and for double precision it is 1 to 2046.

(7) Therefore, in the addition/subtraction p device of FIG. 2, when the exponent part of the calculation result becomes smaller than O, an underflow exception occurs and a trap is generated.

In addition, during the old arithmetic, even if the value of the exponent part deviates from the exponent part expression range of the TI7 present number, the exact value can be found, so that the representation of the exponent part in the arithmetic unit expands the bit value. 2
Complement data is often used.

FIG. 1 shows an exception occurrence prediction circuit according to an embodiment of the present invention. As shown in the figure, this circuit 222 includes a constant circuit 101 that generates a constant by inputting a predetermined signal, which will be described later;
It is comprised of a sign extension circuit 102 which receives the exponent intermediate result 210 shown in FIG.

This comparison circuit 103 detects the occurrence of an underflow exception “I”.
-Fll signal 223 is generated.

Since this prediction circuit 222 needs to be compatible with both single-precision and double-precision arithmetic operations, it is necessary to convert the exponent part intermediate result 210 into data 109 of the same bit width and handle it within the circuit. For this purpose, for single precision the input value 21
It is necessary to convert 0 into data with the same bit width as in sign-extended l-double precision operation.

The sign extension circuit 102 is a circuit that performs bit width extension for this purpose. Is it an operation being executed?) Is it an 11-precision operation?
A signal 105 specifies whether the operation is a double-precision operation.

Comparison circuit 103 compares signal]09 and signal 108,
When the value of signal 109 is less than or equal to the value of signal 108, a signal value indicating that an underflow exception is predicted to occur is output as signal 223.

Constant circuit 101 is a circuit that generates the signal 108. This circuit 1.01 has a double precision of 111. A signal that specifies whether it is accurate, a signal that indicates the time precision operation of Zunawaji1, and a signal that indicates f1''S precision operation when it is 0 (1()5), and a signal that specifies whether it is true addition or subtraction, that is, the signal of 1. A signal 106 indicating addition of armor and subtraction of armor of 0, and a signal specifying that the difference between both operand exponents is 2 or more or 1 or more, an exponent of the poetry operand of Zunawaji 1. A signal indicating that the difference between the indices is 2 or more, and a signal indicating that the difference between the exponents of the 0 poetic operands is 1 or less]07 are manually input.

FIG. 5 shows the respective signals 1-0 indicating the states of both operands.
5. This is a table showing how the constant circuit 101 generates constants such as 106 and 107. In other words, the constant circuit 1.01 generates a constant 0 when it is determined that true addition is to be executed based on the signal 106, regardless of jll, precision, or double precision, and generates a constant 0 regardless of whether the signal is jll, precision, or double precision. True subtraction is performed by signal 106, and a constant 1 is generated if the difference between the exponents of both operands is greater than or equal to 2. !・If the difference between the exponents of the operands is less than or equal to 1, a constant 24 is generated. Furthermore, it is a double-precision operation, and signal 106 indicates the true subtraction, and signal 107 indicates that the difference between the exponents of both operands is less than or equal to 1. If it is determined that this is the case, emit constant 53! Do 1. Each of these constants is compared with a signal representing the value of the initial expanded maximum operand exponent in the comparator circuit 103 as a series of −1 (as in C signal 1 (, 19), i.e., the signal 1
09 or smaller than these constants, it is determined that the start 11 of the reed dart row example I will be 'f-4ill'.

Next, the basis of each constant shown in FIG. 5 will be explained to further clarify the understanding of the present invention.

As described in FIG. 2 and the description of Processes 3 and 4 above, the lodging result of the exponent part is obtained by normalizing the index part intermediate 1t'i result and iff+1. ', IJJ, the mantissa digit i'''T, i. In IE normalization, the maximum number of digits that can be shifted in the mantissa that can be 1iJ is shown in Figure 6. The origin of I is the number of I shift digits 1.:O relationship [7, and of course only the subtraction of J'!+1.'j is a problem. From the number of left-shift digits, it is possible to obtain constants corresponding to λ·1 for each state shown in FIG.

As mentioned above, the occurrence of an underflow exception is predicted by comparing each of the constants and the signal 10 (J) in the comparison circuit 103.Next, we will give a concrete example of how to predict the occurrence of this underflow exception. and explain.

If an underflow exception does not occur during single-precision floating-point addition/subtraction, the intermediate result of the exponent part is expressed as −
Takes values in the range 1 to 254.

The exception occurrence prediction circuit according to the present invention determines that an underflow exception will not occur when the value obtained by subtracting the constant 24 from this value is greater than or equal to 1, that is, when the intermediate result of the exponent part is in the range of 25 to 254. . Further, if the difference between the exponent parts of both operands is 2 or more, it is determined that an underflow exception will not occur when the intermediate result of the exponent part is a value in the range of 2 to 254 because it is a constant or 1. Furthermore, when performing true addition, if the intermediate result of the exponent part is in the range of 1 to 254, it is determined that no underflow exception has occurred.

Also, in double-precision floating-point addition and subtraction, an underflow exception occurs (1), and if not, the intermediate result of the exponent part is 2'-3. However, in the exception occurrence prediction circuit of the present invention, since the constant is 53, the intermediate result of the exponent part is 54 to 2.
When the value is in the range of f'l 4 6, it is determined that an underflow exception has occurred and 7 has not occurred. Also, if the difference between the exponent parts of both operands is 2 or more, it is a constant or 1, so if the intermediate result of the exponent part is a value in the range of 2 to 2 0 4 6, it is determined that an underflow exception will not occur. . Furthermore, when performing true addition, it is determined that an underflow exception will not occur if the intermediate result of the exponent part is a value in the range of 1 to 2 0 4 6.

In this way, by using the underflow exception occurrence prediction circuit, in most cases when floating point operations are performed that do not generate an underflow exception,
It is determined early in the calculation that example 1 does not occur/1. Therefore, in this case, it is possible to perform the instruction execution control shown in FIG. 7(b) to increase the processing speed per C1. On the other hand, only when the occurrence of underflow example No. 1 is predicted in this circuit, an instruction is executed by waiting control as shown in FIG. 7(C). By doing this,
Overall, the efficiency of instruction execution control of the processor can be greatly improved.

[Effects of the Invention] As described in detail below with reference to embodiments, the underflow exception occurrence 'r-detection circuit according to the present invention can perform floating-point addition/subtraction without causing an underflow exception. In most cases, it is determined early on that an exception will not occur. Therefore, a processor using this circuit can perform efficient instruction execution control.

[Brief explanation of the drawing]

1 is a block diagram of an underflow exception occurrence prediction circuit according to an embodiment of the present invention; FIG. 2 is a diagram showing the connection relationship between the circuit shown in FIG. 1 and a general t7 dynamic point addition/subtraction device; The figure and Figure 4 are the format of dynamic point data according to the IEEE standard! Figure 5 is a diagram showing the constants generated in the circuit of Figure 1, Figure 6 is a diagram showing the maximum number of shift digits of the mantissa during normalization and renormalization, and Figure 7 is a diagram showing the trap. Handling exceptions in routines 11! FIG. 3 is a diagram for explaining instruction execution control of i. 101...Constant generation circuit 102...Sign extension circuit 103...Comparison circuit

Claims (1)

[Claims] The maximum number that may be subtracted from the exponent part in the normalization process performed on the maximum operand exponent part selected when executing floating point addition/subtraction of the first and second operands. , a signal indicating whether true addition is to be performed, a signal indicating whether it is a single-precision operation or a double-precision operation, and the first
, a constant generating means that generates a constant in response to a signal indicating whether the difference between the exponent parts of the second operand is 2 or more, and a constant value generated by the constant generating means and the first;
Comparing means for comparing the value of the maximum exponent part selected during the calculation of floating point addition/subtraction of the second operand, and outputting a signal predicting the occurrence of an underflow exception according to the comparison result. Underflow exception prediction circuit for floating-point addition and subtraction.