JPH06290023A - Floating point arithmetic unit - Google Patents

Abstract

PURPOSE:To solve a trouble of performance drop to be generated when an interruption report is delayed by quickly detecting the operation exceptions of an exponent overflow and an exponent underflow by a floating point multiplying instruction and informing an interruption. CONSTITUTION:An operation exception detecting part 200 consists of a post- multiplication normalized quantity detecting circuit 201, a post-multiplication exponent calculating circuit 202, an exponent underflow detecting circuit 203, an exponent overflow detecting circuit 204, an AND gate 205, etc., and constituted so that the normalized quantity of the multiplied result of a multiplicand and a multiplier is found out by the circuit 201, the exponent of the multiplied result is fount out by the circuit 202 and an exponent overflow and an exponent underflow are quickly detected respectively by the circuits 203, 204 based on the exponent of the multiplied result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic unit and, more particularly, to a technique effectively applied to a detection technique for detecting exponential overflow and exponent underflow operation exceptions at high speed.

[0002]

2. Description of the Related Art For example, in the field of scientific and technological calculation, a floating point data format is used as a main data representation format.

Therefore, the data format of floating point data in a HITAC M series information processing apparatus is shown in FIG. 4, and the floating point data is composed of a 1-bit sign part S, an exponent part 7 bits and a mantissa part. Become.

The 1-bit sign part is a code for the mantissa, and the 7-bit exponent part is a number obtained by multiplying the mantissa part represented by a hexadecimal number in the access64 representation by a power of 16.

Next, when the displayable range of the index is shown in FIG. 5, the index can be displayed from +63 to -64, and +6.
An index overflow of 4 or more and an index underflow of -65 or less.

Further, the mantissa part is a hexadecimal number having a decimal point to the left of the most significant digit as shown in FIG. 4, and the data format of the floating point number is, for example, a short precision format in which the mantissa part is 6 digits and 3 bytes. There are three formats: a long precision format with a mantissa of 14 digits and 7 bytes, and an extended precision format with a mantissa of 28 digits and 14 bytes.

In the floating-point data, the normalized data whose mantissa has the most significant digit not 0 (hereinafter, the normalized amount is referred to as 0 digit) and the unnormalized data whose mantissa has the most significant digit 0 ( Hereinafter, the normalization amount is described as one digit on the left), and in the floating-point multiplication instruction, the normalized operation result is obtained in order to maintain the accuracy of the data.

Next, the algorithm of multiplication of floating point data in the prior art will be described.

(1) Two operands of a multiplicand and a multiplier are normalized.

(2) The mantissa of the intermediate result is obtained by multiplying the mantissas of the two normalized operands, and further normalized 2
The exponent of the intermediate result is obtained by subtracting 64 from the value obtained by adding the exponents of the two operands.

(3) The intermediate result is normalized and the mantissa is truncated to the required length to obtain the multiplication result. At that time, the mantissa of the intermediate result may be normalized data or non-normalized data, and the normalization amount is 0 digit or 1 digit on the left. The normalization amount of the multiplication result is calculated from the mantissa of the intermediate result. Ask.

(4) It is checked whether the exponent value of the multiplication result is an exponent overflow or an exponent underflow, and it is an exponent underflow, and the exponent underflow interrupt mask is 0.
In the case of, the multiplication result is set to 0, and when the exponent underflow occurs and the exponent underflow interrupt mask is 1 or in the case of exponent overflow, the operation exception interrupt is reported.

(5) When an operation exception interrupt of exponential overflow or exponent underflow is reported, the execution of the next and subsequent instructions is suspended and the interrupt processing is performed.

[0014]

However, in the prior art as described above, after the multiplication result is obtained, the operation exceptions of exponent overflow and exponent underflow are obtained from the exponent value of the multiplication result. Unless the result is obtained, the operation exception interrupt reporting is delayed because the operation exceptions for exponent overflow and underflow cannot be found.

When the operation exception interrupt report is delayed, the following measures must be taken for the execution of the next and subsequent instructions.

As a first method, execution of the next and subsequent instructions is waited until the operation exception interrupt is determined.

Further, as a second method, if the next and subsequent instructions are executed even if the operation exception interrupt is not confirmed, and the operation exception interrupt of the multiplication instruction is reported during the execution of the next and subsequent instructions, The execution of the instruction being executed is stopped, and the data updated by the extra executed instruction is recovered. In this case, a register for saving the data and a procedure for recovering the data are required.

In the first method, there is a problem that the performance is lowered because the next and subsequent instructions cannot be executed until the interrupt is fixed.

Further, the second method also has a problem that the hardware such as a register for saving data increases and that the recovery process requires a long time so that the performance deteriorates.

Therefore, an object of the present invention is to detect an arithmetic exception of an exponent overflow and an exponent underflow of a floating point multiplication instruction at an early stage and perform an arithmetic exception interrupt,
It is to provide a floating point arithmetic unit that improves arithmetic performance.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0022]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the floating-point arithmetic unit of the present invention is a floating-point arithmetic unit that multiplies floating-point data and decodes the normalized multiplicand and mantissa of the multiplier to detect the normalized amount after multiplication. A post-multiplication normalization amount detection circuit, and a post-multiplication exponent calculation circuit for obtaining the post-multiplication exponent by the detected post-multiplication normalization amount and the exponent of the intermediate result obtained by adding the exponent of the multiplicand and the multiplier An exponent overflow detection circuit for detecting exponent overflow and exponent underflow operation exceptions from the exponent after multiplication and an exponent underflow detection circuit are provided.

[0024]

According to the floating point arithmetic unit described above, the post-multiplication normalization amount detection circuit decodes only the most significant digit of the normalized multiplicand and mantissa of the multiplier as shown in FIG. Can be asked. However, in this case, the normalized amount in all cases cannot be obtained.

There are also cases where the normalized amount after multiplication becomes 0 digit or 1 digit to the left depending on the value of the lower digit.
Further in that case, a more correct normalization amount can be obtained by increasing the number of digits to be decoded.

That is, it goes without saying that all the normalized amounts can be obtained by decoding all the digits.

However, in the case of decoding only the most significant digit of the multiplicand and the mantissa of the multiplier as shown in FIG. 3, the multiplicand,
When the value of the most significant digit of the mantissa of the multiplier uniformly occurs from 1 to F, the normalized amount can be obtained from the probability of 199/225.

The probability that the normalization amount cannot be obtained from the value of the lower digit is 26/225. In this case, even if the normalization amount is obtained from the multiplication result of the mantissa, which is a conventional method, in most cases. In, the normalized amount can be obtained by the normalized amount detecting circuit after multiplication.

Therefore, by directly decoding the mantissas of the multiplicand and the multiplier using the post-multiplication normalization amount detection circuit, the post-multiplication normalization amount can be obtained faster than the multiplication of the mantissa.

Further, when the normalized amount after multiplication is obtained, the value of the exponent of the intermediate result is ± 0 or -1 by using the obtained normalized amount by the exponentiation calculation circuit after multiplication, and the exponent of the multiplication result is obtained. The value of is obtained.

Further, if the value of the exponent of the multiplication result is obtained,
The exponent overflow and exponent underflow operation exceptions are found by the exponent overflow detection circuit and exponent underflow detection circuit that detect whether the exponent value of the multiplication result is 64 or more or -65 or less. In the case of underflow, the arithmetic exception can be detected by taking the logical product with the exponent underflow interrupt mask.

Thus, the post-multiplication normalization amount detection circuit for directly decoding the normalized multiplicand and mantissa of the multiplier to obtain the post-multiplication normalization amount, the exponent of the intermediate result, and the obtained post-multiplication normalization amount. The exponent calculation circuit for calculating the exponent of the multiplication result by the exponent, the exponent overflow detection circuit for detecting exponent overflow and exponent underflow from the exponent, and the operation exception detection means including the exponent underflow detection circuit, In most cases of multiplication, exponent overflow and exponent underflow operation exception interrupts can be detected early without waiting for the operation result.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic explanatory diagram showing the configuration of an arithmetic exception detecting unit in this embodiment, and FIG. 2 is a schematic explanatory diagram showing the configuration of a floating point arithmetic unit according to an embodiment of the present invention.

First, the configuration of the floating point arithmetic unit of this embodiment will be described with reference to FIG.

The floating point arithmetic unit 100 of this embodiment is
A floating point arithmetic unit for multiplying floating point data, for example, a multiplicand register 101 and a multiplier register 1
02, normalization circuits 103 and 104, normalized multiplicand register 105, normalized multiplier register 106, addition circuit 107, multiplication circuit 108, operation exception detection unit (operation exception detection means) 200, and intermediate result Register 109,
Normalization circuit 110 and exponent overflow detection circuit 11
1, an exponent underflow detection circuit 112, AND gates 113 and 114, a multiplication result inhibiting circuit 115, a multiplication result register 116, and an arithmetic control circuit 117.

The multiplicand register 101 is a register for storing a multiplicand, and the multiplier register 102 is a register for storing a multiplier. Then, the normalization circuits 103 and 10
4 normalizes the value of that register.

The normalized multiplicand register 105 and the normalized multiplier register 106 store the normalized multiplicand and multiplier, and the adder circuit 107 adds the exponents of the normalized multiplicand register 105 and the normalized multiplier register 106 to obtain 64. Find the index of the intermediate result.

The multiplication circuit 108 multiplies the mantissas of the normalized multiplicand register 105 and the normalized multiplier register 106 to obtain the mantissa of the intermediate result.

The operation exception detection unit 200 uses the normalized multiplicand register 105, the mantissa of the normalized multiplier register 106, the addition result of the adder circuit 107, and the exponent underflow interrupt mask 151 to detect the normalized amount undetectable signal 211 and the exponent. The underflow early interrupt report signal 212 and the exponent overflow early interrupt report signal 213 are output.

The intermediate result register 109 is used by the adder circuit 10.
7. The intermediate result of the multiplication circuit 108 is stored in the normalization circuit 1
10 normalizes the value of the intermediate result register 109.

The exponent overflow detection circuit 111 detects exponent overflow from the exponent normalized by the normalization circuit 110, and similarly, exponent underflow detection circuit 1
12 detects exponential underflow.

The AND gates 113 and 114 take the logical product of the exponent underflow interrupt mask 151 and the exponent underflow detected by the exponent underflow detection circuit 112, and the exponent underflow interrupt report signal 152,
The inhibition signal 154 that sets the multiplication result to 0 is obtained.

Further, in the case of exponent underflow, when the exponent underflow interrupt mask 151 is 0, the inhibition signal 154 for setting the multiplication result to 0 is set to 1, and when the exponent underflow interrupt mask 151 is 1. Sets the index underflow interrupt report signal 152 to 1.

The multiplication result suppression circuit 115 outputs the suppression signal 15
When 4 is 1, the multiplication result output from the normalization circuit 110 is set to 0, and the multiplication result register 116 holds the output value of the multiplication result suppression circuit 115.

The arithmetic control circuit 117 has an exponent underflow early interrupt report signal 212, an exponent overflow early interrupt report signal 213, a normalization amount undetectable signal 211, an exponent underflow interrupt report signal 152 and an exponent overflow interrupt. The report signal 153 is received and the calculation is controlled.

In the exponent overflow detection circuit 111,
The exponent overflow is detected when the value of the normalized exponent is 64 or more, and the exponent underflow detection circuit 112 detects the exponent underflow when the value of the normalized exponent is 65 or less.

Index underflow early interrupt report signal 21
2. The exponent overflow early interruption report signal 213 is detected by the operation exception detection unit 200, and the usual exponent underflow interruption report signal 152 and exponent overflow interruption report signal 153 are AND gate 113 and exponent overflow detection circuit. Detected by 111.

Next, the operation exception detection unit 200 will be described with reference to FIG.
The configuration of will be described.

The operation exception detection unit 200 of this embodiment includes a post-multiplication normalization amount detection circuit 201 and a post-multiplication exponent calculation circuit 20.
2, exponent underflow detection circuit 203, exponent overflow detection circuit 204, and AND gate 205, and performs early detection of exponent underflow and exponent overflow of floating-point data after multiplication.

The post-multiplication normalization amount detection circuit 201 obtains the post-multiplication normalization amount 210 and the normalization amount undetectable signal 211 from the mantissas of the normalization multiplicand register 105 and the normalization multiplier register 106.

The post-multiplication exponent calculation circuit 202 obtains the post-multiplication exponent from the interim result exponent of the adder circuit 107 for obtaining the interim result exponent and the post-multiplication normalization amount 210.

The exponent underflow detection circuit 203 detects the exponent underflow from the exponent after the multiplication obtained by the post-multiplication exponent calculation circuit 202. Further, the exponent overflow detection circuit 204 detects an exponent overflow from the post-multiplication exponent obtained by the post-multiplication exponent calculation circuit 202, and outputs an exponent overflow early interrupt report signal 213.

The AND gate 205 includes an exponent underflow interrupt mask 151 and an exponent underflow detection circuit 2.
The logical product of the exponent underflow detected by 03 is output, and the exponent underflow early interrupt report signal 212 is output.

Next, the detection of the normalized amount after multiplication will be described with reference to FIG.

As explained in the operation, for example, the normalized amount 210 after multiplication in FIG. 3 is a value when only the most significant digit of the normalized multiplicand and multiplier is decoded, and therefore in all cases. The normalized amount after multiplication cannot be obtained. But in most cases,
It goes without saying that the normalized amount can be detected.

First, the part where the mantissa most significant digit value 301 of the multiplicand is 1 and the mantissa most significant digit value 302 of the multiplier is 1 to 7 is as follows:
The normalized amount 210 after multiplication is the left one digit.

This is because the mantissa of the multiplicand is in the range of 0.10 ... 0 to 0.1F ... F and the mantissa of the multiplier is 0.10 ... 0.
To 0.7F ... The intermediate result is 0.0
X ... X, and the normalized amount 210 after multiplication is always left 1
It shows that it becomes a digit.

Further, the part where the value 301 of the most significant digit of the multiplicand is 1 and the value 302 of the most significant digit of the mantissa of the multiplier is 8 to F is
Since the normalized amount after multiplication is 0 digit or 1 digit on the left and the normalized amount cannot be detected, the normalized amount undetectable signal 211 is 1.

This is because the mantissa of the multiplicand is in the range of 0.10 ... 0 to 0.1F ... F and the mantissa of the multiplier is 0.80 ... 0.
To 0.FF ... F multiplication results in an intermediate result of 0.0
X ... X or 0.1X ... X, which indicates that the normalized amount 210 after multiplication has 0 digits or 1 digit on the left.

Further, the normalization amount is similarly obtained when the mantissa most significant digit value 301 of the multiplicand is 2 or later.

As described above, the post-multiplication normalization amount detection circuit 201 decodes the normalized multiplicand and multiplier to normalize the post-multiplication amount 210 or the normalization amount undetectable signal 2.
11 can be obtained.

Next, the operation of this embodiment will be described.

First, the floating-point arithmetic unit 100 sets the multiplicand and the multiplier in the multiplicand register 101 and the multiplier register 102.

Next, the multiplicand and multiplier set in the multiplicand register 101 and the multiplier register 102 are normalized by the normalization circuit 10.
Reference numerals 3 and 104 denote the normalized multiplicand register 10 that is normalized.
5. Set in the normalization multiplier register 106.

Further, the data set in the normalized multiplicand register 105 and the normalized multiplier register 106 are supplied to an adding circuit 107 and a multiplying circuit 108 to obtain an intermediate result,
It is set in the intermediate result register 109 and supplied to the operation exception detection unit 200.

Then, the arithmetic exception detecting section 200 inputs the exponent 142 and the exponent underflow interrupt mask 151 of the intermediate result which are the outputs of the adder circuit 107.

Further, in the operation exception detection unit 200, the mantissa 140 of the normalized multiplicand and the mantissa 1 of the normalized multiplier are set.
41 is input to the post-multiplication normalization amount detection circuit 201, and the post-multiplication normalization amount 210 and the normalization amount undetectable signal 211 are obtained.

Then, the post-multiplication exponent calculation circuit 202 obtains the post-multiplication exponent from the obtained post-multiplication normalization amount 210 and the intermediate result exponent 142.

Further, the exponent underflow and the exponent overflow are found in the exponent underflow detection circuit 203 and the exponent overflow detection circuit 204 by the exponent after the multiplication.

The AND gate 205 ANDs the exponent underflow thus obtained and the exponent underflow interrupt mask 151 to obtain the exponent underflow early interrupt report signal 212.

Further, the exponent overflow detection circuit 204
The AND gate 205 reports the calculated exponent overflow interrupt and exponent underflow interrupt to the arithmetic control circuit 117 as an exponent overflow early interrupt report signal 213 and an exponent underflow early interrupt report signal 212.

As described above, the post-multiplication normalized amount detection circuit 20
1, post-multiplication exponent calculation circuit 202, exponent underflow detection circuit 203, and exponent overflow detection circuit 20
The operation exception detection unit 200 composed of 4 or the like can early execute the operation exception interrupt processing.

Next, a case where an operation exception interrupt report is made by the conventional method will be described.

The method is the same as the above method until the intermediate result is set in the intermediate result register 109.

The normalization circuit 110 normalizes the intermediate result set in the intermediate result register 109, and then the exponent overflow detection circuit 111 and the exponent underflow detection circuit 112 obtain exponent overflow and exponent underflow.

Further, the exponent underflow detection circuit 11
The AND gate 11 is obtained by the exponent underflow obtained in 2 and the exponent underflow interrupt mask 151.
Reference numeral 3114 calculates the logical product of them and obtains the inhibition signal 154 or the exponent underflow interrupt report signal 152 that makes the multiplication result 0.

Then, the multiplication result inhibiting circuit 115 inhibits the multiplication result output from the normalizing circuit 110 when the inhibition signal 154 obtained by the AND gate 114 is 1, and stores 0 in the multiplication result register 116. To do.

Further, the exponent overflow detection circuit 11
1. The AND gate 113 outputs the calculated exponent overflow interrupt and exponent underflow interrupt to the exponent overflow interrupt report signal 153 and the exponent underflow interrupt report signal 15
2 is reported to the arithmetic control circuit 117.

Next, when the normalization amount undetectable signal 211 is 0 and early detection is possible, the arithmetic control circuit 117 exponent underflow early interrupt report signal 212 and exponent overflow early interrupt report signal 213. Receive the operation exception report by.

Further, the normalization amount undetectable signal 211 is 1
When the early detection is impossible, the operation exception interrupt report is received by the exponent underflow interrupt report signal 152 and the exponent overflow interrupt report signal 153.

When the normalization amount undetectable signal 211 is 1 and early detection is not possible, the next transition is made until the exponent underflow interrupt report signal 152 and the exponent overflow interrupt report signal 153 are determined. Holds the execution of instructions.

As described above, even when the normalized amount after multiplication cannot be detected, the operation exception can be detected by the same method as the conventional method.

Therefore, the floating point arithmetic unit 1 of this embodiment
According to 00, the post-multiplication normalization amount detection circuit 201, the post-multiplication exponent calculation circuit 202, and the exponent underflow detection circuit 20.
The operation exception detection unit 200 including the 3 and the exponent overflow detection circuit 204 can detect an operation exception of a floating-point multiplication instruction at an early stage, report an operation exception interrupt, and improve the processing performance of the floating-point multiplication instruction. it can.

Although the invention made by the present inventor has been concretely described above based on the embodiments, the present invention is not limited to the embodiments but can be variously modified without departing from the scope of the invention. Needless to say.

[0085]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, in the operation of floating-point data, the operation exception detecting means determines whether or not the normalization amount can be detected, and in most cases, the normalization amount is detected and the normalization amount is detected early. Exponent overflow and exponent underflow can be detected. In other cases, exponent overflow and exponent underflow can be detected by the same method as the conventional method.

As a result, it is possible to detect the exponent overflow and exponent underflow operation exceptions of the floating-point multiplication instruction at an early stage and report the interrupt, and solve the problem of performance degradation that occurs when the interrupt report is delayed. Therefore, the performance can be improved.

[Brief description of drawings]

FIG. 1 is a schematic explanatory diagram showing a configuration of an arithmetic exception detection unit in this embodiment.

FIG. 2 is a schematic explanatory diagram showing a configuration of a floating point arithmetic unit according to an embodiment of the present invention.

FIG. 3 is a schematic explanatory diagram showing a normalized amount after multiplication of the operation exception detection circuit in the present embodiment.

FIG. 4 is a schematic explanatory diagram showing a data format of floating point data.

FIG. 5 is a schematic explanatory diagram showing a displayable range of exponents of floating-point data.

[Explanation of symbols]

 100 Floating point arithmetic unit 101 Multiplicand register 102 Multiplier register 103, 104, 110 Normalization circuit 105 Normalized multiplicand register 106 Normalization multiplier register 107 Adder circuit 108 Multiplier circuit 111, 204 Exponent overflow detection circuit 112, 203 Exponent underflow detection circuit 113, 114, 205 AND gate 109 Intermediate result register 115 Multiplication result inhibiting circuit 116 Multiplication result register 117 Operation control circuit 140 Normalized multiplicand mantissa 141 Normalized multiplier mantissa 142 Intermediate exponent 151 Exponent underflow interrupt mask 152 Exponent Underflow Interrupt Report Signal 153 Exponent Overflow Interrupt Report Signal 154 Suppression Signal 200 Operation Exception Detection Unit (Operation Exception Detection Means) 201 Normalized Amount Detection Circuit 2 2 Exponentiation calculation circuit after multiplication 210 Normalized amount after multiplication 211 Normalized amount undetectable signal 212 Exponent underflow early interrupt report signal 213 Exponential overflow early interrupt report signal 301 Mantissa of mandatory Most significant digit value 302 Multiplier Mantissa most significant digit value

Claims (1)

[Claims] 1. A floating-point arithmetic unit for multiplying floating-point data, comprising a post-multiplication normalized amount detection circuit for decoding a normalized multiplicand and a mantissa of a multiplier to detect a normalized amount after multiplication. A post-multiplication exponent calculation circuit that obtains a post-multiplication exponent based on the detected normalization amount after multiplication and the exponent of an intermediate result obtained by adding the normalized multiplicand and exponent of the multiplier, and from the post-multiplication exponent A floating-point arithmetic unit comprising arithmetic operation exception detection means including an exponent overflow detection circuit and an exponent underflow detection circuit for detecting arithmetic exceptions of exponent overflow and exponent underflow.