JPH02115926A - Floating point normalizing and rounding device - Google Patents

Abstract

PURPOSE:To accelerate processing speed and to compress the scale of hardware by generating data for rounding in parallel with the normalization processing of a mantissa. CONSTITUTION:The normalization processing is performed by counting the number of preceding zeros of the mantissa fu111 at a preceding zero detection circuit 11. A barrel shifter 10 is operated based on a counted result, and the mantissa fn120 is generated by performing the normalization processing of the mantissa fu111. Also, the complement of an exponent is performed by operating an adder 23 and a complementor 22, then, the exponent er131 is generated. Also, a rounding processing is performed by generating a bit required for the judgement of rounding from the mantissa fu111 before normalization in a form corresponding to destination size at an LSB/R/S generation circuit 18. Then, the judgement of rounding is performed at a rounding judging circuit 19 based on those bits, and the addition of a rounding signal generated in the above judgement on the mantissa fn120 is performed at an adder 20.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a floating-point normalization and rounding device that performs normalization and rounding of operation results in floating-point arithmetic.

In conventional floating point operations in which normalization and subsequent rounding are performed after an operation, a mantissa overflow may occur when the normalized mantissa is rounded. In this case, further right shift the mantissa and exponent.

Correction by increment operation is required, which hinders high-speed calculation. A conventional floating-point rounding and normalization device that can speed up this correction is disclosed, for example, in Japanese Patent Laid-Open No. Sho Ego-97438. This conventional example detects a case where the normalized result is 1.111・φ・11 and rounding is to be performed, and in this case, the mantissa is not actually rounded, but is set in advance in a separately provided register. 1,000...00 is output, and the exponent part is actually incremented by 1 for correction.

Furthermore, generation of data necessary for rounding processing has been performed by providing means for generating data from the normalized mantissa after the mantissa normalizing means. Conventional examples of this generation means include:
For example, one component of the invention disclosed in Japanese Patent Laid-Open No. 62-226226 is a bit pattern detection circuit placed immediately after the regular barrel shifter. This circuit generates data necessary for rounding processing from the bit one bit lower than the least significant bit of the mantissa of the destination size.

Problem to be Solved by the Invention However, in the former conventional example, when a case where correction is necessary is detected, the correction result can be output immediately for the mantissa part, but the exponent part requires further correction calculation from this point on. Another problem is that a register is also required to store the mantissas 1.000...00 of the correction results.

Furthermore, in the latter conventional example, if the algorithm for generating rounded data is simple, the processing time is not a big problem. However, I.E.E.P.
When a rounding algorithm conforming to the G.754 (IEEE P754) standard is followed, it is necessary to OR the lower bits of the normalized mantissa, which increases the processing time required to generate rounded data. Therefore, when rounding data is generated after normalization as in the conventional example, there is a problem in that the overall processing time becomes longer due to the rounding data generation time.

In view of this, an object of the present invention is to provide a floating-point rounding normalization device that has high processing speed and small hardware scale.

Means for Solving the Problem A first means for obtaining the shift number necessary for normalization by inputting the mantissa part of a floating point number consisting of an unnormalized mantissa part and an exponent part corresponding thereto; A second means takes the mantissa as input and outputs rounding data, and when the mantissa is normalized and the subsequent rounding process is performed from the mantissa and the output of the second means, mantissa overflow occurs. a third means for detecting a case in which the occurrence occurs, and from the outputs of the first means and the third means, determine the number of shifts necessary to make the mantissa rounded into a normalized number, and output this. a fourth means for inputting the mantissa part and shifting according to the output of the fourth means;
A floating point normalization rounding device comprising a correction means for correcting the exponent part according to the output of the fourth means, and a rounding means for rounding the output of the shift means according to the output of the second means. .

Operation The present invention has the above-described configuration, in which the first means calculates the shift number necessary for mantissa normalization, and in parallel with this, the second means calculates the shift number necessary for mantissa normalization.
Find the rounding data from the unnormalized mantissa using the following method. Further, the third means detects, from the bit pattern of the mantissa and the output of the second means, a case where a mantissa overflow occurs when rounding is performed after mantissa normalization. Then, the fourth means determines, from the outputs of the first means and the third means, the number of shifts necessary to obtain a normalized number with the mantissa rounded, and based on this, the The shift means shifts the mantissa, and the correction means corrects the exponent. The rounding means rounds the output of the shifting means using the output of the second means, and finally outputs a rounded mantissa which is a normalized number.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention.

FIG. 11 shows the format of the floating point number input to the floating point normalization rounding device of this embodiment. The format of Figure 11 is IEE Beef 54
(IEEE P754) is a double-precision floating point number that is operated according to the standard and then normalized and rounded, where 110 is an 11-bit exponent e expressed as a bias, and 111 is a weight of 21 to 2-62. bit f+ with
``f-sa, a guard bit (hereinafter referred to as Gu) with a weight of 2-63 2-64, and a round bit (hereinafter referred to as R,
This is a mantissa fu consisting of 57 bits (hereinafter referred to as S) and sticky bits (hereinafter referred to as S). 112 is
The sign bit Su indicates the sign of the mantissa, and 0 indicates a positive number -
1 indicates a negative number.

In FIG. 1, 10 is a barrel shifter that performs normalization shift processing with the mantissa part Ll 11 as input;
The most significant bit shown in Figure 2 has a weight of 2-,
A mantissa f, 120, whose least significant bit is a bit with a weight of 2°62 is output. 11 is f of the mantissa part fu111
This is a leading zero detection circuit which receives all bits except llo and JlRulSu as input, counts the number of leading zeros as shown in FIG. 3, and outputs the result α in binary form. 12
As shown in FIG. 14, the mantissa part f, 111 f1~
a pattern A detection circuit that outputs a pattern As detection signal that becomes l only when f−s+ is all 1, and a pattern As detection signal that becomes 1 only when f, to f−82 are all 1; 13 is the mantissa part f, as shown in FIG.
, pattern BD detection signal that becomes 1 only when fl of 111 is 0 and T O" f-112 is all 1, pattern BSIe4 that becomes 1 only when fl is 01f s" f-23 is all 1. The pattern B detection circuit 14 that outputs the output signal has a mantissa part f, 1, as shown in FIG.
Pattern CD detection signal that becomes 1 only when f4 and fs of 11 are 01f'-+ to f-st and GU are all 1, when f+ and fe are 01f-+ to f-alarm a are all 1 This is a pattern C detection circuit that outputs a pattern C8 detection signal that becomes 1 only when 15, as shown in FIG.
When the externally given Distone/Nissosize signal indicates single precision, the pattern A detection circuit 12 outputs a pattern As detection signal, the pattern B detection circuit 13 outputs a pattern As detection signal, and the pattern C detection circuit 14 outputs a pattern As detection signal. selects the pattern C8 detection signal and outputs it as the pattern A detection signal, pattern B detection signal, and pattern C detection signal, respectively, and if the externally given Distone/Nissosize signal indicates double precision, the pattern The pattern As detection signal is selected from the A detection circuit 12, the pattern BD detection signal is selected from the pattern C detection circuit 13, and the pattern CD1o4 output signal is selected from the pattern C detection circuit 14, respectively. This is a multiplexer that outputs a C detection signal. 16 is a select A signal that inputs the mantissa part f, the upper 3 bits of 111, f11f@, f−+, and becomes 1 only when f1=1, (f+−f++)=(0,
1), the select B signal becomes 1 only if (f+
, fa, f-+) = (0, 0, 1) if and only if 1
The upper 3-bit pattern detection circuit 17 outputs the select C signal which becomes
A sticky bit generation circuit 18 calculates the logical sum of , and outputs a sticky bit signal SS.
f-ass f-*a, f-36, f-s*, G, Ru, Sul The sticky bit signal S, which is the output of the sticky bit generation circuit 17, and the upper 3 bits
Select A, which is the output of the cut pattern detection circuit 16,
This is an LSB, R, S generation circuit which receives a signal from 81C and outputs LSBl R, S signals as shown in FIG. 19 is LSB.

LSB and RlS are the outputs of the R, S generation circuit 18.

The sign pip of the mantissa part Lllll) S, 112, the rounding mode signal given from the outside, and the distone scene size signal are input, and I
Based on the EE P754) standard, the rounding signal Rs (single-precision rounding), the rounding signal Re (double-precision rounding), which becomes 1 when rounding is performed according to the relationship shown in Figure 9, and the logical sum of these signals are calculated. This is a rounding determination circuit that outputs a rounding occurrence signal RND indicating each case where rounding occurs in a signal. 20
is the output of the barrel shifter 10, and the signal R5, which is the output of the rounding judgment circuit 1θ, is at the bit position with a weight of 2-23,
RD performs rounding by adding to bit positions with a weight of 2-62, and outputs a normalized mantissa f, 130, in which bits with a weight of at least 2-62 are 1, as shown in Figure 13. It is an adder. 21 are the leading zero detection circuit 11, the pattern A detection signal, the pattern B detection signal, the pattern C detection signal which are the outputs of the multiplexer 15, the select A1B1C signal which is the output of the upper 3 pit pattern detection circuit, and the rounding judgment circuit 19. From the output rounding generation signal RND, the barrel shifter 10 control signals L*z, L+s, LI, L4, LI, having the relationship shown in FIG.
This is a control circuit that outputs LLlRl, , Rib, and exponent e, 112 correction signals C6, C4, C3, C2, C1, C1, and C. 22 is the output Cs1C4, C3, C2 of the control circuit 21 when the output C of the control circuit 21 is 1.
, CI, and Cm, a complementer 23 uses the output C of the control circuit 21 as a carry input to the lowest order, and has an index e. This is an adder that performs addition of the outputs of 110 and the complementer 22, and outputs a corrected exponent e, 131.

FIG. 2 is a block diagram showing the structure of the barrel shifter 10. In Figure 2, 20. 21.22.23.24
．． 25 is the output L+1L2, La, Le of the control circuit 21
, when Las and La2 are 1, left 1.2.4.8 respectively
．． 16.3 Left shifter that performs a 2-bit shift, 26.2
7 is when the outputs R+a and R+b of the control circuit 21 are 1,
Each of these is a right 1-bit shifter that performs a 1-bit shift to the right.

FIG. 4 is a logic diagram of the pattern A detection circuit 12. Fourth
In the figure, 400 to 407 are exclusive OR gates, and when the bits f+ to f-22 match the bit pattern 141 shown in FIG. 14, the pattern As detection signal of the AND gate 40 output becomes 1. Become. Also, f+~f
-6, bit is the bit pattern 14 shown in FIG.
If it matches 0, pattern A of AND gate 41 output
The s detection signal becomes 1.

FIG. 5 is a logic diagram of the pattern B detection circuit 13. Fifth
In the figure, 500 to 507 are exclusive OR gates, and when the bits f+ to f-23 match the bit pattern 151 shown in FIG. 14, the pattern As detection signal of the AND gate 50 output becomes 1. Become. Also, f+~f
-52 bits are bit pattern 15 shown in FIG.
If it matches 0, pattern A of AND gate 51 output
The s detection signal becomes 1.

FIG. 6 is a logic diagram of the pattern C detection circuit 14. 6th
In the figure, 600 to 607 are exclusive OR gates, and when the bits f+ to f-24 match the bit pattern 161 shown in FIG. 15, the pattern C8 detection signal output from the AND gate 60 becomes 1. Become. Also, f+~G
When the bits of u match the bit pattern 160 shown in FIG. 18, the pattern CD detection signal output from the AND gate 61 becomes 1.

The operation of the floating point normalization rounding device configured as above will be explained.

This device performs normalization processing and rounding processing, and first an outline of the operation of normalization processing will be described. The basic operation of normalization processing is
The leading zero detection circuit 11 counts the number of leading zeros of the mantissa f, 111 as shown in FIG. 3, and operates the barrel shifter 10 based on the count result to detect the mantissa f. 111 to generate mantissa f, , 120, and adder 2
3. Operate the complementer 22 to perform exponent complement and generate the exponent e,131. In addition, the basic operation of rounding processing is to convert the bits necessary for rounding judgment into LSB, R
.

The S generation circuit 8 generates the mantissa fu111 before normalization according to the destination size, and based on these bits, the rounding determination circuit 19 performs rounding determination as shown in FIG. The rounded signal Rs1 generated by
Rn and mantissa f. 120 additions are performed by the adder 20. Size conversion is also performed by taking the destination size into consideration during rounding.

However, the bit pattern of the normalized mantissa fn120 is 1.111...111...(pattern 1
), when this is rounded by the adder 20, the mantissa f becomes 10.000...000, which causes a mantissa overflow and requires normalization again. Therefore, in the present invention, the occurrence of mantissa overflow in this normalization and rounding processing is prevented as follows. In other words, when normalization processing is performed, the bit pattern becomes the above pattern 1.
If the bit pattern shown in the figure is detected by a pattern C detection circuit, a pattern B detection circuit, and a pattern C detection circuit, and this pattern is detected and the rounding determination circuit 19 determines that rounding is to be performed ( When the rounding generation signal RND output from the rounding judgment circuit 19 is 1), the control circuit 21 instructs the right 1-bit shifter 27 of the barrel shifter 10 to shift, so that the bit pattern of f, 120 becomes 0.111 instead of the normalized number. ...111, and when rounded by the adder 20, the mantissa f, 130 becomes 1
．． 000...000 to prevent mantissa overflow due to rounding.

Further, data necessary for exponent correction corresponding to this operation of the mantissa is outputted from the control circuit 21 and added to the exponent eullO to obtain the final exponent e, 131.

Next, the details of the above operation will be described.
The signals can be classified into the following seven types based on the outputs of the upper 3-bit pattern detection circuit 16 (select A signal, select B signal, select C signal).

(al) Select A signal = 1, pattern A detection signal =
If 0.

For these two signals, if the distortion size signal specifies single precision, the bit pattern of the upper 24 bits of the mantissa f, 111 is (f+, fa, f-+, f-
Nitrogen,・”,f−*+,f−i2)=(1,0,11
0, 凰10. ...,! 10.110) or = (1,1,110,110,...,110.11
0) (Note: Ilo indicates 1 or 0.) If the distone scene size signal is double precision, the bit pattern of the upper 53 bits of the mantissa f', 111 is (f+, fs , f-+, f-as", f-s@, f-s
t)=(1,0,110,110,...,I
lo, violet 10) or = (1, 1, 110, 110,..., 110.11
0), and since f I = 1 in both cases, the normalization process is a one-bit shift to the right. Furthermore, since there are no consecutive 1's in the upper 24 bits for single precision and the upper 53 bits for double precision, no mantissa overflow occurs even if rounding is performed. Paying attention to the above, control is performed as follows.

Since the select) A signal is 1 and the pattern A detection signal is 20, the output of the control circuit 21 is in the type a1 column of FIG. Therefore, the right 1-bit shifter 26 of the barrel shifter 10 is operated by the output signal R1a of the control circuit 21 to generate a normalized mantissa f,120. In addition, the adder 23 combines the output signal CO, which is 1, of the control circuit 21 with the index e.
The corrected index er131 is obtained by addition with u110.

Furthermore, the LSB, R, S generation circuit 18 is connected to the select A
Since the signal is 1, the mantissa f before shifting by 1 bit to the right
As shown in the type a column of FIG. 8 from u111, L S B along the distance length size.

From this data, the rounding judgment circuit 19 generates R1S,
Rounding signals Rs and Re corresponding to each rounding mode are output as shown in FIG. 9 according to the distortion date size signal. Then, the adder 20 adds the rounding signal R51R11 and the mantissa f, 120 to obtain a normalized and rounded mantissa L130.

(a2) Select A signal = 1, pattern A detection signal = 1
in the case of.

For these two signals, if the distone scene size signal specifies single precision, the upper 24 of the mantissa r, ttt are (f+, fi, f-+, f-*, ..., f -as
') = (1, l, 1.1..., l, 1), and if the distortion U size signal specifies double precision, then the upper 53 bits of the mantissa r, t t t are CB, fa, f-I, f-tr, ...+ f-st
* f −st ) = (1, 1, 1, l, ..., 1
．． 1), and since f+=1, the normalization process is a one-bit shift to the right. Furthermore, since the mantissa has consecutive 1s, further rounding after normalization will cause a mantissa overflow.

Paying attention to the above, control is performed as follows.

- Since the select A signal = 1 and the pattern AM output signal = 1, the output of the control circuit 21 is in the column of type a2 in FIG. However, whether the output signal R1b is also set to 1 and the right 1-bit shifter 27 of the barrel shifter 10 is also operated depends on the rounding generation signal RND which is the output signal of the rounding determination circuit 19.

That is, if the rounding generation signal RND is 1, rounding is performed, so in order to prevent the mantissa overflow due to rounding, the right 1-bit shifter 27 of the barrel shifter 10 is operated with Rlb of the control circuit 21 output set to 1, and 0.111 is output from the barrel shifter 10. . . . outputs a mantissa f, 120, which is 111. The exponent correction data also corresponds to this operation, and if the rounding generation signal RND is O, CO
is set to 1, and if the rounding generation signal RND is 1, C1 is set to 1,
The adder 23 adds these signals and the index eu110 to obtain a corrected index e r 131.

In addition, since the select A signal is 1, the LSB, R, S generation circuit 18 outputs the mantissa fu11 before shifting by one bit to the right.
As shown in the type a column in FIGS. 1 to 8, L S BlR,S is generated according to the destination size,
From this data, the rounding determination circuit 19 outputs rounding signals R8 and RD according to the destination size signal as shown in FIG. 9 according to each rounding mode. Then, in addition 320, the rounding signal Rs1 Re and the mantissa f are added. By performing the addition of 120, a normalized and rounded mantissa f, 130 is obtained. Further, the rounding determination circuit 19 performs 1 when rounding is performed.
A rounding generation signal RND is output to the control circuit 21.

(bl) Select B signal = 1, pattern B detection signal =
If 0.

For these two signals, if the destination size signal specifies single precision, the upper 25 bits of the mantissa f, 111 are (f+, f@, f-+, f-2.°°°, f- 2z)=
(0,1,110,110,...,110.110)
If the destination size signal specifies double precision, the upper 54 bits of the mantissa r, i 1 t are (f+, Ls, f-+, f-ss°・+ f-s+
+ f-s2): (0, 1, 110, 110,...,
110.110). Also, fI=
Since this is a 01 f review, this data has already been normalized and no normalization shift is required.Also, in the case of single precision, 24 bits of 1 are not consecutive until fII=f-2g, and in the case of double precision However, since the 53 bits of 1 are not consecutive from f@ to f-$2, no mantissa overflow occurs even if rounding is performed. Paying attention to the above, control is performed as follows.

Select) B signal = 1, pattern B detection signal 20, so the output of the control circuit 21 is in the column of type b1 in FIG. For correction, the adder 23 adds the exponent eullO and 0, thereby essentially outputting the exponent e, J110 as it is as the exponent e r 131.

Furthermore, since the select B signal is 1, the LSB, R, S generation circuit 18 generates the LSB, R, S from the mantissa fu111, as shown in the type b column in FIG. From this data, rounding signals R8 and RD corresponding to each rounding mode are output as shown in FIG. 9 according to the destination size signal. Then, an adder 20 generates rounding signals Rs, Rn and a mantissa f. By performing the addition of 120, the normalized and rounded mantissa f, IJO is obtained.

(b2) Select B signal = 1, pattern B detection signal =
In case of 1.

For these two signals, if the destination size signal specifies single precision, the upper 25 bits of the mantissa full are (f+, fs, f-+, f-2s'', f-2g): (
0, 1, 1, l, ..., 1.1), and if the destination size signal specifies double precision, the upper 54 pits of the mantissa fu111 are (f +, f@, f −+, f−*, ..., f−s+,
f-sa): (0, 1, 1, I, ..., 1.l). Furthermore, since fI=0 and f.=1, this data has already been normalized and no normalization shift is necessary. Furthermore, since the mantissa has consecutive 1s, further rounding after normalization will cause a mantissa overflow. Paying attention to the above, control is performed as follows.

Since the select B signal = 1 and the pattern B detection signal = 1, the output of the control circuit 21 becomes the column of type b2 in FIG. In order to prevent mantissa overflow due to rounding, Rlb of the control circuit 21 output is set to 1, and the right 1-bit shifter 27 of the barrel shifter 10 is operated to output a mantissa fl1120 of o, itt . . . 111 from the barrel shifter 10. The exponent correction data also corresponds to this operation, and if the rounding generation signal RND is O, then C
O is set to O, and if the rounding generation signal RND is 1, CO is set to 1, and these signals and the exponent e, 110 are added to the adder 23.
A corrected index e, 131 is obtained.

Furthermore, since the select B signal is 1, the LSB, R, S generation circuit 18 generates the LSB and RlS from the mantissa f, 111, as shown in the type b column in FIG. From this data, the rounding signals Rs1 to Rm corresponding to each rounding mode are output as shown in FIG. 9 in accordance with the distortion cod size signal. Then, the adder 20 adds the rounding signal Rs1 Rn and the mantissa f, 120, thereby obtaining a normalized and rounded mantissa fr130. Further, the rounding determination circuit 19 performs 1 when rounding is performed.
A rounding generation signal RND is output to the control circuit 21.

(cl) When select C signal = 1 and pattern C detection signal 20.

For these two signals, if the distortion size signal specifies single precision, the upper 26 bits of the mantissa f, 111 are (f'+, fs, f-+, f-2,''・,f -s4):
(0,0,1,110,...,110.110), and if the distone date size signal specifies double precision, then the upper 55 pits of the mantissa f, 111 are (f+, f @, f-7, f-2,”・, f-sa, Gu
): (0,0,1,110,...,110.110
), and f+=O1fs=o, f−
Since +=1, the normalization process for this data is a 1-bit shift to the left. Also, in the case of single precision, f-+ ~ f-s
24 bits up to a, 5 up to f-+ to G for double precision
Since 3 bits of 1 are not consecutive, no mantissa overflow occurs even if the mantissa after normalization is rounded. Paying attention to the above points, control is performed as follows.

Since the select) C signal = 1 and the pattern C detection signal = 0, the control circuit 21 is of type c1 in FIG.
The bit shifter 20 is operated to perform normalization. Also, correction of the exponent eullo is performed by operating the complementer 22 with the control signal C which is 1, and using the adder 23 to correct the exponent eul°1.
Processing is performed by subtracting the control signal CO, which is 1, from 0.

Furthermore, since the select B signal is 1, the LSB, R, S generation circuit 18 generates LSBl R1S from the mantissa f, 111, as shown in the type C column in FIG. From this data, rounding signals Rs and RD corresponding to each rounding mode are outputted as shown in FIG. 9 in accordance with the distortion and date size signal. And adder 2
By adding the rounding signals Rs, Ro and the mantissa f, 120 at 0, a normalized and rounded mantissa f, 130 is obtained.

(c2) When select C signal = t, pattern C detection signal = 1.

If the distoneness e size signal specifies single precision, these two signals will be
The 6 bits are (f+, f'i, f-+, f-as°・, f-+a)=
(0+0+1+++..., I, l), and if the distance size signal specifies double precision, then the upper 55 bits of the mantissa f, 111 are (f+, f*, f-+, f- as", f'-it, G,
, ) = (0, 0, 1, 1, ..., 1.1), and since f, = 0, f1 = 0, r-, = 1, the normality of this data is (Basically, this can be done by shifting 1 bit to the left. However, in the case of single precision, f-+ ~
24 bits up to f-24, f-+ to G for double precision
In ut, there are 53 bits and 1 power (because it is continuous, if the mantissa is rounded after normalization, an imaginary mantissa overflow of 1 will occur. Paying attention to the above, control is performed as follows.

Since the select C signal = 1 and the pattern C detection signal = 1, the output of the control circuit 21 is in the column of type C2 in FIG.
It depends on the rounding generation signal RND which is the output signal of . That is, when the rounding generation signal RND is O, in order to prevent mantissa overflow due to rounding, Ll is set to 1, the left 1-bit shifter 20 of the barrel shifter 10 is operated, and the mantissa f of 1.000...000 is generated from the barrel shifter 10. , 120 are output. Also, by setting co and ct of the control circuit 21 output to 1, the adder 23 outputs the index e.
. Subtract 1 from 110 to obtain the corrected index er131. When the rounding generation signal RND is O, mantissa overflow occurs due to rounding, so the barrel shifter 10 does not shift, and the barrel shifter 10 generates a mantissa f of 0.111...111. Outputs 120.

Then, the adder 23 outputs the exponent e, 110 as it is as an exponent e r 131.

Furthermore, since the select C signal is 1, the LSB, R, S generation circuit 18 generates LSBlR,S from the mantissa f 111, as shown in the type C column in FIG. From this data, outputs a rounding signal Rs1 Ro corresponding to each rounding mode, as shown in FIG. 9, according to the distortion e size signal. And adder 2
Round signal Rs1 Rn and mantissa f with 0. By performing the addition of 120, a normalized and rounded mantissa f' of 130 is obtained. Further, the rounding determination circuit 19 outputs a rounding generation signal RND of 1 to the control circuit 21 when rounding is to be performed.

(d) Select A signal, B signal, C signal = O In these signals, the mantissa f and the upper bit of J111 are (f +
, fi, f-+, f-*s...)=(0,0,0,11
0, . Therefore, Gu% R1
If the 11Su bit is also O and the destination size designation signal indicates double precision, the rounding signal Rn output from the rounding determination circuit 19 is O, and no mantissa overflow occurs due to rounding. Paying attention to the above points, control is performed as follows.

Since the select A signal, B signal, and C signal = 0, the output of the control circuit 21 becomes the type d column in FIG. =L32・26+1. +a・2'+Ls・23+La
・L32, LeeLm, L4, L2, L with the relationship of 22+L2・2++L+・2
.

Output as a signal. and control signals Ll, L2, L
4, LII, L+a, L32 are the corresponding left shifters 20~
25 and the mantissa f. , and outputs the normalized mantissa f, 120. Also, the index eu110
The correction is α”Cs・2S+C4・2′+C3・2′+C2
・Control signals C51C4, C3, C2, C8 with the relationship of 22+C+・2'+Cs・2θ
, C@ and C which is 1, eu-α in the adder 23
Process by executing.

Furthermore, the LSB, R, S generation circuit 18 is connected to the select A
1B1 Since the C signal is O, type D in Figure 8
As shown in the column, LSB and R are all O.

The rounding determination circuit 19 outputs a rounding signal R51RD which is 0 from this data. And adder 2
Rounding signal R81RD which is 0 and mantissa f', 120
By performing the addition of , a normalized mantissa f, 130 is obtained.

However, in this case, if the distone size specification signal indicates single precision, the mantissa before normalization r,, itt
Since it is impossible to obtain the bits necessary for rounding judgment from
Formally, the adder 2o performs addition with 0 to obtain the normalized mantissa f, 130, and then inputs this into the device again,
Rounding will be performed.

As described above, according to the invention in this embodiment, the leading zero detection circuit 11 and the barrel shifter 1o are provided to normalize the mantissa ful11, but the upper 3 bit pattern detection circuit 1B, the sticky bit generation circuit 17, and the LSBl By providing the R, S generation circuit 18 and the rounding judgment circuit 19, the mantissa f, 1 before normalization can be calculated in parallel with the normalization process in the barrel shifter 1o.
11 to generate rounding data. In addition, pattern C detection circuit 12, pattern B detection circuit 13, pattern C
By providing the detection circuit 14 and the control circuit 21, it is possible to detect in advance the case where a mantissa part o, - barflow occurs when rounding processing is performed after normalization, and by controlling the number of shifts in the barrel shifter 10, The result of rounding by the adder 20 is always the normalized number. Furthermore, correction of the exponent can be processed in parallel with rounding of the mantissa by one addition/subtraction in the adder 23. Furthermore, new hardware required to realize these processes includes a pattern A detection circuit 12, a pattern B detection circuit 13, a pattern C+yJ output circuit 14, an upper 3-bit pattern detection circuit 18, an LSB1R1S generation circuit 18, and a control circuit 21. , and these can be constructed with simple combinational circuits.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, rounding data is generated in parallel with the mantissa normalization process, and rounding data is generated in accordance with the IEEEP 754 standard. Even if it takes time, the overall processing time will not be long. Furthermore, if the normalized result is rounded, it is possible to detect the case where the mantissa overflow occurs, and in this case, by adjusting the normalization process, this can be prevented. Moreover, the mantissa normalization and rounding processing and the exponent correction processing can be processed in parallel, and the mantissa and exponent can be obtained almost simultaneously.
Its practical effects are great.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a floating point normalization rounding device in an embodiment of the present invention, Fig. 2 is a block diagram of a barrel shifter, Fig. 3 is an input/output relationship diagram of a leading zero detection circuit, and Fig. 4 is a pattern A Logic diagram of the detection circuit, FIG. 5 is a logic diagram of the pattern B detection circuit, FIG. 6 is a logic diagram of the pattern C detection circuit,
Figure 7 is the input/output relationship diagram of the multiplexer, Figure 8 is the LS
FIG. 9 is an input/output relationship diagram of the B1R1S generation circuit, FIG. 9 is an input/output relationship diagram of the rounding judgment circuit, FIG. 10 is an input/output relationship diagram of the control circuit, and FIG. 11 is a format diagram of floating point numbers input to this device. , Fig. 12 is a format diagram of the barrel shifter output, Fig. 13 is a pit pattern diagram of the rounded mantissa, Fig. 14 is a bit pattern diagram detected by the pattern A detection circuit, and Fig. 16 is a diagram of the bit pattern detected by the pattern B detection circuit. FIG. 18 is a diagram of the bit pattern detected by the pattern C detection circuit. IO... Barrel shifter, 11... Leading zero detection circuit,
12...Pattern A detection circuit, 13...Pattern B detection circuit, 14...Pattern C detection circuit, 16...Upper 3-bit pattern detection circuit, 17...
・Sticky bit generation circuit, 18...LSB, R1
S generation circuit, 19... Rounding judgment circuit, 20.23... Adder, 21... Control circuit. Name of agent: Patent attorney Shigetaka Kurino and one other person Fig. Fig. u n (fo to f-wa) Fig. No. - Day 5 Turn 80 on the 1st iris No. 1 exit 1st fig. Seishaku It No. 11

Claims (1)

[Claims] A first means for calculating a shift number necessary for normalization by inputting the mantissa of a floating point number consisting of a non-normalized mantissa and a corresponding exponent; and a third means for detecting, from the mantissa and the output of the second means, a case where a mantissa overflow occurs when the mantissa is normalized and the subsequent rounding processing is performed. and a fourth means for determining and outputting the number of shifts necessary to make the mantissa rounded into a normalized number from the outputs of the first means and the third means; Shifting means that receives the mantissa as input and performs shifting according to the output of the fourth means;
A floating device comprising: a correction means for correcting the exponent part according to the output of the fourth means; and a rounding means for rounding the output of the shift means according to the output of the second means. Decimal normalization rounding device.