JPS61282928A - Floating-point arithmetic unit - Google Patents

Abstract

PURPOSE:To make the arithmetic result of zero at a high speed by providing a means which generates the zero condition of a fixed-point part in accordance with the exponent part of an intermediate result and the fixed-point part of the intermediate result independently of a means which detects the exponent underflow exception. CONSTITUTION:In a mantissa normalization arithmetic part 18, zero bits of an intermediate result register 6 are encoded by an encoder 11' to obtain a normalized counted value, and this normalized counted value is subtracted from the exponent part of an intermediate result register 8 to obtain the zero condition of the fixed-point part by a carry look ahead forecasting circuit 19. If the zero condition is satisfied, the output (zero signal) of the circuit 19 goes to '1', and the arithmetic result of the fixed-point part obtained by a normalization shift circuit 10 is made of zero by an AND circuit 14. Thus, the arithmetic result is made of zero at a high speed evenn if the exponent under-flow exception occurs.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a floating-point arithmetic device, and more particularly to a floating-point addition/subtraction device suitable for quickly zeroing out arithmetic results when an exponent underflow exception occurs. .

[Background of the Invention] A floating point value is composed of three parts: a sign, an exponent part, and a mantissa part. The signs (+) and (-) are expressed as 0°1, the exponent is expressed as a power of 16, and the mantissa is expressed as a hexadecimal number with a decimal point to the left of the most significant digit. Floating point values are fixed length.

In the format of 32 bits per word, the 0th bit is a sign, 1
The 7th to 7th bits are the exponent part, and the 8th to 31st bits are the mantissa part.

For floating point numbers, the most significant digit of the mantissa is 0.1 hexadecimal.
As described above, the mantissa and exponent parts can be adjusted, which is called normalization.For example, when an arithmetic exception occurs as a result of executing a floating-point instruction, a program interrupt is performed.

In a floating-point operation, if the resulting exponent is less than zero and the mantissa is not zero, an exponent underflow exception occurs. At this time, the mantissa part is normalized and the sign and mantissa part show correct values, but the exponent part shows a value 128 larger than the correct value.

Generally, in floating-point addition and subtraction, a normalized count is calculated from the zero detection bit for each digit (generally hexadecimal) of the mantissa part of the intermediate sum, and this normalized count is subtracted from the exponent part of the intermediate sum to detect exponent underflow. Detecting an exception.

In FIG. 6 showing an example of the structure of a conventional calculation result, 17 is an exponent normalization calculation section, and 18 is a mantissa normalization calculation section.

When performing normalized addition, first, in order to check the sizes of the two operands OPI and OP2 of the input register 1.2, the exponent parts of the two operands are compared. If the sizes of the exponent parts of the two operands OPI and OP2 are different, the shift circuit 3 makes the mantissa part of the operand with a small exponent part equal to the exponent part of the operand with a large exponent part. After shifting to the right until , the adder 4 performs algebraic addition, and the intermediate sum of the mantissa part is set in the intermediate result register 5. At the same time, the zero bit of the intermediate sum is set in the intermediate result register 6. On the other hand, the larger exponent part is taken out by the exponent selection gate 7 and intermediate result register 8
is set to

In the mantissa normalization operation unit 18, a normalized shift count value is obtained by encoding the zero bit of the intermediate result register 6 or the mantissa part of the intermediate result register 5 with the encoder 9, and the upper part of the mantissa part is determined by the normalization shift circuit lO. Shift to the left until there are no zeros, and fill in the empty lower digits with zeros.

In the exponent normalization operation unit 17, the zero bit of the intermediate result register 6 is encoded by the encoder 11 to obtain a normalized count value, and in the exponent part adder/subtractor 12,
The normalized count value obtained by the encoder 11 is subtracted from the value of the intermediate result register 8.

If an exponent underflow occurs during subtraction in the exponent adder/subtractor 12 and the exponent underflow mask bit in the program mask (on psw) is set to "1", an exponent underflow occurs. Causes a flow interrupt.

Further, if the exponent underflow mask bit is reset to rOJ, the exponent underflow interrupt is suppressed, and the AND circuits 13 and 14 zero out the calculation results of the exponent and mantissa parts. The calculation result is stored in register 15.
16, respectively.

However, in the configuration shown in FIG. 2, the delay until the exponent underflow condition is detected from the zero detection bit of the intermediate result register 6 and the mantissa is zeroed based on the result becomes long, and the machine cycle of the arithmetic unit is reduced. This is a bottleneck in shortening the length.

For this good luck, 1. For example, as shown in Japanese Patent Laid-Open No. 55-135942, the exponent part of the intermediate sum is decoded, and the decoded output is ANDed with one or several zero detection bits of the mantissa part. A method for quickly detecting an exponential underflow exception is known. However, this method significantly increases the number of gates in order to reduce the number of gate stages required to detect an exponential underflow condition, and the distance to the mantissa postshift calculator increases, resulting in a signal propagation delay. This creates a new problem of increasing size.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an operation result zeroing means that can quickly zero the operation result when an exponent underflow exception occurs in a floating point arithmetic unit.

[Summary of the invention]

The present invention provides a mantissa normalization operation unit that performs bost normalization of the mantissa part, in addition to an exponent underflow exception detection circuit, based on information representing the number of consecutive zero digits from the upper part of the mantissa part of the intermediate sum. A mantissa zeroing logic circuit detects exponent underflow by decoding the required number of shift digits and subtracting it from the exponent part of the intermediate sum, and zeroes the mantissa part if the exponent underflow mask is zero. It is characterized by having been established.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 2 are represented by the same symbols. The difference from FIG. 2 is that the mantissa normalization calculation section 18 is provided with a normalized count encoder 1 bit and a carry look-ahead prediction circuit 19, and instead of the exponent underflow signal from the exponent normalization addition/subtraction circuit 12, the carry look-ahead prediction AND circuit 1
4.

When performing normalized addition, the exponent parts of the two operands OPI and OP2 of input register 1.2 are compared. If the exponent parts of the two operands opt and op2 are different, the mantissa part of the operand having the smaller exponent part is shifted to the right by the shift circuit 3 until the two exponent parts are equal, and then the adder 4 Perform algebraic addition of the mantissa part,
The intermediate sum is set in intermediate result register 5. At the same time, the zero bit of the intermediate sum of the mantissa is set in the intermediate result register 6. On the other hand, two operands OPI.

The larger exponent part of OF2 is set in the intermediate result register 8 via the exponent selection gate 7.

In the mantissa normalization calculation unit 18, the zero bit of the intermediate result register 6 is encoded by the encoder 9 to obtain a normalized shift count value, and in the normalization shift circuit 10, the mantissa part of the intermediate result register 5 has no zero in the upper part. Shift to the left up to 0.0 and fill the empty lower digits with zeros to obtain the result of the mantissa operation. At the same time, the zero bit of the intermediate result register 6 is encoded by the encoder 11' to obtain a normalized count value, and the carry look-ahead prediction circuit 19 subtracts the normalized count value from the exponent part of the intermediate result register 8 to obtain the mantissa part. Find the conditions for zeroing out. When the zeroing condition is satisfied, the output (zeroing signal) of the carry look-ahead prediction circuit 19 becomes ``1'',
The calculation result of the mantissa obtained by the normalization shift circuit lO is A
It is made zero by the ND circuit 14.

On the other hand, in the exponent normalization calculation unit 17, the intermediate result register 6
The encoder 11 encodes the zero bits of , to obtain a normalized count value, and the exponent adder/subtractor 12 subtracts the normalized count value from the exponent part of the intermediate result register 8 to obtain the calculation result of the exponent part. At that time, addition/subtraction HI11
If an exponent underflow signal is generated from 2 and the exponent underflow mask bit is reset to "0", the calculation result of the exponent part is zeroed by the AND circuit 13.

Above, we have explained the case of performing normalized addition.
The same applies to normalized subtraction.

〔Effect of the invention〕

According to the present invention, since the propagation time of the nulling signal from the exponent normalization calculation unit to the mantissa postshift calculation unit is not required at all, even when an exponent underflow exception occurs,
It is possible to zero out the calculation result at high speed. Furthermore, since the number of required gates is smaller than that of the conventional technology, it can be implemented without mounting restrictions. This results in
It is possible to shorten the machine cycle of a floating point arithmetic unit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a floating point arithmetic device according to the present invention, and FIG. 2 is a diagram showing an example of a conventional configuration. 1.2... Input register, 3... Digit alignment shift circuit, 4... Adder, 5, 6.8... Intermediate result register, 9... Normalization shift count encoder, 10...・Normalization shift circuit, 11.11'
...Normalized count encoder, 12...Normalized addition/subtraction circuit, 13.14...AND circuit, 1
5... Index final register. 16... Mantissa final register, 17... Exponent normalization calculation unit, 18... Mantissa normalization calculation unit, 19...
・Carry foresight prediction circuit. Figure 2

Claims (1)

[Claims] (1) Operate two floating point numbers, check the number of consecutive zero digits from the upper part of the mantissa part of the intermediate result, shift the mantissa part of the intermediate result by the number of digits, and obtain the operation result of the mantissa part, In an arithmetic device that subtracts the number of digits from the exponent part of the intermediate result to obtain the arithmetic result of the exponent part, and zeroes the arithmetic results of the exponent part and the mantissa part when an exponent underflow occurs, an exponent underflow exception is generated. A floating-point arithmetic device characterized in that, separate from the detecting means, means is provided for generating a zeroing condition for the mantissa part from the exponent part of the intermediate result and the mantissa part of the intermediate result.