JPS61158725U - - Google Patents
Info
- Publication number
- JPS61158725U JPS61158725U JP4063785U JP4063785U JPS61158725U JP S61158725 U JPS61158725 U JP S61158725U JP 4063785 U JP4063785 U JP 4063785U JP 4063785 U JP4063785 U JP 4063785U JP S61158725 U JPS61158725 U JP S61158725U
- Authority
- JP
- Japan
- Prior art keywords
- input signal
- amplifier
- contact
- level
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Bipolar Integrated Circuits (AREA)
Description
第１図は、本考案の一実施例を示すＩＣパター
ンの平面図、第２図は本考案が適用される直流結
合型のＡＬＣ回路を示す回路図、第３図は従来の
ＡＬＣ回路の制御トランジスタのパターンを示す
平面図、第４図はその断面図、及び第５図は制御
トランジスタと寄生ＰＮＰトランジスタとの関係
を示す回路図である。
主な図番の説明、１…入力信号源、２…抵抗、
３…増幅器、６…レベル制御回路、８…第２制御
トランジスタ、１９，２０…コレクタコンタクト
、３３…第１コンタクト、３６…第２コンタクト
。
Fig. 1 is a plan view of an IC pattern showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a DC coupled ALC circuit to which the present invention is applied, and Fig. 3 is a control of a conventional ALC circuit. FIG. 4 is a plan view showing the pattern of the transistor, FIG. 4 is a cross-sectional view thereof, and FIG. 5 is a circuit diagram showing the relationship between the control transistor and the parasitic PNP transistor. Explanation of main figure numbers, 1... Input signal source, 2... Resistor,
3... Amplifier, 6 ... Level control circuit, 8... Second control transistor, 19, 20... Collector contact, 33... First contact, 36... Second contact.
Claims (1)
増幅する増幅器と、該増幅器の出力信号レベルを
検出するレベル検出回路と、該レベル検出回路の
出力信号に応じて前記増幅器の入力信号を制御す
る制御トランジスタとを直流結合して成るＩＣ化
された自動レベル制御回路において、前記制御ト
ランジスタのコレクタコンタクトと直角方向の分
離領域に沿つて、基体に流れる電流を吸い上げる
為のコンタクトを配置し、該コンタクト接地した
ことを特徴とする自動レベル制御回路。 an input signal source, an amplifier that amplifies the input signal from the input signal source, a level detection circuit that detects the output signal level of the amplifier, and controls the input signal of the amplifier according to the output signal of the level detection circuit. In an IC-based automatic level control circuit comprising a DC-coupled control transistor, a contact is arranged along a separation region in a direction perpendicular to the collector contact of the control transistor to absorb the current flowing through the substrate; An automatic level control circuit characterized by contact grounding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4063785U JPH0513053Y2 (en) | 1985-03-20 | 1985-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4063785U JPH0513053Y2 (en) | 1985-03-20 | 1985-03-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61158725U true JPS61158725U (en) | 1986-10-01 |
| JPH0513053Y2 JPH0513053Y2 (en) | 1993-04-06 |
Family
ID=30549711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4063785U Expired - Lifetime JPH0513053Y2 (en) | 1985-03-20 | 1985-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0513053Y2 (en) |
-
1985
- 1985-03-20 JP JP4063785U patent/JPH0513053Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0513053Y2 (en) | 1993-04-06 |
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