JPS61156975A - Digital synchronizing signal processing circuit - Google Patents

Abstract

PURPOSE:To shorten a time required for pulling in synchronization by forming a gate signal employing a clock burst and avoiding an erroneous detecting pulse from reseting a counter. CONSTITUTION:A burst section of an unique word section of a video signal inputted from an outside section are extracted, inputted to a band pass filter 55 passing at fCK/2, detected by a diode 56, passed to a low pass filter 57 and inputted to a comparator 58. Then, a wave shape of an output point thereof is as shown in a figure (d). A synchronous signal detecter 54 uses a pattern comparator and outputs a detecting pulse when coinciding with a prepared pattern. When a CN ratio is small and an error rate of a transmitting system is large, the detecting pulse is generated in a position in which a signal except for the unique word section should be present, and a probability for performing an erroneous synchronization judging is increased. By taking an AND in an output signal of a synchronous signal detecter and an AND gate 59 by the use of the figure (d) in a gate signal, a correct synchronization condition can be pulled in an extremely short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital synchronization signal processing circuit suitable for receiving television satellite broadcasting.

[Technical background of the invention]

To receive television satellite broadcasts, a receiver must receive and demodulate weak radio waves. therefore,
The CN ratio of the demodulated received signal is quite low, and the receiver is required to operate normally even with such a low CN ratio signal. In order to ensure normal operation of the receiver, it is fundamental to accurately extract the synchronization signal and bring it into a synchronized state. For this reason, in satellite broadcasting, instead of the analog synchronization method used in conventional television signal reception, the adoption of a digital synchronization method with better noise resistance is being considered. As an example of a digital synchronization method, there is a method of inserting a specific digital synchronization pattern, that is, a unique word, with a word length of KK bits in the synchronization period of a television signal, and synchronizing by detecting this, as shown in Figure 2. .

In other words, Fig. 2 (a) is a waveform diagram of a video signal having a conventional analog synchronization signal, in which a horizontal synchronization signal H is generated for each line L.
is inserted, and a vertical synchronizing signal V is inserted every l frame.

Further, in Figure 2 (b), a unique word U is inserted in the horizontal synchronization section, and digital data D is inserted in the section where the vertical synchronization signal ■ existed in the conventional analog synchronization signal.

Also, Figure 2 ((J is a unique word U in the vertical synchronization section)
is inserted. In this case, the position of the original horizontal synchronization signal H becomes data E such as audio.

As a method of detecting this unique word and achieving frame synchronization, there is a circuit that realizes a state transition as shown in Figure 3. In other words, from the unlocked state of 8TO to 5TI-8
In TN, a normal unique word is detected within n frames. If a normal unique word cannot be detected within the STI to STN, the process returns to STO again. If a unique word can be detected during this time, it is assumed to be semi-synchronized and the mode shifts to the next mode.

In the next mode, only when a unique word cannot be detected continuously in m frames from 8tI to StM, it is determined that the synchronization state is not reached and the same operation is repeated again. If a unique word can be detected within m frames, then from that point Scroll m frames again and repeat this.

A circuit that operates in this manner can be realized, for example, with a configuration as shown in the block diagram shown in FIG. That is, when a unique word detection pulse is generated, the frame counter 34 is reset via the switch 31. When the detection pulse passes, the switch 31 is turned off, and the switches 32 and 33 are turned on. The frame counter 34 runs freely and outputs a frame pulse and a reset pulse gate at the position where the original unique word should be. Next 1
After the frame passes, the N counter 35 and the M counter 36 are reset only when the next unique word detection pulse passes through the switches 32 and 0:33 and matches the reset pulse gate described above. AN if the above unique word detection pulse and reset pulse gate do not match
The detection pulse does not pass through the D gates 37 and 311, and therefore the counters 35 and 36 are not reset, and a switch control signal is generated. Then, the switch control signal turns on the switch 31 and turns off the switches 32 and 33 to return to the initial state, and repeats the above-described operation until the detection pulse and the reset pulse match. Further, when both of the above pulses match, the switch 32 is turned OFF.

The switch 33 is turned on and is controlled only by the M counter 36. When the detection pulse passes through the AND gate 38 every frame and continues to reset the M counter, a synchronized state is established and the state of the switch is maintained. Here, if the reset pulse gate and the detection pulse do not match for m consecutive frames, an asynchronous state occurs, and the switch 31 is turned ON.
Switches 32 and 33 are turned off and the above operation is repeated. Furthermore, reliable synchronization is achieved even when the signal has a low CN ratio and the work rate is extremely high.

[Problems with background technology]

In such a synchronization signal detection circuit, a reset pulse (b) is output as shown by the solid line in response to the input signal (a) in FIG. In other words, the above input signal (
The unique word UW of a) is detected and a unique word detection pulse (C) is output, thereby opening the gate through which the reset pulse passes. However, when low C
Since the error rate of the transmission system becomes high, the unique word detection pulse is also output to an abnormal position as shown in (d).

As a result, a reset pulse gate as shown by the broken line in (b) is output, making it impossible to pass the original unique word detection pulse. After the N counter 35 shown in Figure 3 completes N counts, it is initialized and repeats the same operation until it outputs the reset pulse gate at the correct position. For this reason, the synchronization pull-in time becomes extremely long.

Also, turn on the power like a television broadcast.

OFI” or for reasons such as switching channels.

When the synchronization state changes frequently, a long synchronization pull-in time becomes a particularly serious problem.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a digital synchronization signal processing circuit that can shorten synchronization pull-in and synchronization recovery even when the CN ratio is low in television satellite broadcasting.

[Summary of the invention]

Akira Motomohi proposes that in a receiving device that receives a television signal in which a clock burst is inserted for clock reproduction on the side of a unique word, a gate signal surrounding a position where a unique word should be present is generated using the clock burst. It is characterized by the fact that it prevents the frame counter from being reset by an incorrect detection pulse, and shortens the time required to pull in synchronization.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. That is, if we extract the burst part and the synchronization pattern, that is, the unique word part, of the video signal input from the outside, at point A in the figure,
) is the waveform shown. and then convert this signal to half the frequency fcK of the clock burst, that is, ftx/2
When inputted to the band pass filter 55, which passes through.

At the output point (B in the figure), only the burst component is extracted due to the passband characteristic of the bandpass filter 550, and the output characteristic is as shown in FIG. 6(b). This output greatly depends on the frequency characteristics of the bandpass filter, but
Generally, narrowband bandpass filters have an increased amount of delay. Next, when this output is detected by a diode 56 and passed through a low-pass filter 57, an envelope as shown in FIG. 6(C) is obtained at the output point (C in the figure). When this output is input to a comparator 58 having a certain threshold value, the waveform at the output point (D in the figure) is as shown in Figure 6 (d).
It becomes as shown in .

On the other hand, the unique word is latched by the clock fcK via the slicer 52 and input to the synchronization signal detector 54.

Here, the clock fCK is a signal reproduced by the clock reproduction circuit 51.

The synchronizing signal detector 54 uses a pattern comparator and outputs a detection pulse when a pattern matching a pattern prepared in the pattern comparator is input manually.

Here, when the CN ratio is large and the error rate of the transmission system is small, a correct detection pulse is output at the position where the original unique word should be. In addition, if the CN ratio is small and the transmission system has a high rejection rate, the pattern comparator allows errors of up to 3 bits, so detection pulses are generated at positions where signals other than the original unique word should be. The probability of making an incorrect synchronization determination increases. For this reason, initial synchronization takes time.

Therefore, by using a gate signal as shown in Figure 6(d) and performing an AND operation with the output signal of the synchronization signal detector using an AND gate 59, only the output of the synchronization signal detector 4 that occurs during the burst period can be detected. If this pulse is regarded as a pulse for determining synchronization and the synchronization is attempted, the correct synchronization state can be achieved in an extremely short period of time. In this case, if the gate signal is expanded using a mono multivibrator or the like, it becomes possible to gate the synchronization signal more reliably.

〔Effect of the invention〕

As described above, according to the present invention, when the CN ratio is small and the error rate of the transmission system is high, such as in television satellite broadcasting, and when there is only a synchronization signal once per frame, the clock burst can be used for one line. Assuming that the synchronization continues, it is possible to correctly detect the synchronization signal with 525 times the probability compared to when the clock burst is not used. We provide a digital synchronization signal processing circuit that can significantly shorten the synchronization recovery time even when synchronization is lost due to a sudden drop in the CN ratio, channel switching, digital signal ON/OFF, etc. can.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a waveform diagram comparing analog synchronization and digital synchronization, and Figure 3 is a waveform diagram comparing analog synchronization and digital synchronization.
Figure 1 shows the state transition when synchronizing with a conventional device.
Figure 1-4 is a block diagram showing an example of a conventional device, ]・5
The figure shows the output of a unique word detection pulse based on the C/N ratio, and Figure 6 is a waveform diagram illustrating the operation of an embodiment of the present invention. 55... Band pass filter % 56... Diode, 57... Low pass filter, 58... Comparator.

Claims (2)

[Claims] (1) In a device that receives a transmission signal that is sent and includes a unique word of specific pattern data for synchronizing the television signal periodically in the frame period of the television signal, means for generating a detection pulse when data is input; and means for generating a gate pulse generated from a clock burst inserted for clock recovery preceding the unique word and indicating the position of a normal detection pulse; and,
A digital synchronous signal processing circuit characterized by comprising means for allowing the detection pulse to pass if the detection pulse is included in the clock burst gate, and for blocking passage of the detection pulse if the detection pulse is not included. . (2) In the device described in claim 1, the clock burst gate generation means includes a bandpass filter that extracts only the burst component, a diode that rectifies the output of this bandpass filter, and a rectifier of this diode. A digital synchronous signal processing circuit comprising a low-pass filter to which an output is applied and a comparator that compares the output of the low-pass filter with a certain threshold.