JPS5824282A - Control signal transmission system - Google Patents

Abstract

PURPOSE:To reduce errors of a decoded control signal by closing a data gate if >=1 prescribed condition is not satisfied when transmitting the control signal in H pulses during vertical blanking periods of a TV signal. CONSTITUTION:An FSK signal (c) which is extracted by BPF1 and contains a noise is passed through a carrier level discriminating circuit for amplification 2, rectification 3, and voltage comparison 4 to output a signal (f), and also passed through a limiter 5, a frequency discriminating circuit 6, and an LPF7 to output a demodulating signal (d). The signal (f) is supplied to one input terminal of an AND circuit, and the signal is applied to the other terminal through a voltage comparing circuit 9 and a time deciding circuit 10. The output of this circuit 23 is sent to a data gate 11. Further, voltage comparing circuits 15 and 16, an NOR circuit 17, and the AND circuit 18 discriminate whether the absolute value of the output signal of an FSK signal democulating circuit is greater than a certain value at a sampling point. Then, a gate 11 is closed when the carrier level of the signal (f) is less than the certain value, when the signal (d) does not reach an expected value for a certain time, or when the absolute value of the output signal is less than the certain value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that during the vertical blanking period of a television signal,
The present invention relates to a control signal transmission method for transmitting control signals used for program identification, broadcast program operation control, etc.

Conventionally, this type of control signal transmission system uses multi-frequency control in which a control code is formed by a combination of burst-like signals of a plurality of predetermined frequencies during a horizontal synchronization signal during a vertical blanking period of a video signal. A method is adopted in which the signals are superimposed and transmitted, and the receiving side extracts the plurality of frequencies from the received signal, detects the combination of the frequencies, and decodes it. The conventional control signal transmission method described above requires as many sharp bandpass filters as the number of frequencies to be used for extracting each of a plurality of frequencies, and therefore has the disadvantage that the circuit scale becomes large. Furthermore, due to the influence of the delay characteristics of the bandpass filter, it is difficult to narrow the time per bit of the control signal, and therefore the information rate cannot be increased. Therefore, there is also a drawback that the types of control items are severely restricted. .

The purpose of the invention is to solve the above-mentioned conventional drawbacks, to provide a control signal transmission method that can increase the amount of information transmitted and the variety of control items, and that can be realized with a simple configuration without requiring a large number of bandpass filters. Our goal is to provide the following.

The transmission method of the present invention is a control signal transmission method in which a control signal is transmitted between horizontal synchronization pulses during a vertical blanking period of a television signal, and includes a predetermined number of carrier detection bits, a start bit, a data bit, and a stop bit. 9 is superimposed on the horizontal synchronizing pulse pulse during the vertical blanking period, and is sent out to the transmission path and received. In @, the above F8 has a bandpass filter that extracts the signal, and the extracted
a signal demodulation circuit at F8 that demodulates the PSK signal; a circuit that generates a sampling pulse at predetermined time intervals in synchronization with a start bit in the output signal of the signal demodulation circuit at F8;
A control code decoding circuit for identifying the demodulated output of the signal demodulation circuit at F8 by the sampling pulse, and a data gate for connecting the output of the signal demodulation circuit to the control code decoding circuit at F8, the data gate , the carrier level output from the bandpass filter is above a certain value; the output signal of the @code demodulation circuit in F8 is above a predetermined value for a certain period of time; the output signal of the PSK signal demodulation circuit #4 is It is assumed that the circuit is configured to close when at least one of the three conditions that the absolute value is equal to or greater than a certain value at the sampling time is not satisfied.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
Only the receiver side is shown. Further, FIG. 2 is a time chart showing the control code, FSK signal, and signal status of each part on the receiving side used in this embodiment.

That is, the control codes used in this example are as shown in FIG.
) K, positive carrier detection bin as shown) S, .

S! +83, followed by a negative start bit s4, a data bit S, ~SII, and a stop bit sIt
It is composed of. Note that the data bit (sll) is a parity code. Then, as shown in FIG. 2 Φ), during the horizontal synchronizing signal Ha of the vertical blanking period, a signal is superimposed on F8 whose frequency has been shifted in accordance with the logic state of the control code and transmitted. It is desirable that the band of the signal at F8 is set to a band that is less affected by the luminance component of the video signal and the shadow subcarrier, and it is also desirable that the phase of the signal at F8 is continuous. On the receiving side, as shown in FIG. 1, the bandpass filter l receives the signal (i), so the signal C is extracted at F8, and demodulated at y8 by the signal demodulation circuit. Limiter circuit 59 Frequency discrimination circuit 6. Low-frequency P wave device 7
It demodulates the FSK signal C and outputs the demodulated signal d. A signal e whose demodulated signal d has been waveform-shaped by a voltage comparison circuit 8 having a threshold value at a zero crossing point is applied to a shift register 19 and a start bit detection circuit 1612 via a data gate 11. The above signals c, d, and el have waveforms as shown in Figure 2 (Cχ, (d) and (e)).The above signal e has a waveform that includes extra pulses due to axis alignment, but as will be explained later. Thus, the data gate 11 outputs the gate output signal j as shown in FIG. 2 θ).

When the start focus detection circuit 12 detects the start bit S, it sets the flip-flop 13. When the 7 limp flop 13 is set, the counter circuit 14 starts operating and outputs sampling pulses k at fixed time intervals according to the clock of the clock generator 26 (
(See Figure 2)).

The shift register 19Fi The sampling pulse k
The output signal jt of the gate 11 is set and sequentially shifted, converted into serial-to-parallel signals, and sent to the readiness check circuit 20. That is, the shift register 19ti constitutes a control rod coding/decoding circuit. When the parity check is correct, the output m of the check path 20 (see Figure 2)
The control code is loaded into the data register 22 by the output pulse of the AND-path 25 which ANDs the output 11 of the p-lanter 21 (see FIG. 2-)). That is,
In this embodiment, the control code is transmitted to F8 by a signal in a 111-step synchronization method, so there is no need for a bandpass filter for each frequency as in the conventional case, and only one bandpass filter IT is required, which reduces the circuit scale. Although it is small, it is less effective in transmitting a large amount of information.

The data gate 11 is a gate that is opened when the output logic of the AND circuit 23 is -1'' and closed when it is -〇-. has been done.

First, happy 2@(C) extracted by bandpass filter 1
Amplifying circuit 2
．． The signal is inputted to a middle level determination circuit consisting of a current circuit 3 and a voltage comparison circuit 4, and is compared with a specified voltage after amplification and rectification.The level of the signal is determined by F8.
If the normal level is υ, the signal ft-high Vpe/I/(
If the signal f is set to a low level A/(logic 10") and the specified level is small, the signal f is set to a low level A/(logic 10").
As shown in Figure 2 (0), FSK above a certain level
It becomes high level only while the signal is being received. That is, when the time during which the output signal C of the band P wave 8a1 is continuously at or above the specified level is longer than the specified time, the logic becomes "1" during that period.This signal f is output from the AND circuit 2.
3, the data gate 11 is not opened when the signal f is at a low level. Therefore, the data gate 11 is not activated due to noise generated within the signal band at F8, so data errors due to noise can be prevented. Note that the above signal f1
naturally becomes logic 10'' if the output value of the bandpass filter l becomes a low level within a specified time.

Next, the demodulated signal d is compared with the positive threshold g' by the voltage comparator circuit 9 (see Figure 2 (b)), and a signal as shown in Figure 2 (h) is output. .

jM'p! The first positive pulse portion h' of fh corresponds to the aforementioned carrier 41 output bit (3 bits) and has a length of approximately 3 bits. The time judgment circuit 1OFi sets the logic state of the output signal 1 to l'' (high level) when the length of the positive pulse portion hIo of the signal exceeds one redundancy (for example, two focus lengths) (see Figure 2 0).
. The time determination circuit 10 also includes an OR circuit 24, which will be described later.
ν is set by the output of . 4 In the example 4, voltage comparison circuit 9 construction time -1-Il redundancy circuit 10,
The condition of merit is that ``the output of the FaK value code demodulation tunnel is also greater than the expected value for a certain period of time.'' And, if this condition is not met, data goo) 11tIX! !
! I can't get enough of it.

Note that the output of the AND circuit 23 is input to the negative signal OR circuit 24, and the output of the OR circuit 24 resets the time I81 judgment time, so when the signal f becomes low level, the time judgment circuit 100 is reset. The signal 1 also becomes 0'' (see FIG. 2(i)).

In other words, since the signal i is set when the demodulated signal continues, for example, 2 bits long, in F8, there is no possibility that the carrier level determination circuit described above malfunctions due to the video signal, synchronization signal, or other O noise in the television signal. By not opening the data gate 11 even in such a case, erroneous reception is prevented and the detection accuracy of the control signal is improved. The output of the AND circuit 23 opens the data gate 11, and the gate output signal j (see FIG. 2 0) is decoded by the operation described above.

On the other hand, in parallel with the above decoding operation, the demodulated signal d is input to the voltage comparison circuits 15 and 16, and the positive threshold value j' and the negative threshold value j# as shown in FIG. The voltage comparator circuit 15 outputs "m@t" when the positive part of the input signal d is equal to or higher than the threshold value 11, and the voltage comparator circuit 16 outputs "m@t" when the positive part of the input signal d is equal to or higher than the threshold value 11. j", a logic 11" is output. Both outputs are input to an AND circuit 18 via a NOR circuit 17. The sampling pulse k output from the counter 14 is input to the other input of the AND circuit 18. Therefore, the above
When the signal d is below a certain value at the sampling time,
AND circuit 18 output logic is @1'', OR circuit 2
4, the time determination circuit 10 and flip-flops 13.27 are reset, and all data reception operations are stopped. That is, voltage comparator circuits 15, 16 and NO
The R circuit 17 and the AND circuit 18 are configured so that the absolute value of the output signal of the signal demodulation circuit is compared with a certain threshold value at the time of sampling.
good. When the time judgment circuit 1O is reset, the output logic of the AND circuit 23 becomes @0'' (data goo)11
closes. Therefore, according to this embodiment, an unstable demodulated signal whose level is below a predetermined level at the time of sampling is
Since this is blocked by the gate 11, it is possible to prevent the decoded data from being damaged. Furthermore, since it is checked by the parity check circuit 20, errors can be detected more reliably.

In this embodiment, condition A is that "the right carrier level output from the bandpass filter is equal to or higher than a certain value."
In F8, condition B is that the output signal of the signal demodulation circuit is at least a predetermined value for a certain period of time; and condition C is that the glycoside value of the output signal of the FSK signal demodulation circuit is at least a certain value at the time of sampling. Since the configuration is such that all three conditions are detected and if any one condition is not satisfied, the data gate (11) is closed, so the probability that a signal due to noise etc. satisfies all three conditions is extremely low. , the correct control code can be decoded.

However, the present invention does not necessarily require detecting all of the three conditions 1, B, and C as in the above embodiment. For example, simply configuring the gate 11 to be closed when condition A is not satisfied can produce considerable effects. The same applies to conditions B and C. Furthermore, it is also possible to use an arbitrary combination, such as configuring 11 to close when conditions A and B are not satisfied.

In any case, since each of the above three conditions must be satisfied for a normal received signal, errors in received data can be reduced by closing the gate 11 when one or more of these conditions are not satisfied. It produces an effect.

As described above, in the present invention, since the control code is transmitted by a signal to P8, the number of bandpass filters is small, and the circuit scale is small and simple. Furthermore, since the bit length is not limited by the transmission delay characteristics of the bandpass filter, a lot of information can be transmitted using control codes with a short bit length, and many control items can be obtained.

In addition, since the data gate is configured not to open when at least one of the 3il conditions that a normal received signal satisfies is not satisfied, the vA of the decoded control code can be reduced. Furthermore, if all three conditions mentioned above are used, it is possible to achieve an extremely low error probability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing control codes used in the present invention, signals at F8, and signals of various parts on the receiving side. In the figure, 1... bandpass filter, 2... amplifier circuit, 3... rectifier circuit, 4.8, 1, 115.16...
Voltage comparison circuit, 5... Limiter circuit, 6... Frequency discrimination circuit, 7... Low frequency F wave device, 10... Time discrimination circuit, 11-... Data gate circuit, 12...- Start pit detection circuit, 13.27...R, 8 flip-flop, 14.21...counter circuit, 17...N
O'f'L circuit, 1B, 23°25...AND circuit,
19... Shift register circuit, 20... Parity check circuit, 24... OR circuit, 26... Clock generator. Agent Attorney residence 1) Toshi So 2nd Ward Cf) Figure 2 (n)

Claims (1)

[Claims] In a control signal transmission method in which a control signal is transmitted between horizontal synchronization pulses during a vertical blanking period of a television signal, a control code is composed of a predetermined number of carrier detection bits, a start bit, a data bit, and a stop bit. Then, the frequency is shifted by the control code and the signal is superimposed between the horizontal synchronizing pulses during the vertical blanking period and transmitted to 7jF8 □
On the receiving side, there is a bandpass filter at F8 to extract the signal, a signal demodulation circuit at F8 to demodulate the signal to the extracted F8, and a start bit in the output signal of the signal demodulation circuit at F8. A circuit that synchronizes and generates a sampling pulse tube at predetermined time intervals, a control code decoding circuit that identifies the demodulated output of the signal demodulating circuit at F8, and a control code decoding circuit that identifies the demodulated output of the signal demodulating circuit at F8 according to the sampling pulse; and a data gate connected to the encoder/decoder circuit, and the data gate company, the intermediate level output from the bandpass filter is above a certain value: the output signal of the FSKli code demodulator is lower than the scheduled value for a certain period of time or more. , above; and 3, the feed value of the output signal of the signal demodulation circuit is greater than or equal to a certain value at the sampling time point in F8.
A control signal transmission system characterized in that it is configured to close when at least one of the conditions is not satisfied.