JPH02305285A - Frame decomposing circuit - Google Patents

Abstract

PURPOSE:To correctly segment reception data by detecting the number of quantization bits based on received dynamic range information and generating a detection pulse corresponding to a block terminal code based on at least first and second pulse signals. CONSTITUTION:A frame decomposing circuit 22 detects a number (n) of bits based on received dynamic range DR information. A first pulse signal P1 to indicate the position of a block terminal code EOB is generated in accordance with the number (n) of bits. Simultaneously, the pattern of the code in the position where the block terminal code EOB can exist is detected by matching. A second pulse signal L2 to indicate the position of EOB is generated based on this detection output. A detection pulse Pd generated at the timing regarded as the position of the block terminal code EOB is generated from pulses P1 and P2. This pulse Pd is used to correctly segment reception data in each block.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention converts an image signal into a block structure, performs encoding adapted to the dynamic range for each block, and stores additional data and information generated by this encoding. The present invention relates to a frame decomposition circuit applied to a transmission system that transmits quantized codes.

[Summary of the Invention] This invention converts an image signal into a block structure, and converts an image signal into a normalized block structure with a variable number of bits depending on the dynamic range, which is the difference between the maximum and minimum values of pixel data for each block. In a frame decomposition circuit installed on the receiving side of a transmission system that employs coding adapted to the dynamic range that quantizes pixel data, the number of quantization bits is detected based on the received dynamic range information. A first pulse signal indicating the position where the block end code exists is formed from the detected pitch I/number, and a code pattern at a position where the block end code may exist is detected by matching, and this detection output is A second pulse signal indicating the position where the block end code is present is formed based on the block end code, a detection pulse corresponding to the block end code is generated based on at least the first pulse signal and the second pulse signal, and the detection pulse Frame decomposition is done well.

[Prior Art] The applicant of this application filed a patent application in 1973! -) - As described in the specification of No. 266/I 07, the dynamic range, which is the difference between the maximum and minimum values of multiple pixels included in the two-dimensional block 1:], is determined, and this dynamic range is An adaptive encoding device that performs adaptive encoding is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, there is an adaptive encoding device that performs encoding adapted to the dynamic range of a three-dimensional block formed from pixels in areas included in each of a plurality of frames. Proposed.

Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. is proposed.

Coding adapted to the dynamic range described above (ADRC
) is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted. In particular, variable length A and D RC can increase the compression ratio. However, variable length AI)RC poses a problem of error propagation because the amount of transmitted data varies depending on the content of the image. In order to prevent error propagation, a detection signal (block end code) is inserted at the break of each block of transmitted data. A frame decomposition circuit on the receiving side decomposes the received data into blocks by detecting the block end code.

Inserting a block termination code has conventionally been done also in variable length codes such as run-length limited codes and Buffman codes. FIG. 6 shows a code conversion table for Huffman codes. Each number from 0 to 31 is converted into an encoded code with a length of 1 bit to 11 bits. As a simple example, FIG. 7 shows an example of the structure of transmission data when an encoded code is transmitted using eight values as one block. In FIG. 7, a block address indicating the position of a block within one image is added at the beginning, followed by eight values (1, 4, 0, 0, 2, 3, ], etc.).

The interpipe cords of 2) are arranged in sequence, and the block end code EOB is located at the end. The block end 5-one end code EOB is detected by matching bit patterns.

[Problem to be solved by the invention]

With this data structure, if an error occurs during transmission and one bit corresponding to the value O changes from "I" to "0", the seventh
As shown at the bottom of the figure, the inter-tube code of (0101101) is decoded as (li!6), and the subsequent (0100
0) is detected as the block end code EOB. In this way, if an erroneous block end code EOB is detected due to an error, the received data cannot be decomposed into correct block divisions.

A similar problem also occurs when the EOB itself contains an error.

Compared to variable length codes such as conventional Huffman codes, the above-mentioned variable length AL)"RCC encoding has a block termination code E
It has a feature that the insertion position of OB can be predicted from the dynamic range DR, which is an additional code.

Therefore, an object of the invention is to provide a frame disassembly circuit that can correctly detect a block termination code by utilizing the characteristics of variable length ADRC and can correctly extract received data.

[Means to solve the problem]

In this invention, the maximum value MAX and minimum value MIN of a block of a block-structured digital image signal, and the maximum value MA
The dynamic range DR of the difference between χ and the minimum value MIN is detected, and the pixel data in the block normalized by the maximum value MAX or the maximum value MIN is less than the original number of pixels,
In addition, an additional code having dynamic range information encoded into a code signal DT with a variable number of bits n according to the dynamic range l) H and a code signal ■) 1 are sequentially arranged, and the block delimiter is Data to which a block end code EOB having a predetermined pick pattern indicating the block is input is input, and in a frame decomposition circuit that detects the block end code EOB of each block, based on the received dynamic range DR information. The number n of bits is detected, and the first pulse signal P1 indicating the position where the block end code EOB exists is generated from the detected number n of bits, and the block end code F and the code at the position where OB can exist are generated. pattern is detected by matching, and based on this detection output, a second pulse signal P2 indicating the position where the block end code EOB exists is generated, and based on at least the first pulse signal P1 and the second pulse signal P2. A detection pulse Pd corresponding to the block end code EOB is generated.

[Operation] The quantization focus number n of a block can be detected from the dynamic range information which is an additional code in the received data. Since the variable length data is a quantization code DT, the block termination code E added to the end of one block of data is
The location of OB can be predicted. A first position pulse P1 indicating this position is formed. In addition, the block termination code EO
Since B has a specific bit pattern, the block end code EOB is detected by matching, and the second position pulse P2 is formed. These first position pulses P
A detection pulse Pd is generated from both the first position pulse P2 and the second position pulse P2, which is generated at a timing considered to be at the position of the block end code EOB.

Using this detection pulse Pd, the received data can be correctly extracted block by block.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description will be given in the following order.

a, transmitting side, receiving side C1 transmission data d, frame decomposition circuit e, modification a, transmitting side FIG. 1 shows the configuration of the transmitting side of the transmission system to which this embodiment is applied, and is denoted by Digital video data in which one sample is digitized into 8 bits is supplied to the input terminal. Video data is processed by blocking circuit 2.
The arrangement of data is converted from scanline order to block order. One frame or one field of screen is subdivided into two-dimensional blocks of (4×4-16 pixels), for example.

The output signal of the blocking circuit 2 is supplied to a maximum value detection circuit 3, a minimum value detection circuit 4, and a delay circuit 5. Detection circuit 3
and 4 are the maximum value MAχ and minimum value M of the block, respectively.
Detect IN. The delay circuit 5 delays the data for a time to detect the maximum value MAX and the minimum value MIN.

The subtraction circuit 6 calculates (MAX-MIN), and the dynamic range DR is obtained from the subtraction circuit 6. The subtraction circuit 7 calculates the minimum value MI from the video data from the delay circuit 5.
By subtracting N and removing the minimum value, normalized video data is obtained from the subtraction circuit 7. Positive −10=If the difference is removed, the calculation is not limited to the difference from the minimum value MIN, but may be performed by calculating the difference from the maximum value MAX. The dynamic range DR from the subtraction circuit 6 and the normalized video data from the subtraction circuit 7 are supplied to a quantization circuit 8 .

From the quantization circuit 8, a quantization code DT is obtained which is smaller than the original number of bits (8 bits) and has a variable number of bits n, for example, 0, 2, 2.3 or 4 bits. The quantization circuit 8 is
Quantization is performed in accordance with the dynamic range DR. That is, the video data after the minimum value has been removed is quantized again using the number n of quantization bits of the block determined by the size of the dynamic range DR. The number n of quantization bits is increased as the dynamic range DR becomes larger. Quantization circuit 8
is a circuit that determines the number of quantization bits n by comparing the dynamic range DR with a plurality of threshold values, a division circuit that forms a quantization step from this number of quantization bits n and the dynamic range DR, and a quantum It consists of a circuit that divides the video data from which the minimum value has been removed in the quantization step, and rounds down the quotient to form an integer value (quantization code D i ").More practically, dynamic ROM to which range DR and pixel data after minimum value removal are supplied
A quantization circuit 8 is configured.

The dynamic range DR and the minimum value MIN are supplied to parity generation circuits 9 and 10, respectively, and the parity of the error detection code is generated. Further, a block termination code EOB is supplied from an input terminal 11, and the code EOB is supplied to a parity generation circuit 2 to generate a parity error detection code. As an error detection code, CRC
Although a code or the like can be used, this example is simple parity with a 1-bit parity pit added. Further, if necessary, a code having not only error detection but also error correction capability may be used.

The quantization code r)T from the quantization circuit 8 and the dynamic range DR from the parity generation circuit 9.10.12,
The minimum value MIN, the block end code EOB, and an additional code consisting of a parity code related to these are supplied to the framing circuit 13.

In the framing circuit 13, a block address indicating a position within one image is added, and transmission data is generated at its output terminal 14. The parity code may be formed within the framing circuit 13. In addition, for transmission of dynamic range information, maximum value MAX, minimum value M
It is sufficient to transmit two data of IN and dynamic range DR.

b. Receiving side FIG. 2 shows the configuration of the receiving side that is paired with the above-mentioned transmitting side. In FIG. 2, received data input to an input terminal indicated by 21 is supplied to a frame decomposition circuit 22. In the frame decomposition circuit 22, the received data is decomposed by detecting the block end code EOB, and the quantization code DT, minimum value MIN, and dynamic range DR are separated and outputted from the frame decomposition circuit 22. This frame decomposition circuit 22 will be described in detail later.

The dynamic range DR and quantization code DT from the frame decomposition circuit 22 are supplied to the decoding circuit 23. The decoding circuit 23 detects the quantization bits 1 to n of the block from the dynamic range DR, determines the quantization step from the quantization bit number n, and generates the quantization code D.
Multiply T by the quantization step and convert the multiplication output into an integer. It is practical to configure the decoding circuit 23 with a ROM.

The output signal of the decoding circuit 23 is supplied to the adder circuit 24, where the minimum (iMtN) is added, and the adder circuit 24
From this, restored data is obtained corresponding to each pixel. This restored data is supplied to the block decomposition circuit 25, and the output terminal 26 of the block decomposition circuit 25 provides video data in the original order (ie, the order of the scan lines).

C1 Transmission Data (2) Transmission data in this embodiment in which the block is composed of 16 pixels will be explained with reference to FIGS. 3 and 4. As shown in Figure 3, one block of transmission data consists of an m-pit block address and an 8-bit minimum value MI.
Parity pits for N and MIN, 8-bit dynamic range DR and l) Parity bits for R, (16Xn)-bit quantization code DT, 5-bit block end code EOB, and parity bit for EOB are arranged in sequence. It has a data structure.

The number of quantization bits n is (0, ■, 2.3 or 4 bits)
It is.

That is, as shown in the fourth section, in this embodiment, the number of bits in one block is determined depending on the number n of quantization bits. When (n=o), one block of data is (m
+8+8+5) bits, and if (n=1),
If the data of one block is (m+8+8+16+5) bits and (n-2), then the data of one block is (m+8+8+32+5) bits, and if (n=3), the data of one block is (n-2). m+8+8+48
+5) hit, and in the case (n=4), the data of one block is (m+8+8+64+5) bits. As described above, in variable length ADRC, the amount of data per block corresponds to the number of allocated bits n, and the position of the block end code EOB can be predicted on the receiving side.

d. Frame decomposition circuit FIG. 5 shows a frame decomposition circuit 22 that utilizes such characteristics.
An example is shown below. This frame decomposition circuit 22 comprehensively detects the block end code EOB from the three types of detection results. In the first detection method, the dynamic range D
The position of the block end code EOB is determined based on R. In the second detection method, the block end code EOB
A block end code EOB is detected by bit pattern matching at a position where there is a possible pressure. In the third detection method, the position of the block end code EOB of the current block is detected based on whether or not the next block is decomposed.

These three detection methods have different characteristics with respect to errors occurring during transmission.

That is, when the dynamic range DR is error data, correct detection cannot be performed using the first detection method, and the second or third detection method is effective. In addition, if the block end code EOB is error data, the second
Correct detection is difficult with the above detection method, and the first or third detection method is effective. Furthermore, dynamic range DR
and block end code EOB are both error data, the third detection method is effective. Therefore, it is determined which detection method should be given priority based on the error state of the dynamic range DR and the block end code EOB.

In FIG. 5, received data from an input terminal indicated by 21 is supplied to a shift register 32 via a block delay circuit 31 having a delay amount of one block. The shift register 32 is supplied with a bit clock CK. The serial output of the shift register 32 is outputted via the gate circuit 33. A quantization code 1)T is obtained at the output side of the gate circuit 33.

The 9-bit parallel output of the shift register 32 is connected to the latch 34.
supplied to

The latch 34 latches 9 bits of received data using a latch pulse from the latch pulse generating circuit 35. The latch pulse generation circuit 35 is supplied with the count value of the counter 36 . The counter 36 counts the pit clock CK. The launch pulse generation circuit 35 generates a latch pulse for capturing the minimum value MIN and the parity bit when the count value of the counter 36 matches (m-1-9), and also when the count value of the counter 36 matches (m+18). ), a latch pulse is generated to capture the dynamic range DR and parity bit, and the counter 3
When the count value of 6 matches the value from switch circuit /J4, a latch pulse is generated to capture the block end code EOB and parity bit. Further, a counter 37 is provided for counting the number of generated latch pulses by H1.

A detection pulse generation circuit 38 generates a detection pulse Pd indicating a block break based on the detection of the received data no-lock termination code EOB.

That is, position pulses Pl, P2, 1-'3 indicating EOB obtained by different first, second and third detection methods are supplied to the detection pulse generation circuit 38, and the dynamic range D
Detection signal P4 indicating the error detection result of R and]-, OB
and P5, the detection pulse Pd is formed from the position pulse that is determined to be comprehensively correct, as described above.

This detection pulse I)d is supplied to the clear terminals of counters 36 and 37, and these counters 36 and 37 are cleared for each block. Further, the detection pulse Pd is supplied to a gate pulse generation circuit 39, and a gate pulse for controlling on/off of the gate circuit 33 is generated. The gate circuit 33 is turned on only at the timing of the quantization code DT.

The dynamic range DR taken out as the parallel output of the latch 34 is supplied to the ROM 40 and the error detection circuit 41. The number of quantization bits corresponding to the dynamic range DR is output from the ROM 40. Quantization bit number n
is supplied to the addition circuit FIlf43 via a 16x circuit 42 composed of a bit shift circuit. The value of (m+18+6) is supplied to the adder circuit 43.
The output of 3 is a value of (16n+m+18+6). This value is the block end code E of the received block when an error-free dynamic range DR is detected.
It shows the position of OB.

The output signal of the adder circuit 43 is supplied to one input terminal a of the switch circuit 44, and the output signal of the data generation circuit 45 is supplied to the other input terminal a. The switch circuit 44 is controlled by the detection output P4 of the error detection circuit 41, and when there is no error, the input terminal a is connected to the output terminal C, and when an error is detected, the input terminal a is connected to the output terminal C. Ru. The detection output P4 of this error detection circuit 41 is supplied to the detection pulse generation circuit 38.

If the dynamic range DR is error data, the number of quantization hits n cannot be known from the dynamic range I)R, so five pieces of data (m+18+6, m+18
-1-6+16, m+18-1-6+32, m+18
+6 +4.8, m+18 +6 +64) are sequentially generated from the data generation circuit 45. Data indicating the position of the block end code EOB from the output terminal C of the switch circuit 44 is supplied to the latch pulse generation circuit 35, and a latch pulse for latching EOB is formed.

The count output of the counter 37 that is cleared by the detection pulse Pd and counts the latch pulses is supplied to the decoder 46.

When the timing of the latch pulse generation is correct, the latch pulse is generated first to latch the minimum value MIN among the received data of the block, and then the second latch pulse is generated to latch the dynamic range DR. A latch pulse is generated, and a third latch pulse (when there is an error, five scratches 1 from the third to seventh) is generated to latch the block end code EOB. Therefore, MIN and DRlE OB can be separated and taken out by the output signals of the decoder 46 corresponding to these latch pulses. Gate circuits 47, 48, and 49 are provided to which the received data from the latch circuit 34 is supplied,
The minimum values M and IN are taken out from the gate circuit 47,
The dynamic range DR is taken out from the gate circuit 48, and the block termination code 1 and ○B are taken out from the gate circuit 49. Further, the output signal used for the EOB gate of the decoder 4G is the position pulse P1 of the first detection method.
The signal is supplied to the detection pulse generation circuit 38 as a signal.

The block end code EOB (including parity pits) from the gate circuit 49 is supplied to an error detection circuit 50 and a -number output circuit 51. - The number output circuit 51 detects coincidence between the EOB bit pattern from the data generation circuit 52 and the output data of the gate circuit 49. The detection signal of the error detection circuit 50 (“1” when there is no error, “0” when there is an error) and the detection signal of the − number output circuit 51 (−
“1” is supplied to the AND gate 53 when the result is a loss, and “0” when there is a mismatch. The output signal of the A, ND gate 53 is supplied to the detection pulse generation circuit 38 as the position pulse P2 of the second detection method. Additionally, the error detection circuit 50
The detection signal P5 is supplied to the detection pulse generation circuit 38.

The received data on the input side of the block delay circuit 31 is used for the third detection method, that is, the method of detecting the signal P3 indicating the position of the block end code EOB based on whether or not data is extracted in the next block. .

The received data is checked by the test circuits 61, 62, 63, 64 and 65.
supplied to The test circuit 61 is shown surrounded by a dashed line, and the other test circuits 62, 63, 64, and 65 are
Since it has the same configuration as the iB61, its details are omitted. The inspection circuit 61 inspects the detection pulse Pd when the number of quantization bits n is (n=o). The test circuits 62, 63, 64 and 65 are (n=1), (n=2)
, (n-3), and (n=4), the detection pulse Pd is inspected, respectively. The output signals of these test circuits 61 to 65 are
When the detection pulse Pd correctly cuts out the cock, it becomes 1". The output signals of the inspection circuits 61 to 65 are supplied to the OR gate 66, and the output signal of the OR gate 66 generates the detection pulse as the position pulse P3. A circuit 38 is provided.

The test circuit 61 counts the bit clock CK and performs an OR
A counter 67 is provided which is cleared by the output signal of the gate 68. 01 maggate 68 has a detection pulse P.
d and the output signal of the coincidence detection circuit 69 (which is "1" when there is a coincidence) are supplied. The count output of counter 67 is supplied to coincidence detection circuits 70 and 71. -Numerical output circuit 70
has a value of (m+18) (i.e., dynamic range I
) is supplied with the value corresponding to the position of R, and the - number configuration circuit 7
A zero match output is provided to latch 72. - The output signal of the adder circuit 77 is supplied to the number output circuit 71, and - the scattered output is supplied to the latch 73.

The received data from the input side of the block delay circuit 31 is converted into parallel data by the shift register 74, and the shift register 74 converts the received data into parallel data.
The parallel outputs of register 74 are provided to latches 72 and 73. Since the latch 72 latches the received data with the matching output of the minus number output circuit 70, the latch 72 generates a parallel output of a total of 9 pins I· of the dynamic range DR and the parity bit. Dynamic range DR is ROM
75, and the number n of quantization bits is specified from the ROM 75. The output signal of the ROM 75 is supplied to an adder circuit 77 via a 16x circuit 76. The adder circuit 77 has (
m+18-+-6) is supplied, and the adder circuit 7
7 is supplied to a coincidence detection circuit 71.

The coincidence output of the coincidence detection circuit 71 is the block termination code I.
Since it corresponds to EOB, EOB is latched by the latch 73 to which the coincidence output of the minus number construction circuit 71 is supplied. The output signal of the latch 73 is supplied to a coincidence detection circuit 78 and matched with the EOB bit pattern from the data generation circuit 79. - From the number output circuit 78,
An output signal that becomes "1" is generated when the -.

The output signal of the A N D gate 80 is supplied to the OR gate 66 as the output signal of the test circuit 61 . The AND gate 80 is supplied with the output signal of the minus number output circuit 69 .

In the above-described inspection circuit 61, if the detection pulse Pd correctly corresponds to the block delimiter, and in the case of (n-〇), it does not indicate that the block was correctly cut out and returns "1".
generates an output signal. When even one of the two conditions is not satisfied, an output of "1" is not generated from the gate 1-80.

The other test circuits 62, 63, 64 and 65 have the same configuration as the test circuit 61 described above. However, the inspection circuit 62
In this case, the data supplied to the coincidence detection circuit corresponding to the -number construction circuit 69 is set to the value (m+1.8+]6+6), and the inspection circuit 63 supplies the data supplied to the coincidence detection circuit corresponding to the -number construction circuit 69. The data supplied to the output circuit is (m+1.8+32-+-6
), and the data supplied to the inspection circuit 64, the -number construction circuit 69, and the corresponding coincidence detection circuit is (rn+1
8 +4.8 +6), and the test circuit 65, -
The data supplied to the matching detection circuit corresponding to the number output circuit 69 has a value of (m+18+64+6). Therefore, when the block is correctly extracted by the detection pulse Pd, an output signal of 1'' is generated from any of the test circuits 61 to 65.
5 does not need to be configured independently, and -26= may be configured to share a common part.

EOB position pulse P1 generated by the first detection method and EOB position pulse P generated by the second detection method described below.
EOB position pulse P3 generated by the second and third detection methods
are supplied to the detection pulse generation circuit 38, and detection pulses P4. P5 is supplied to the detection pulse generation circuit 38. By comprehensively combining these, a detection pulse Pd indicating the most probable block separation is formed.

e. Modification The present invention is a variable length A D in which regions belonging to a plurality of temporally consecutive frames constitute a three-dimensional block.
It can also be applied to R and C, and can also be applied to an encoding method that performs frame dropping when a three-dimensional block is a static area.

〔Effect of the invention〕

According to the present invention, when the additional code and quantization code generated by variable length A and D RC are transmitted with a block end code added to each block, the block end code can be detected correctly. Therefore, the frame decomposition operation can be performed correctly.

[Brief explanation of the drawing]

FIG. 1 is a Brookock diagram of the transmitting side of an embodiment of the present invention.
FIG. 2 is a block diagram of the receiving side of an embodiment of the present invention, FIGS. 3 and 4 are route diagrams used to explain transmission data, and FIG. 5 is a block diagram showing the configuration of a frame decomposition circuit. FIGS. 6 and 7 are route maps used to explain conventional variable length codes. Explanation of main symbols in the drawings 21: Input terminal for received data, 22: Frame decomposition circuit, 36.37.67: Counter, 38: Detection pulse generation circuit, 40.75: ROM that generates quantization pin number. , 41
．． 50: Error detection circuit.

Claims (1)

[Claims] A dynamic range of the difference between the maximum value and minimum value of the block of the block-structured digital image signal and the maximum value and minimum value is detected, and the dynamic range of the difference between the maximum value and the minimum value is detected, and the Pixel data in a block is encoded into a code signal with a variable number of bits less than the original number of bits according to the dynamic range, and an additional code having information on the dynamic range and the code signal are sequentially distributed. At the same time, data to which a block termination code having a predetermined bit pattern indicating the delimitation of the blocks is added is inputted, and a frame decomposition circuit detects the block termination code of each of the blocks. Detect the number of bits based on the range information, generate a first pulse signal indicating the position where the block end code exists from the detected number of bits, and detect the position where the block end code may exist. detecting a code pattern by matching, and generating a second pulse signal indicating the position where the block end code exists based on the detection output; and based on at least the first pulse signal and the second pulse signal. A frame decomposition circuit configured to generate a detection pulse corresponding to the block end code.