JPS6115593U - Clock circuit structure - Google Patents
Clock circuit structureInfo
- Publication number
- JPS6115593U JPS6115593U JP10088784U JP10088784U JPS6115593U JP S6115593 U JPS6115593 U JP S6115593U JP 10088784 U JP10088784 U JP 10088784U JP 10088784 U JP10088784 U JP 10088784U JP S6115593 U JPS6115593 U JP S6115593U
- Authority
- JP
- Japan
- Prior art keywords
- board
- circuit board
- lead
- insertion holes
- circuit structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の実施例を示す図面である。
第２図、第ｊ図、第４図は本考案の実施例を示す図面で
ある。
第５図は本考案のリード基板を示す。１・・・・・・主
回路基板、２・！・・・・副回路基板、３・・・胃スペ
ーサ、４・・・・・・はんだ付、５・・・・・・導通ピ
ン、６・・・・・・リード基板。FIG. 1 is a drawing showing a conventional embodiment. FIG. 2, FIG. J, and FIG. 4 are drawings showing embodiments of the present invention. FIG. 5 shows the lead board of the present invention. 1... Main circuit board, 2...! ... Sub circuit board, 3 ... Stomach spacer, 4 ... Soldering, 5 ... Conductive pin, 6 ... Lead board.
Claims (1)
り、前記主回路基板と前記副回路基板には平面的同位置
に前記リード基板挿入穴が少なくとも２個以上設けられ
、該挿入穴に箭記リード基−板が挿入され、はんだ付け
により固定されてお該リードフレー云は、導通、はんだ
付される銅はくと該銅はくを保持する絶縁基板より成り
、銅はくが２−個以上連続して形成されていることを特
徴とする時計の回路構造。It consists of at least a main circuit board, a sub-circuit board, and a lead board, and the main circuit board and the sub-circuit board are provided with at least two lead board insertion holes at the same position in plan view, and the lead board insertion holes are provided in the insertion holes. A board is inserted and fixed by soldering, and the lead frame is made of a conductive, soldered copper foil and an insulating substrate that holds the copper foil, and there are two or more copper foils. A clock circuit structure characterized by being formed continuously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10088784U JPS6115593U (en) | 1984-07-04 | 1984-07-04 | Clock circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10088784U JPS6115593U (en) | 1984-07-04 | 1984-07-04 | Clock circuit structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6115593U true JPS6115593U (en) | 1986-01-29 |
Family
ID=30660328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10088784U Pending JPS6115593U (en) | 1984-07-04 | 1984-07-04 | Clock circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6115593U (en) |
-
1984
- 1984-07-04 JP JP10088784U patent/JPS6115593U/en active Pending
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