JPS61155778A - Inspection of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an efficient inspection method, by testing the output of a ROM at a specified address of a microcomputer and the output of an instruction PLA which translates the output data at the address into an internal control signal at each one cycle through an internal path. CONSTITUTION:Address selection information is inputted into a ROM5 at a clock CLK1, output information of an instruction PLA test inputted at a clock CLK2. At a clock CLK3, data of the ROM is outputted to an internal path from the ROM5 while being inputted to the instruction PLA6 and at a clock CLK4, it is outputted to the internal path from the instruction PLA6. The output of an instruction test is outputted to the internal path and can be tested in a short time. In parallel with the ROM test, an instruction PLA can be tested thereby achieving the efficiency and reduction of the test.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applied to ROM (Read Only Memory).
), RAM (Randow Acaesg Memo
ry), ROM and instructions for a 1-chip 7'W-r microcomputer with a CPU! PLA
(Programmable LogicArray) output test method.

Conventional technology Conventionally, R built in a single-chip microcomputer
The output test for the OM was performed by inputting address information into the address selection circuit of the ROM and checking the output of the ROM, and the shift back 1 method was used for the output test for the PLA. The shift balance method is a method in which the output of the instruction PLA is turned off once, and the result of the instruction test is output one by one for each machine cycle, and the ROM test and the instruction PLA test take a long time.

Problems to be Solved by the Invention The present invention eliminates these drawbacks, and makes it possible to efficiently perform ROM output tests and instruction PLA output tests by simply adding a small number of test circuits within the chip. This is the purpose.

Means for Solving the Problems The present invention provides an RO of a predetermined address of a microcomputer.
A raw conductor whose purpose is to test the output of M and the output of an instruction PLA that translates the output data of its ROM or the output data of a previous address as an internal control signal every cycle via an internal bus. This is a method for testing integrated circuits.

Function: In order to output the instruction test output to the internal bus at the timing when the ROM data is not output, the ROM
In parallel with the test, the instruction PLA can be tested. According to this method, the output of the instruction test is output to the internal bus, so the test can be performed in a shorter time than the conventional shift buffer method. Also ROM
Since you can test the instruction PLA in parallel with the test, you can measure the efficiency and shortening of the test.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation timing diagram thereof. The present invention will be explained in detail using FIGS. 1 and 2.

A ROM address is input from port 1 to address bus 2 at the timing of clock CLK1 of the first cycle. R
OM address information is input to the ROM address selection circuit 3. The ROM data is output to the data bus 4 at the timing of the clock CLK1 of the second cycle. RO at the timing of the second cycle clock CLKa
M data is output to port 1 and input to instruction PLA. , second cycle clock C
At the timing of LK1, the next ROM address is input. The ROM data input to instruction PLAK at the timing of clock CLK3 in the second cycle is translated into an internal control signal by instruction PLA. The instruction PLA output information input from the boat 1 at the timing of CLK2 in the second cycle is input to the control circuit via the data bus 4, and the output information of the instruction PLA is sent to the address bus 2 and the data at the timing of clock CLK4 in the second cycle. It is divided into buses 4 and output to port 1. Instruction PL
Data corresponding to the number of internal buses is outputted from A, and the remaining outputs are outputted at the timing of the next clock CLK4.

FIG. 2 is a diagram showing the timing of an embodiment to which the present invention is applied. Clock CLK1 inputs address selection information to ROM5, clock CLK2 inputs instruction PLA test output information, clock CLK3 outputs ROM data from ROM5 to the internal bus and is also input to instruction PLAe, and clock CLK4 inputs instruction PLA test output information. The test input of the instruction PLAe, which is output from PLA6 to the internal node, is from ROM5.
Since the output data of is used as is, there is no need for new input from boat 1. Furthermore, since the output of the instruction PLAs is output to the internal bus, testing can be performed in a shorter time than in the conventional shift buffer method. Since the instruction PLA test is performed in parallel with the ROM test, there is no need to provide a special test time for the instruction PLA.

If 24 internal buses are used, instruction P
Considering only the LA output test, the instruction PLA output can be tested simultaneously for the number of internal buses, so the time is reduced by 1 compared to the conventional shift balance method.
/24, which improves efficiency.

As described in detail, according to the present invention, the output of the ROM and the instruction PLA are inspected via the internal bus, and the instruction PLA is tested within the ROM test cycle, thereby reducing time. In addition, there is no need to provide a large number of test circuits, and the ROM and instruction PL of a single-chip microcomputer
It can have a great effect on the A test.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the timing of an embodiment to which the present invention is applied.

Claims (1)

[Claims] The output of the ROM at a predetermined address of a microcomputer having ROM, RAM, and CPU, and the output of an instruction PLA that translates the output data of that ROM or the output data of a previous address as an internal control signal are transmitted via an internal bus. 1. A method for testing a semiconductor integrated circuit, characterized in that the test is performed for each cycle.