JPS61153716A - Microcomputer control device - Google Patents

Abstract

PURPOSE:To shorten the time extending from turn-on of a power source to initializing, by initializing simultaneously each CPU by an external signal, in an arithmetic unit having a main CPU and plural sub-CPUs. CONSTITUTION:A title microcomputer control device is provided with a main CPU1 for executing a control of the whole circuit of said device, and a sub-CPU 2 which is operated by a control signal from this main CPU1, and provided with an input switch 3 for starting an initializing program of the main CPU1 and the sub-CPU2. In this regard, while there is no interruption, a pull-down resistance 4 for stabilizing it to an 'L' levle is provided on an interruption terminal of the sub-CPU2. In this state, when the input switch 3 becomes on, an all clear terminal of the main CPU1 becomes an 'H' level, and the main CPU1 is initialized. Also, at the same time, the interruption terminal of the sub-CPU2 also becomes an 'H' leve, an interruption processing program is executed, and the initializing is ended.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an initialization method in an arithmetic unit constituted by one or more CPUs.

[Conventional technology]

In an arithmetic device configured with one or more CPUs, stable operation of the arithmetic device cannot be achieved unless each CPU and other elements are initialized after power is turned on.

Conventionally, in an arithmetic unit having one or more CPU'), initial settings are performed using a circuit as shown in FIG. 2 (tL). Here, it is the main ○ptr that controls 21 circuits. No. 22 is a sub-CPU whose operation is controlled by control signals from the CPU. 23 is an input switch for initializing the main CPU 21; Reference numeral 24 denotes a control signal that is output as a precaution to initialize the sub-CPU 22 when the main CPU 21 is initialized by the signal from the input switch 23. A control signal 25 is output to notify the main CPU 21 that the secondary cpty 22 has been initialized. Here, from Fig. 2(b) K, the second
To explain the operation in detail, first, when the input switch 23 is turned on, the initialization program written in the program area inside the main CPU 21 is executed to initialize itself. When the initial setting of itself is completed, it sends 24 control signals to the 22 sub-OFs contained in the program area l'c111 inside the main CPU 21.
υExecute the initial setting program. 22 vice apIl
When the initialization is completed according to the boot program, r sends back the signal 25 to the main 0PUK of 21 to notify the end of the initialization. Due to this busy schedule, each CPU was initialized.

[Problem that the invention seeks to solve]

However, in the conventional technology described above, when the device has one or more CPUs, it takes time from turning on the power until completing the initial setting bZ. The user must carry a program for initializing other apUs in the program area that the main OF■ has internally, and the program capacity of the main OPυ decreases. Furthermore, since the secondary OPυ may malfunction, there is a problem in that the main CPU must have hardware and software for managing the operating status of the secondary OFH. Therefore, the present invention is intended to solve this problem, and its purpose is to provide a simple structure for each CPU without affecting the internal storage capacity of the main CPU.
pUK provides simultaneous initialization.

[Means for solving problems]

Consisting of a main CPU that controls the entire arithmetic unit, and one or more sub-OPHs whose operations are controlled by control signals from the main CPU and whose initial setting means within the sub-CPU can be activated by external signals. The nine arithmetic units are busy and each CPU't? The present invention is characterized in that it has an initial setting means for performing simultaneous busy initial setting.

[Effect]

According to the above-described configuration of the present invention, the initial setting means sends each CPV busy initial setting signal to each CPV.
At the same time, r completes the initial setting by its own initial setting means.

〔Example〕

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is a circuit diagram of a microphone dicombinator control device according to the present invention. 5 main CPUs control the entire circuit.
It is. <13, which is a sub-C+PU operated by a control signal from the main CPU of 2 and 1, is an input switch for starting the initial setting program of the main optr of 1 and the sub-0PtJ of 2. Reference numeral 4 denotes a pull-down resistor that stabilizes the interrupt terminal of the sub CPU 2 at the "L" level while there is no interrupt.

3 is a flowchart showing the operation procedure of the microcomputer control device of the present invention.

To explain the operation according to the flowchart, first, when the 30-input switch is turned on, the AO (all clear) terminal of the main CPU goes to the H9 level, and the main CPU is initially powered up. Please make sure that the λ terminal is stable to the sum of the resistances of 4 until then.
'Level Tonal.

Since the sub CPU is busy, it executes the interrupt/exit processing program and completes the initial setting. This allows two CPUs
The initial settings are completed at the same time.

FIG. 4 is a diagram of a tide gauge constructed by actually using the micro combinator control device of the present invention as an application example of the present invention. Here, the tide gauge refers to the internal (F)R tide data necessary to calculate low tide and high tide times in each region.
OM, RAMIC 1 is selected and displays the low tide, high tide time, tide level, etc. at the set time of the dangerous area.

41 is a 4-bit CPU that controls the system, such as clock functions and display, and tidal calculation control. Reference numeral 42 denotes an 8-bit sub-CPU for calculations that reads and reads tidal data and performs tidal calculations in each region. 43 is O of 41 and 42
This is an input switch to which Fσ is initially set. By turning on this switch, the all clear terminal of the main CPU 41 goes to the #H9 level, so each function is unconditionally stabilized in its initial state. ! At the same time, the 42nd sub-CPU goes to the "L" level due to the pull-down resistor of the 44th one, and the NM, which is the unconditional interrupt/exit terminal, goes to the "H" level. Then, the 42 sub-CPU receives a -conditional interrupt-
Friend's command crab S to handle LL transfers the busy address control. Since this is busy, the sub-CPU 42 executes this instruction and sets all functions to the initial state. This is 4
This means that cpσ of 1 and 42 are simultaneously busy initialized.

Further, 45 is a ROM that stores a tidal calculation program and regional data. 46 tidal calculation results etc. are stored and b<RAM. 47 is 45 ROM, 46 RA
This is an address decoder that sets the address for writing and reading data of M. On the 4th, there is a display device that shows the results of tidal calculations, such as 1 time. 49#: is the switch 9 which controls the tidal needle.

It should be noted that the embodiments listed here are merely examples.

〔Effect of the invention〕

The present invention is configured so that one or more CPUs such as 5 or more can be initialized at the same time.
Since the PUs are initialized at the same time, it does not take time hζ from power-on until the initialization is completed. According to the present invention, there is no need for a program for initializing the secondary CPU'1 in the program area within the main apσ car, so the program area of the main CFH can be utilized without waste.

Further, with a very simple circuit configuration, stable operation can be performed immediately after power is turned on. This has the effect that initial settings can be made without incurring a large load due to malfunction of the sushi sub cptr.

[Brief explanation of the drawing]

tJ/E1 Figure 1 is a configuration diagram of a microphone 2 combiator control device according to the present invention. Figure 2) is a configuration diagram of a conventional initial setting circuit, and Figure 2) is a flowchart showing the operation of IE2 Figure 6). Figure fj/L3 is a two-chart showing the operation of the microcombi controller of the present invention. FIG. 4 is an operational diagram of a tide meter constructed using the microphone-combiator control device of the present invention.
・Main OFσ 2...Sub CPU 3...Initial setting switch 4...Pull-down resistor or higher

Claims (1)

[Claims] It is composed of a main CPU that controls the entire arithmetic unit, and one or more sub-CPUs whose operation is controlled by control signals from the main CPU and whose operation is capable of activating initial setting means within the sub-CPU by external signals. 1. A microcomputer control device comprising an initial setting means for simultaneously initializing each CPU using an external signal in an arithmetic unit.